TW201227745A - Development system for a flash memory module - Google Patents

Abstract

A development system for a flash memory module is disclosed. The development system includes a transporting path switch and a flash memory emulator. The transporting path switch coupled in serial on a signal transporting path between a memory controller and a flash memory and receives a debug enable signal. The flash memory emulator receives at least a control command from the memory controller through the signal transporting path. The flash memory emulator phrases the control command and generates at least an emulating response data correspondingly. The flash memory emulator further transports the emulating response data to the memory controller through the signal transporting path.

Description

201227745

36327twf.doc/I VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a flash memory development system. [Prior Art] Flash memory is a programmable (only memory) (rea (j oniy memory, R〇M)), which allows it to be erased multiple times and updated. In the case of debugging for flash memory and its memory controller, 'Fundamental development is done using the development system. In the conventional technical field, this is about flash memory. The module development system can be constructed using a logic analyzer (L〇gicai Anaiyzer, LA) or a universal asynchronous transceiver _versal AsynehiOn() us Receiver/Tmnsmitter, UART). The above-mentioned conventional practice of using a logic analyzer can provide relatively detailed debugging data, but it is quite expensive in price _. In addition, logic analyzers are not able to provide long-term anger records. It is not a good choice. In the technique of riding an asynchronous transceiver, the error-detection record generated by it cannot be correlated with the occurrence time of the error. In addition, the Universal Asynchronous Transceiver also has a recording function for the number of debug records. Of course, in addition to the two methods mentioned above, the prior art also proposes a variety of different alternatives for the debugging and monitoring of the flash memory module. However, there is no satisfactory solution in terms of both cost and efficiency. . Therefore, the establishment of an effective flash memory module development system,

201227745 36327twf.doc/I is also a topic that designers in the field value. SUMMARY OF THE INVENTION The present invention provides a flash memory memory. The present invention proposes a flash memory embedding simulator. The transmission path is cut; == to the second and the control command is interpreted and the response control command is sent to the second channel. The fourth is transmitted through the signal to simulate the response data to the memory controller. The transmission path switch is transmitted by the signal: the transmission path to the memory: = one of the ones - by the light connection to one of the real, the above-mentioned flash memory simulator is more host End / used to transmit at least the status information of Wei Cun control (4) to I Ming - in the embodiment, the above host side is more flashed

201227745 36327twf.docA The memory simulator and the signal transmission path are used to transmit at least one data signal to and from the δ ** memory controller according to the non-flash memory control command. In an embodiment of the present invention, the host terminal further sets a debug error detection mode, and causes the flash memory simulator to generate debug test data as an analog response data according to the status information and the debug test mode. And transferred to the memory controller. ― In the tenth embodiment of the invention, the memory controller is based on the solid $ y, checking whether the flash memory emulator transmits the flash memory access, and the memory is accessed according to (4) memory access. The demand for access is quickly sent to the flash memory emulator by the flash memory access request k described above in the main embodiment 10. In the embodiment of the present invention, the above-mentioned information is obtained to obtain backup status data. The host side of Norwegian used to store the status information to transmit the backup status. 4 ^(4)(4) The number of the working state of H = the path: the letter provided in the converter _ a variety of two between the simulator =, flash memory and flash flash memory simulator to the '艮己二action. And through the use of the transmitter to monitor and debug the action. A method of memory control that enhances the cost competition of products. = To make the above features and advantages of the present invention more obvious and easy to understand through the use of blame instruments or complexities.

201227745 36327twt.doc/I The embodiment is described in detail with reference to the accompanying drawings.

I [Embodiment] * i First, referring to FIG. 1, FIG. 1 is a schematic diagram of a development system 100 of a flash memory module according to an embodiment of the present invention. The development system 1 includes a transmission path switcher 110 and a flash memory emulator 12A. The transmission path switcher 110 is connected in series between the memory controller 1 of the flash memory module and the signal transmission path of the flash memory 50. The flash memory emulator 120 is coupled to the transmission path switch 11 to receive at least one control command CTRL s from the memory controller by the signal transmission path, and interpret the received control command CTRLS in response to the control. Command CTRLS to generate at least one simulated response data. The flash memory emulator 120 transmits the analog response data to the memory controller through the signal transmission path. The above signal transmission path includes transmitting the control ί command CTRLS transmitted from the memory controller 11 to the flash memory emulator ι2 and the shutter. In addition, the transmission path control further includes transmitting one of the analog response data generated by the flash memory simulator 120 corresponding to the control command CTRLS and the actual response data generated by the flash memory 50 to the memory, and controlling H 110. Here, the 'transport path switcher 11() receives the error-initiated k-th DEBEN and selects the explicit response data generated by the fast-flashing suffix class If 12G or the flash memory 5 依据 according to the debt error start signal debEN. The actual response data is passed back and forth to the memory controller ι! 〇. Specifically, when the debug start signal DEBEN indicates that the debug action is initiated, the transit path switcher 110 selects to transmit the flash memory emulator 201227745

The analog response data generated by 36327twf.doc/I 120 is passed back to the memory controller ii〇. On the contrary, if the debug start signal DEBEN indicates that the debug action is turned off, the transfer path switcher 110 selects the actual response data generated by the transfer of the flash memory 5 to be transferred back to the memory controller 11A.

The flash memory emulator 120 is designed to include all functions of the flash memory 5〇. Simply put, when the memory controller 1 〇 快 快 ^ ^ ^ 写 写 ’ 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些Phase (10), when the memory control (four) 1 〇 send read command to the flash memory is transferred to the flash memory money l2G, the flash memory simulates the H 12G back to transfer its stored (four) material to the memory controller Please note that the debug start signal DEBEN can be generated by the flash memory emulator 120. In addition, the flash memory emulator 120 also provides an operation of connecting to the external host terminal 3G and data transmission according to the transmission interface. That is to say, the flash memory emulator 120 can transmit one or more of the flash memory modules to the host terminal through the connection interface with the host terminal 3G. . In addition, the flash memory simulator can also use the connection provided by the silk receiver _ 来 to perform the flashing (four) mode (four) row phase. In this example, the error start signal plus dirty can also be 2 Dalai started command, and the flash memory phantom (4) 12 machine 0 = 生 曰 曰 1 1 1 1 1 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 _ Γ ', the host side 30 can be a personal computer or other electronic device with the same class 51 data processing capabilities. 201227745

36327twf.doc/I In this example, ^ § 己 儒 儒 模拟 simulator 120, can be received by the signal transmission path provided by the basin knife 11G 二 ί 岐 岐 « L «This traffic periodicity Transfer to host side 30. The host side 3 (4) compares one or more traffic flows to monitor the flash padlock control (4) and the access location of the flash memory 5G. One or more data signals are sent at 12° with the flash memory simulator. Among them, the mistranslation and the flash command and the memory controller 10 flash memory control age ^ can have =t. Therefore, the two-way communication is performed by the non-device 1Q, and the effect of the machine is interfered with the memory control. In addition, the non-decision does not result in the definition of the existing flash memory module, and the domain end Γ 纽 ( (4) command can (4) the designer can identify itself. Both the heart and the sugar control 1G can detect the error two: face two = can also communicate with the state and macro macro # two flash memory simulator 120 transmitted state μ, Τ 2; 2: memory controller The data is sent to the memory controller 1 to generate a test mode. For example, the host terminal 30 sets the test mode. When the fast ^i ten pairs of addresses 0x0020 read the data for the error detection, the memory control received by the memory model 120 201227745

When the control command CTRLS transmitted by the 36327twf.doc/I device is just for the address 〇χ〇〇2〇, the flash memory emulator 120 changes the data of the existing address 0x0020 that should be transmitted. (for example, 0xAA) is the debug test data 0x55 as the analog response data and transmitted to the memory controller. The memory controller 10 is then observed to receive the response from the expected response data to observe the memory controller. > Memory Controller 1〇 can also check fast according to a fixed period

Whether the memory simulator 12 has the need to transmit flash memory access. When the memory controller 10 detects that the memory emulator 12 has sent a flash memory access, the suffix control II 1 mussel 4 performs the flash memory on the real side towel, (4) Memory access requirements can be sent by the main and through the flashcard New Zealand 1112G. And remember j control ^ U) for the flash memory 5. The result of the access performed, the cool value transmission path switcher 110 and the flash memory emulator 120 can be hi-ended. That is to say, in the present embodiment, the host terminal 30 can access the flash memory 50. The 3G can also be obtained by the flash memory simulator 12 (3), and the domain end 30 can be used as the backup status data to the memory controller 10 to control the descent 10 According to FIG. 2, FIG. 2 is a schematic diagram of a transmission path including a path __= according to an embodiment of the present invention. The transmission path is 〇 〇 SW SW 丨 丨 丨 丨. 111 is controlled by switches SWi and 冓. Among them, switches SW1 and SW2 are controlled by the debug start 201227745 " __________doc / ι U tiger DEBEN ' and the switches SW1 and SW2 are turned on or off = body transfer path switch 110 will The control command CTRS of the received η 二 2 / 恣 10 is simultaneously transmitted through the endpoint A1 by 5 〇. The transfer to the flash memory simulator 12G money flash memory 妒 50 value two 'by the flash memory simulator 12G And the flash memory actually responds to the data switcher U〇 data (simulation response data and sw2<l track will switch the mode according to the path, group 111 towel switch _ response data ^ or break ^ state ^ send analog response Data and actual. 10. The body control of the present invention is used to interpret the memory response data to control the command and to generate the analog transmission path and the function of the control and the error according to the control command. In addition, the present invention further utilizes the path. ^ Borrowing ϊΐ 选 ( 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动Normal action = this = fast response, memory and memory controller, you can ship - to 'on the help of high-cost electronic devices, to achieve the fault detection and monitoring functions of flash memory. However, if (4) read the touch exposure as above, Cai Lin used to limit the technical collar y has the knowledge of the pass, in the absence of the protection of the invention, although it can make some changes and retouching, so this... The patent application model defined in the attached file shall prevail. [Simplified illustration] 201227745

36327 twf.doc/I FIG. 1 is a schematic diagram of a development system 100 of a flash memory module according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an embodiment of a transmission path switcher 110 according to an embodiment of the present invention. [Main component symbol description] 100: Development system Φ 110: Transmission path switcher 120: Flash memory emulator 10: Memory controller 30: Host terminal 50: Flash memory 111: Path switching module CTRLS ·· Control command DEBEN: Debug start signal SW1, SW2: Switch • Al, A2: End point 11

Claims (1)

201227745, Λ ^TVAtOOC/I VII. Patent application scope: 1. A flash memory development system, including: a transmission path switcher, connected in series on a 4th transmission road surface, receiving 1 micro-motion signal = - flash memory display, transfer the pass === from the memory controller 22 response, 'The flash memory simulator passes the second mode = send the analog response data to the memory controller Transmission path transmission; 2. If the transmission path switcher transmits the control command transmitted by the body controller to the flash ===remember the flash memory, and And transmitting, according to the debug startup signal, a second poor packet transmission path of an actual response data generated by the flash memory to the memory controller. —— 辂 辂 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请To the host end 1 to transmit the flash memory as described in claim 3, the controller is directed to "memory crying u and the signal 12 201227745 36327twf.doc / l transmission path according to a non-flash The memory control command is configured to transmit at least one data signal to the memory controller. 6. The flash memory development system of claim 3, wherein the host side further sets a debug test mode, and The flash memory simulator generates an error test data according to the status information and the debug test mode as a response and transmits to the controller. 7. (4) The memory development system described in item 3 of the claimant village, wherein the 7 memory control n checks whether the flash memory simulation is transmitted according to the -gj periodic period—(4) memory access requirements, The memory controller accesses the flash memory according to the flash memory access. The cake L is in the flash memory development system as described in item 7 of the second benefit range. The memory access requirement is sent by the host to the flash 9. As described in the third item of the application, The host side is further configured to store the status data in a backup state, and the flash memory development system described in item 9 of the second benefit range; Control is used as the basis for the response of the working state of the memory controller. 13