201217982 六、發明說明： 【發明所屬之技術領域】 本發明係有關於積體電路，特別是有關於可控制複數 從屬元件之積體電路。 【先前技術】 内部積體電路（Inter Integrated Circuit，I2C )匯流排 是飛利浦（PHILIPS)公司所開發的串列式傳輸匯流排標 準，用來作為積體電路之間的一種溝通協定，例如微控制 器及其週邊元件。一般而言，位於内部積體電路匯流排上 的主控（Master)元件會先發出接收端專屬的從屬元件位 址，用以表示主控元件欲與哪一個從屬（Slave)元件進行 溝通。接著，主控元件才會送出資料，此時只有該從屬元 件會接收資料。因此’主控元件可對每個從屬元件進行查 詢及控制。然而’當從屬元件的數量增加時，主控元件需 要使用更多的時間來對每一從屬元件進行控制。 【發明内容】 本發明提供一種積體電路，用以控制複數從屬元件， 其中每一上述從屬元件具有一時脈輸入接腳、一資料輸入 接腳以及一位址選擇接腳。上述積體電路包括：一處理單 元，用以提供欲傳送至上述複數從屬元件之至少一者的一 責訊，以及，一控制器，耦接於上述處理單元，用以根據 内部積體電路（Inter Integmed Ckeuit，I2C ) Ε流排協定 而&(、上述> Λ至母上述從屬元件的上述時脈輸入接腳 及上述貝料輸人接腳，並根據上述資訊提供_選擇信號至 VIT10-0008IOO-TW/0608-A42404twf 4 201217982 述複數從屬元件之至少該者的上述位址選擇接腳。 再者’本發明提供—種控制方法 ’適用於用以控制複 數從屬元件之-積體電路，其中每一上述從屬元件具有一 時脈輸入接腳、—資料輪入接腳以及一位址選擇接腳。上 述控制方法包括.接收欲傳送至上述複數從屬元件之一或 多者的^資訊；根據内部積體電路（I2C)匯流排協定’提 供上述資訊至每-上述從屬元件的上述時脈輸入接腳及上 述資料輸入接腳；以及，根據上述資訊，提供一選擇信號 β至^件以相上雜轉擇接腳。 【貫施方式】 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉出較佳實施例，並配合所附圖式，作詳 細說明如下： 實施例： 第1圖係顯示使用積體電路100來提供不同聲道的應 用示意圖。在第1圖中，積體電路10〇可作為主控（Master) • 元件來控制四個立體聲數位對類比轉換器（Digital to Analog Converter ’ DAC) 110A-110D，即數位對類比轉換 器110A-110D為從屬（slave)元件，以便提供7.1聲道的 效果。例如，數位對類比轉換器110A-110D可分別提供前 置聲道、環繞聲道、中央/低頻特效聲道以及側環繞聲道等 不同聲道。在第1圖中，積體電路100可透過内部積體電 路（I2C)匯流排協定與週邊從屬元件進行溝通。舉例來說， 對積體電路1〇〇而言，每一數位對類比轉換器110A-110D 具有各自的從屬元件位址。因此，透過串列時脈線（Serial VIT10-0008I00-TW/0608-A42404twf 5 201217982201217982 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to an integrated circuit, and more particularly to an integrated circuit that can control a plurality of slave elements. [Prior Art] The Inter Integrated Circuit (I2C) bus is a tandem transmission bus standard developed by Philips (PHILIPS), which is used as a communication protocol between integrated circuits, such as micro-control. And its surrounding components. In general, the master component located on the internal integrated circuit bus will first issue the slave-specific slave address to indicate which slave component the master component wants to communicate with. Then, the master component will send the data, and only the slave component will receive the data. Therefore, the master component can query and control each slave component. However, when the number of slave components increases, the master component needs to use more time to control each slave component. SUMMARY OF THE INVENTION The present invention provides an integrated circuit for controlling a plurality of slave components, wherein each of the slave components has a clock input pin, a data input pin, and an address selection pin. The integrated circuit includes: a processing unit for providing a charge to be transmitted to at least one of the plurality of slave components, and a controller coupled to the processing unit for the internal integrated circuit ( Inter Integmed Ckeuit, I2C) bus bar protocol & (, above > to the above-mentioned clock input pin of the above-mentioned slave component and the above-mentioned shell input pin, and provide _ selection signal to VIT10 according to the above information -0008IOO-TW/0608-A42404twf 4 201217982 The at least one of the above-mentioned address selection pins of the plurality of dependent elements. Further, the "control method provided by the present invention" is applied to an integrated circuit for controlling a plurality of dependent elements. Each of the slave elements has a clock input pin, a data wheel input pin, and an address selection pin. The control method includes: receiving information to be transmitted to one or more of the plurality of slave elements; Providing the above information to each of the clock input pins of each of the above-mentioned slave components and the above data input pins according to an internal integrated circuit (I2C) bus bar protocol; and, according to In the above information, a selection signal β to ^ is provided to be used as a phase-shifting pin. [Comprehensive mode] The above and other objects, features, and advantages of the present invention are more apparent and easy to understand. The preferred embodiment, in conjunction with the drawings, is described in detail as follows: Embodiment: Fig. 1 is a schematic diagram showing the application of using the integrated circuit 100 to provide different channels. In Fig. 1, the integrated circuit 10 can be used. As a Master • Component to control four stereo to analog converters (DACs) 110A-110D, ie digital to analog converters 110A-110D are slave components to provide 7.1 sound For example, the digital-to-analog converters 110A-110D can provide different channels such as front channel, surround channel, center/low frequency effect channel, and side surround channel. In Fig. 1, the integrated body The circuit 100 can communicate with peripheral slave components via an internal integrated circuit (I2C) bus protocol. For example, for the integrated circuit 1〇〇, each digit has its own slave to the analog converters 110A-110D. Address. Thus, when the serial transmission clock line (Serial VIT10-0008I00-TW / 0608-A42404twf 5 201217982
Clock Line ’ SCL )信號以及串列資料位址（serial Data Address，SDA)信號，積體電路loo可傳送對應於欲控制 之數位對類比轉換器的從屬元件位址，以便選址至該數位 對類比轉換器，進而對該數位對類比轉換器進行控制。假 設數位對類比轉換器110A-110D為相同型號的積體電路 時’積體電路100仍無法同時控制數位對類比轉換器 110A-110D。例如，積體電路10〇無法同時致能全部的數 位對類比轉換器110A-110D。換句話說，雖然積體電路ι〇〇 可使用相同的控制指令來致能數位對類比轉換器 110A-110D，然而由於數位對類比轉換器u〇A_11〇D分別 具有不同的從屬元件位址，因此積體電路1〇〇仍需依序透 過不同的從屬元件位址來傳送相同的致能指令至數位對類 比轉換器110A-110D，以便分別對數位對類比轉換器 110A-110D進行控制。 第2圖係顯不使用另一積體電路2〇〇來提供不同聲道 的應用示意圖。在第2圖中，數位對類比轉換器21〇a_21〇d 為特定兀件，其可具有不同的從屬元件位址並可透過元件 位址選擇接腳SADDR來進行設定。舉例來說，假如數位 對類比轉換器的元件位址選擇接腳Saddr被奴為邏輯 位準0時’則可⑨定該數位對類比轉換器的從屬元件位址 為ADDG。反之’假如數位對類比轉換器的元件位址選擇 接腳SADDR被設定為邏輯位準“i”時，則可設定該數位對 類比轉換器的從屬it件位址為ADm。如第2圖所顯示， 積體電路200包括處理單元22〇、解瑪器23〇以及兩内部 積體電路介面單元240與250。内部積體電路介面單元24〇 VIT10-00〇8!00-TW/0608-A42404twf . 201217982 會提供串職料信號SDAG以及串_脈信號scl〇 位對類比轉換器21GA與2的資料輸人接聊s麵 時脈輸入接腳SCLK，而内部積體電路介面單元25〇合 供串列資料信號圖以及串列時脈信號scu至數二 類比轉換器21GC與21QD的資料輸人接腳s_以及時脈 輸入接腳SCLK。此外’由於數位對類比轉換器2i〇a鱼 2K)C的元件位址選擇接腳SADDR被設定為邏輯位準， 且數位對類比轉換器2_肖2㈣的元件位址選擇接腳 SADDR被設定為邏輯位準“丨，，，所以數位對類比轉換器 210Α與21〇(:的從屬元件位址為Α_，而數位對類比轉 換器210Β與210D的從屬元件位址為ADD1。因此，在積 體電路2GG中，透過解碼器23〇、内部積體電路介面單元 240與内部積體電路介面單元25〇，處理單元22〇可同時對 ，位對類比轉換器21〇AA210C兩者或是數位對類比轉換 器210B與210D兩者進行控制。此外，處理單元22〇亦可 分別對每一數位對類比轉換器210A-210D進行控制。值得 注意的是，在第2圖中，積體電路200仍然無法同時對全 部的數位對類比轉換器210A-210D進行控制。 第3圖係顯示根據本發明一實施例所述之積體電路 300的應用示意圖，其可藉由控制複數個從屬元件來提供 不同聲道。如先前所描述，積體電路3〇〇可作為主控元件 來控制四個立體聲數位對類比轉換器31〇a_31〇d，以分別 提供前置聲道、環繞聲道、中央/低頻特效聲道以及侧環繞 聲道等不同聲道來達到7_1聲道的效果。在第3圖中，積 體電路300包括處理單元32〇以及控制器360，其中控制 VIT10-0008I00-TW/0608-A42404twf η 201217982 器360包括解碼器330、介面單元340以及選擇單元350。 介面單元340可透過接腳ΡίΝ1提供串列資料信號SDA至 每一數位對類比轉換器310A_31〇D的資料輸入接腳 SDIN ’並可透過接腳j>IN2提供串列時脈信號SCL至每一 數位對類比轉換器310A-310D的資料輸入接腳SClk。此 外’選擇單元可透過接腳PIN3—〇、piN3—〗、pIN3—2與 PIN3—3分別提供選擇信號SEL〇、SEL1、SEL2與SEL3至 數位對類比轉換器3l〇A、310B、31〇c與31〇D的元件位址 選擇接腳SADDR。 在第3圖中，處理單元320會提供欲傳送至數位對類 比轉換器310A-310D之至少一者的資訊INF〇至解碼器 330。接著，解碼器33〇會對來自處理單元32〇的資訊ΐΝρ〇 ，行，碼，以得到資訊INF0的識別碼仍，其中識別碼m 指示資訊INFO欲被傳送至數位對類比轉換器31〇a_3i〇d 的何者。接著，介面單元34〇透過解碼器33〇接收到資訊 INFO,並根據内部積體電路匯流排協定來產生對應於資訊 INFO的串列資料信號SDA及串列時脈信號SCL。接著°， 介面單元340會經由接腳PIN1與接腳piN2分別提供串列 資料信號SDA及串列時脈信號SCL至數位對類比轉換器 310A-31GD。同時地，選擇單元35Q會根據所接收的識別 碼ID來提供適當的選擇信號至數位對類比轉換器 310A-310D。舉例來說’當識別碼山指示資訊inf〇係欲 被傳送至數位對類比轉換器310A時，則選擇單元35〇會 提供具有第-邏輯位準的選擇信號SEU)至數位對類比^ 換器310A，並提供具有第二邏輯位準的選擇信號seu、 VIT10-0008I00-TW/0608-A42404twf 〇 201217982 SEL2與SEL3至數位對類比轉換器31〇B_3l〇D，以便通知 數位對類比轉換器310A來接收串列時脈信號SCL以及串 列 > 料彳§號SDA。值得庄意的是，選擇信號的 邏輯位準可根據數位對類比轉換器31〇A_3l〇D的規格而決 疋。舉另一例子來說，當識別碼ID指示資訊INF〇係欲被 傳送至數位對類比轉換器310A以及310B時，則選擇單元 350會提供具有第一邏輯位準的選擇信號8£1^〇以及選擇信 號SEL1至數位對類比轉換器310A以及310B，並提供具 # 有第二邏輯位準的選擇彳§號SEL2與SEL3至數位對類比轉 換器310C-310D，以便通知數位對類比轉換器3i〇a以及 310B來接收串列時脈信號SCL以及串列資料信號SDA。 在一實施例中，第一邏輯位準的選擇信號與第二邏輯位準 的選擇信號可為邏輯互補信號。 此外，對積體電路300而言，數位對類比轉換器 310A-310D具有相同的從屬元件位址。因此，根據本發明 之實施例，積體電路300可同時對數位對類比轉換器 • 310A-310D進行控制。例如，當積體電路3〇〇欲同時對數 位對類比轉換器310A-310D進行控制時，處理單元32〇會 提供欲同時傳送至數位對類比轉換器31〇A_31〇d的資訊 INFO至解碼器330。接著，解碼器330會對來自處理單元 320的資訊INFO進行解碼，並得到資訊INFO的識別石馬 ID ’其中識別碼ID會指示資訊INFO欲被傳送至全部的數 位對類比轉換器310A-310D。接著，介面單元340會根據 内部積體電路匯流排協定來產生對應於資訊INF〇的串列 資料信號SDA及串列時脈信號SCL並傳送至數位對類比 VIT1 〇-〇〇08IO〇-TW/〇608-A424Q4twf 9 201217982 轉換器310A-310D。同時地，選擇單元35〇會分別提供具 有第一邏輯位準的選擇信號SEL〇、SEL1、SEL2與SEL3 至數位對類比轉換器310A-310D，以便通知全部的數位對 類比轉換器310A-310D來接收串列時脈信號scl以及串列 資料信號SDA，並執行後續程序。在一實施例中，上述資 訊INFO係以一對照表（lookup table)的形式存放在一暫 存器中’以供解碼器使用。在一實施例中，上述複數數位 對類比轉換器310A-310D具有相同的從屬元件位址時，則 上述串列資料信號包含上述數位對類比轉換器31 〇a_3 10D 的位址。 再者’積體電路300亦可透過控制器360提供符合串 列週邊介面（Serial Peripheral Interface，SPI)匯流排協定 的信號至週邊的從屬元件。舉例來說，當積體電路3〇〇與 從屬元件以串列週邊介面匯流排協定進行溝通時，介面單 元340會透過解碼器330接收到來自處理單元320的資訊 INFO ’並根據串列週邊介面匯流排協定來產生對應於資訊 INFO的串列資料信號SDA及串列時脈信號SCL。同時地， 選擇單元350會根據所接收的識別碼ID來提供適當的選擇 信號至數位對類比轉換器310A-310D，其中選擇信號 SEL0-SEL3可視為數位對類比轉換器310A-310D的晶片選 擇（Chip Select，CS)信號。因此，若數位對類比轉換器 310A-310D同時支援串列週邊介面（serial peripheral interface，SPI)匯流排協定時，則積體電路300可根據數 位對類比轉換器310A-310D所選定之匯流排協定對數位對 類比轉換器310A-310D進行控制，而無須進一步變動印刷 VITl 0-0008!00-TW/0608-A42404twf 10 201217982 電路板上的相關設計與應用。 第4圖係顯示根據本發明_實施例所述之適用於一積 路，控制方法’其中積體電路可控制複數個從屬元 、且母從屬元件具有一時脈輸入接腳、一資料輸入接 :以位址轉細。首先，接收欲傳送至複數從屬元 或夕者的—資訊（步驟S4〇2)。接著，根據内部積 ^匯流排協定’分別提供對應於上述資訊的串列時脈 串列資料信號至每—從屬以的串列時脈輸入接 腳及串列資料輸人接腳（步驟S404)。接著，對欲傳送之Clock Line ' SCL ) signal and serial data address (SDA) signal, the integrated circuit loo can transmit the slave component address corresponding to the digital-to-analog converter to be controlled, so as to be addressed to the digit pair An analog converter, which in turn controls the analog to analog converter. Assuming that the digital-to-analog converters 110A-110D are the same type of integrated circuits, the integrated circuit 100 cannot simultaneously control the digital-to-analog converters 110A-110D. For example, the integrated circuit 10A cannot simultaneously enable all of the digital pair analog converters 110A-110D. In other words, although the integrated circuit ι〇〇 can use the same control instructions to enable the digital-to-analog converters 110A-110D, since the digital-to-analog converters u〇A_11〇D have different slave component addresses, Therefore, the integrated circuit 1〇〇 still needs to transmit the same enable command to the digital-to-analog converters 110A-110D through different slave component addresses in order to control the digital-to-analog converters 110A-110D, respectively. Figure 2 shows an application diagram that does not use another integrated circuit 2〇〇 to provide different channels. In Fig. 2, the digital-to-analog converter 21〇a_21〇d is a specific component which can have different slave component addresses and can be set by the component address selection pin SADDR. For example, if the digital address selection pin Saddr of the analog converter is slaved to logic level 0, then the number of the slave to the analog converter's slave component is set to ADDG. On the other hand, if the digit address selection pin SADDR of the analog converter is set to the logic level "i", the slave address of the analog converter can be set to ADm. As shown in Fig. 2, the integrated circuit 200 includes a processing unit 22, a masher 23A, and two internal integrated circuit interface units 240 and 250. Internal integrated circuit interface unit 24〇VIT10-00〇8!00-TW/0608-A42404twf . 201217982 will provide serial feed signal SDAG and serial_pulse signal scl clamp to analog converter 21GA and 2 data input The internal integrated circuit interface unit 25 is coupled with the serial data signal map and the serial clock signal scu to the second analog converter 21GC and 21QD data input pin s_ And the clock input pin SCLK. In addition, the component address selection pin SADDR of the 'bit pair analog converter 2i〇a fish 2K' is set to a logic level, and the component address selection pin SADDR of the analog to analog converter 2_Shaw 2 (4) is set. The logic level is "丨,,, so the digital pair analog converters 210Α and 21〇 (: the slave component address is Α_, and the digit pair analog converters 210Β and 210D slave component addresses are ADD1. Therefore, in the product In the body circuit 2GG, through the decoder 23, the internal integrated circuit interface unit 240 and the internal integrated circuit interface unit 25, the processing unit 22 can simultaneously, the bit-to-pair converter 21A AA210C or a digital pair The analog converters 210B and 210D are controlled. In addition, the processing unit 22 can also control each of the digital-to-analog converters 210A-210D. It is noted that in the second figure, the integrated circuit 200 is still It is not possible to control all of the digital-to-analog converters 210A-210D at the same time. Fig. 3 is a schematic diagram showing the application of the integrated circuit 300 according to an embodiment of the present invention, which can be provided by controlling a plurality of slave elements. Different channels. As previously described, the integrated circuit 3 can be used as a master to control four stereo digit-to-analog converters 31〇a_31〇d to provide front channel, surround channel, center/ Different channels such as low frequency effect channel and side surround channel achieve the effect of 7_1 channel. In Fig. 3, integrated circuit 300 includes processing unit 32A and controller 360, wherein VIT10-0008I00-TW/0608 is controlled. -A42404twf η 201217982 The device 360 includes a decoder 330, an interface unit 340, and a selection unit 350. The interface unit 340 can provide the serial data signal SDA to the data input pin SDIN of each digit pair analog converter 310A_31〇D through the pin ΡίΝ1. 'The serial clock signal SCL can be provided through the pin j>IN2 to the data input pin SClk of each digit pair analog converter 310A-310D. In addition, the 'selection unit can be through pin PIN3-〇, piN3-〗, pIN3-2 and PIN3-3 provide selection signal SEL〇, SEL1, SEL2, and SEL3 to the digital address selection pins SADDR of the analog-to-digital converters 31a, 310B, 31〇c, and 31〇D, respectively. In the figure, the processing order 320 will provide information INF〇 to the decoder 330 to be transmitted to at least one of the digital pair analog converters 310A-310D. Next, the decoder 33 will ΐΝρ〇, line, code the information from the processing unit 32〇 to The identification code of the information INF0 is still obtained, wherein the identification code m indicates which of the digital pair analog converters 31A_3i 〇d is to be transmitted to the digital information INFO. Next, the interface unit 34 receives the information INFO through the decoder 33, and generates the serial data signal SDA and the serial clock signal SCL corresponding to the information INFO according to the internal integrated circuit bus protocol. Next, the interface unit 340 provides the serial data signal SDA and the serial clock signal SCL to the digital pair analog converters 310A-31GD via the pin PIN1 and the pin piN2, respectively. Simultaneously, selection unit 35Q provides an appropriate selection signal to digital pair analog converters 310A-310D based on the received identification code ID. For example, when the identification code indication information inf is to be transmitted to the digital pair analog converter 310A, the selection unit 35 提供 provides a selection signal SEU with a first logic level to a digital pair analog converter. 310A, and provides a selection signal seu, VIT10-0008I00-TW/0608-A42404twf 〇201217982 SEL2 and SEL3 to digital pair analog converter 31〇B_3l〇D with a second logic level to notify the digital pair analog converter 310A Receiving the serial clock signal SCL and the serial number > § § SDA. It is worth noting that the logic level of the selection signal can be determined by the specification of the analog converter 31〇A_3l〇D. As another example, when the identification code ID indication information INF is to be transmitted to the digital pair analog converters 310A and 310B, the selection unit 350 provides a selection signal having the first logic level. And selecting the signal SEL1 to the digital pair analog converters 310A and 310B, and providing the selection 彳§ SEL2 and SEL3 to the digital-to-digital converter 310C-310D having the second logic level to notify the digital-to-analog converter 3i 〇a and 310B receive the serial clock signal SCL and the serial data signal SDA. In an embodiment, the selection signal of the first logic level and the selection signal of the second logic level may be logical complementary signals. Moreover, for integrated circuit 300, digital to analog converters 310A-310D have the same slave component address. Thus, in accordance with an embodiment of the present invention, integrated circuit 300 can simultaneously control digital to analog converters 310A-310D. For example, when the integrated circuit 3 wants to simultaneously control the digital-to-analog converters 310A-310D, the processing unit 32 提供 provides information INFO to the decoder that is simultaneously transmitted to the digital-to-analog converter 31〇A_31〇d. 330. Next, the decoder 330 decodes the information INFO from the processing unit 320 and obtains the identification of the information INFO. The identification code ID indicates that the information INFO is to be transmitted to all of the digital pair analog converters 310A-310D. Next, the interface unit 340 generates the serial data signal SDA and the serial clock signal SCL corresponding to the information INF〇 according to the internal integrated circuit bus arrangement and transmits the digital data to the analog VIT1 〇-〇〇08IO〇-TW/ 〇608-A424Q4twf 9 201217982 Converter 310A-310D. Simultaneously, the selection unit 35 提供 provides selection signals SEL 〇, SEL1, SEL2 and SEL3 to digital pair analog converters 310A-310D having a first logic level, respectively, in order to notify all digits to the analog converters 310A-310D. The serial clock signal scl and the serial data signal SDA are received, and a subsequent procedure is executed. In one embodiment, the aforementioned information INFO is stored in a register in the form of a lookup table for use by the decoder. In one embodiment, when the complex digits have the same slave component address for the analog converters 310A-310D, then the serial data signal includes the address of the digit-to-analog converter 31 〇a_3 10D. Furthermore, the integrated circuit 300 can also provide a signal conforming to the Serial Peripheral Interface (SPI) busbar protocol to the peripheral slave components via the controller 360. For example, when the integrated circuit 3 〇〇 communicates with the slave component in the serial peripheral interface bus protocol, the interface unit 340 receives the information INFO ' from the processing unit 320 through the decoder 330 and according to the serial peripheral interface. The bus bar protocol generates a serial data signal SDA and a serial clock signal SCL corresponding to the information INFO. Simultaneously, selection unit 350 provides an appropriate selection signal to digital pair analog converters 310A-310D based on the received identification code ID, wherein selection signals SEL0-SEL3 can be considered as wafer selection for digital to analog converters 310A-310D ( Chip Select, CS) signal. Therefore, if the digital pair analog converters 310A-310D simultaneously support a serial peripheral interface (SPI) bus protocol, the integrated circuit 300 can select the bus protocol according to the digital pair analog converters 310A-310D. The digital-to-digital converters 310A-310D are controlled without further variation in the design and application of the printed VIT1 0-0008!00-TW/0608-A42404twf 10 201217982 circuit board. Figure 4 is a diagram showing a method for controlling a method according to the present invention, wherein the integrated circuit can control a plurality of slave elements, and the master slave component has a clock input pin and a data input: Turn the address to fine. First, the information to be transmitted to the plural slave or the evening is received (step S4〇2). Then, according to the internal product bus arrangement agreement, respectively, the serial clock serial data signal corresponding to the above information is provided to each of the dependent serial clock input pins and the serial data input pins (step S404). . Then, for the transmission
Λ進仃解碼’並得到一識別碼，其中識別碼係對應 讀從屬元件之該者（即識別碼指示上述資訊欲被傳送 :稷數從屬元件的何者）（步驟S406)。接著，根據上述 °另1碼、’提供適#的選擇錢至複數從屬元件之該者，以 便通知複數彳％件之該者來接收串列時脈信號以及串列 資料信號，並進行後續操作（步驟s彻）。值得注意的是， 對積體電路而言’每-從屬元件具有相同的從屬元件位址。 •在一實施例中，若積體電路與週邊從屬元件為單向傳 輸’或是從屬元件在接收到來自積體電路的訊息之後，不 需進步傳送回應信號（Acknowledge，ACK )或是不回應 #5虎（Negative-Acknowledge ’ NAK)給積體電路，則根據 本發明實施例所述之積體電路可更快速地對從屬元件進行 控制。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發日狀精神和範_，當可作些許之更動與潤飾， VIT10-0008I00-TW/0608-A42404twf 201217982 因此本發明之保護範圍當視後附之申請專利範圍所界定者 為準。 【圖式簡單說明】 第1圖係顯示使用積體電路來提供不同聲道的應用示 意圖； 第2圖係顯示使用另一積體電路來提供不同聲道的應 用示意圖； 第3圖係顯示根據本發明一實施例所述之積體電路的 應用示意圖，其可藉由控制複數個從屬元件來提供不同聲 道；以及 第4圖係顯示根據本發明一實施例所述之適用於一積 體電路的控制方法。 【主要元件符號說明】 100、200、300〜積體電路； 110A-110D、210A-210D、310A-310D〜數位對類比轉 換器； 220、320〜處理單元； 230、330〜解碼器； 240、250〜内部積體電路介面單元； 340〜介面單元； 350〜選擇單元； 360〜控制器； ID〜識別碼； VIT10-0008I00-TW/0608-A42404twf 12 201217982 INFO〜資訊； 2、PIN3 PIN卜 PIN2、PIN3_0、PIN3_1、PIN3_ 腳； 以及 SCL、SCLO、SCL1〜串歹<J時脈信號； SDA、SDAO、SDA1〜串列資料信號； SEL0-SEL3〜選擇信號。 VIT10-0008!00-TW/0608-A42404twf 13The decoding is performed and an identification code is obtained, wherein the identification code corresponds to the one of the read slave elements (i.e., the identification code indicates that the information is to be transmitted: which of the number of dependent elements) (step S406). Then, according to the above-mentioned other code, 'providing the appropriate money' to the one of the plurality of dependent elements, to notify the person of the plurality of pieces to receive the serial clock signal and the serial data signal, and perform subsequent operations. (Step s thoroughly). It is worth noting that the 'per-slave element' has the same slave element address for the integrated circuit. • In an embodiment, if the integrated circuit and the peripheral slave component are unidirectional transmissions' or the slave component receives the message from the integrated circuit, there is no need to improve the transmission response signal (Acknowledge, ACK) or not respond. The #5虎(Negative-Acknowledge 'NAK) is an integrated circuit, and the integrated circuit according to the embodiment of the present invention can control the slave components more quickly. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit of the present invention. , VIT10-0008I00-TW/0608-A42404twf 201217982 Therefore, the scope of protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram showing an application using an integrated circuit to provide different channels; Fig. 2 is a schematic diagram showing an application using another integrated circuit to provide different channels; A schematic diagram of an application of an integrated circuit according to an embodiment of the present invention, which can provide different channels by controlling a plurality of slave components; and FIG. 4 shows an application for an integrated body according to an embodiment of the invention. The control method of the circuit. [Major component symbol description] 100, 200, 300 ~ integrated circuit; 110A-110D, 210A-210D, 310A-310D ~ digital to analog converter; 220, 320 ~ processing unit; 230, 330 ~ decoder; 250~Internal Integrated Circuit Interface Unit; 340~Interface Unit; 350~Select Unit; 360~Controller; ID~ID; VIT10-0008I00-TW/0608-A42404twf 12 201217982 INFO~Information; 2, PIN3 PIN Bu PIN2 , PIN3_0, PIN3_1, PIN3_ pin; and SCL, SCLO, SCL1 ~ string 歹 < J clock signal; SDA, SDAO, SDA1 ~ serial data signal; SEL0-SEL3 ~ selection signal. VIT10-0008!00-TW/0608-A42404twf 13