201209430 六、發明說明： 【發明所屬之技術領域】 本發明係關於積體電路測試之技術領域，尤指一種 混合模式積體電路的測試系統及方法。 曰 【先前技術】 隨著積體電路製程的進步，積體電路在應用設計上 愈來愈複雜，因此積體電路測試成為積體電路製造流程 中重要的-環。積體電路測試主要係以自動測試裝置 (AUt〇matic Testing Equipemem，ate)，利用；則試程式模 擬積體電料種可能之使用環境及方法，例如在高溫、 低/皿、電壓不穩及電壓偏高或偏低等惡劣彰竟與一般正 常使用狀況下，將受測積.體電路置於此模擬環境中，測 試其工作狀態是否在規格範圍内，以麵積體電路之品 質。 積體電路測試一般可分成兩個階段，其中在切割、 封裝前的測試為積體電路晶圓測試（Wafer 丁⑶），其目的 在針對W作電性功能上❹m，使1(：在進人封裝前能 先行過濾出電性功能不良的晶片，以降低積體電路成品 的不良率’減少製造成本的耗費。而封裝成形後的測試 為積體電路成品測試（FinaI Test)，》目的在確認積體電 路成。口的功能、速度 '容忍度、電力消耗、熱力發散等 屬性是否正常，以確保積體電路出貨前的品質。 201209430 現今的積體電路是一個相當複雜電路設計，包含了 數=及類比等電路。圖混合模式積體電路no的 不思圖’如圖1所不’其包含—類比至數位轉換器120、 -相位鎖相迴路13〇、及_内部電路14()。類比至數位轉 換器12〇將一外部輸入訊號轉換成數位資料 ADO[n-l:〇]，以輸出至該内部電路14〇。一般的類比至數 位轉換器120通常會以相位鎖相迴路13〇所產生的^、“。 # 訊號做為取樣頻率。而cik一adc訊號是由相位鎖相迴路13〇 將crystal訊號的輸入頻率合成所產生。 圖2係習知使用一自動測試裝置（ATE)l50對一混合 杈式積體電路1 10進行測試的示意圖。其係由該自動測試 裝置150產生cryStai訊號及輸入訊號，其中，該自動測試 裝置150依據内部的測試資料以產生該輸入訊號。該自動 測试裝置1 50接收混合模式積體電路丨1〇輸出的數位資料 AD〇[n_i :0]，並與測試資料比較，以判斷類比至數位轉 φ 換器120的功能是否正常。於圖2的測試方法中，由於受 限忒自動測試裝置15〇的性能，因此量測類比至數位轉換 器120時’必須將crystai訊號略過相位鎖相迴路丨3〇，直接 輸出至該類比至數位轉換器12〇，才能利用該自動測試裝 置150送出的固定程序進行測試’因此無法量測相位鎖相 迴路130的抖動（j i 11 eΓ)對類比至數位轉換器12〇造成的 影響，同時’相位鎖相迴路丨30需另外再進行測量，因此， 無法對混合模式積體電路11〇進行整體性能量測。習知自 動測試裝置無法偵測訊號的過渡（transit丨οη)，因此時.習知 201209430 自動測試裝置無法利用相位鎖相迴路的輸出時序的正緣 或負緣來擷取類比至數位轉換器資料。 圖3係習知使用一邏輯分析儀（L〇gic Analizer， LA)160對一混合模式積體電路11〇進行測試的示意圖。由 於邏輯分析儀（LA) 160較自動測試裝置（ΑΊΈ)貴且功能較 齊全’尤其邏輯分析儀（LA)160能偵測訊號的邊緣觸發 點’因此可用來量測該類比至數位轉換器12〇搭配相位鎖 相迴路130的整體性能。但由於邏輯分析儀（LA)16〇内部 記憶體有限且其記憶體大小不易增加，因此邏輯分析儀 (LA)160不易收集大量的資料來進行分析，同時也會受限 於邏輯分析儀（LA) 160的價格’致使測試成本會增加許 多。因此習知混合模式積體電路的測試系統及方法仍有 予以改進之必要。 【發明内容】 本發明之主要目的係在提供一種混合模式積體電路 (mixed-mode 1C)的測試系統及方法，俾能在低成本的自 動測試裝置下進行混合模式積體電路的性能量測，並藉 由簡易的邏輯設計便能量測類比電路的整體性能並俄測 相位鎖相迴路的穩定度。 依據本發明之一特色，本發明提出一種混合模式積 體電路（mixed-mode 1C)的測試系統，包括一混合模式積 體電路及一自動測試裝置。該混合模式積體電路包含一 類比至數位轉換器、一相位鎖相迴路、一時序接腳、及 一先進先出緩衝器。該類比至數位轉換器接收一測試訊 201209430 ° 。’將D亥測试況號轉換成一數位輸入資料。該相位鎖 相、路接收—第—外部時序訊號，以產生-輸人時序訊 =^ f盼序接腳接收一第二外部時序訊號。該先進先出 ^…連接至該類比至數位轉換器、該相位鎖相迴路及 二夺序接腳，依據該輸入時序訊號，以將該數位輸入資 T寫入°亥先進先出緩衝器中，並依據該第二外部時序訊 、X肩出该先進先出緩衝器的資料。該自動測試裝置 a該混合模式積體電路，以產生該測試訊號、該第 -；^卜A夺序°孔號、及該第二外部時序訊號，並依據該第 ρ時序訊號，以拾鎖該先進先出緩衝器的資料。 依據本發明之又—特色，本發明提出―種混合模式 _電路（mixed_mode π)的測試方法，其係在一自動測 、裝置中測s式一混合模式積體電路該混合模式積體電 路包含-類比至數位轉換器、—相位鎖相迴路、一時序 :腳及先進先出緩衝器，該方法包含下列步驟： 。:自動測试裝置產生—測試訊號、一第一外部時序訊 :、及二第二外部時序訊號，其中該測試訊號係依據一 立彳忒貝料產生，（B)該相位鎖相迴路接收該第一外 Z序㈣’以產生—輸人時序訊號；（C)該類比至數 入^器接㈣測試㈣及該輸人時序減，依據該輸 ,序汛唬以將該測試訊號轉換成一數位輸入資料；（D j進先出緩衝器依據該輸人時序訊號，以將該數位輸 、料寫人j先進先出緩衝器中，並依據該第二外部時 A唬’以項出該先進先出緩衝器的資料；（Ε)該自動 201209430201209430 VI. Description of the Invention: [Technical Field] The present invention relates to the technical field of integrated circuit testing, and more particularly to a test system and method for a hybrid mode integrated circuit.曰 [Prior Art] With the advancement of the integrated circuit process, the integrated circuit is becoming more and more complicated in application design, so the integrated circuit test becomes an important loop in the integrated circuit manufacturing process. The integrated circuit test is mainly used by the automatic test equipment (AUt〇matic Testing Equipemem, ate); the test program simulates the possible use environment and method of the integrated electric material, such as high temperature, low/dish, voltage instability and If the voltage is too high or too low, and the normal use conditions, the measured product body circuit is placed in this simulation environment to test whether its working state is within the specification range, and the quality of the area body circuit. Integral circuit testing can generally be divided into two stages, in which the test before cutting and packaging is integrated circuit wafer testing (Wafer Ding (3)), the purpose of which is to make electrical functions for W, so that 1 (: in progress) Before packaging, people can filter out the defective silicon wafers first, so as to reduce the defect rate of the finished circuit's finished product, and reduce the manufacturing cost. The packaged test is the FinaI Test. Check whether the integrated circuit function, speed 'tolerance, power consumption, thermal divergence and other attributes are normal to ensure the quality of the integrated circuit before shipment. 201209430 Today's integrated circuit is a rather complex circuit design, including Circuits such as number = and analogy. The diagram of the mixed mode integrated circuit no "as shown in Figure 1" includes - analog to digital converter 120, - phase locked loop 13 〇, and _ internal circuit 14 ( The analog to digital converter 12 converts an external input signal into digital data ADO[nl:〇] for output to the internal circuit 14A. A general analog to digital converter 120 will typically The phase-locked loop 13 产生 generates the ^, ". # signal as the sampling frequency. The cik-adc signal is generated by the phase-locked loop 13 〇 the crystal signal input frequency is synthesized. Figure 2 is a conventional use of an automatic A schematic diagram of a test device (ATE) 150 for testing a hybrid 积-type integrated circuit 110. The automatic test device 150 generates a cryStai signal and an input signal, wherein the automatic test device 150 generates the test data according to the internal test data. The automatic test device 150 receives the digital data AD〇[n_i:0] outputted by the mixed mode integrated circuit 丨1〇, and compares it with the test data to determine the function of the analog to digital converter φ120 Whether it is normal. In the test method of Fig. 2, due to the limitation of the performance of the automatic test device 15〇, when measuring analog to the digital converter 120, the crystai signal must be skipped by the phase-locked loop 丨3〇, and the direct output Up to the analog to digital converter 12〇, the test can be performed by the fixed program sent by the automatic test device 150. Therefore, the jitter of the phase locked loop 130 cannot be measured (ji 11 eΓ). The effect of the analog-to-digital converter 12〇, while the 'phase-locked loop 丨30 needs to be measured separately, therefore, the integrated energy measurement cannot be performed on the hybrid mode integrated circuit 11〇. The conventional automatic test device cannot detect The transition of the test signal (transit丨οη), therefore, the conventional 201209430 automatic test device cannot use the positive or negative edge of the output timing of the phase-locked loop to draw the analog-to-digital converter data. Figure 3 is a conventional use. A logic analyzer (L) is used to test a mixed mode integrated circuit 11A. Since the logic analyzer (LA) 160 is more expensive than the automatic test device (ΑΊΈ) and has a more complete function 'in particular, the logic analyzer (LA) 160 can detect the edge trigger point of the signal', so it can be used to measure the analog to digital converter 12 The overall performance of the phase locked loop 130 is matched. However, because the logic analyzer (LA) 16 〇 internal memory is limited and its memory size is not easy to increase, the logic analyzer (LA) 160 is not easy to collect a large amount of data for analysis, and is also limited by the logic analyzer (LA) The price of 160' causes the cost of testing to increase a lot. Therefore, the test system and method of the conventional mixed mode integrated circuit are still necessary for improvement. SUMMARY OF THE INVENTION The main object of the present invention is to provide a mixed mode integrated circuit (mixed-mode 1C) test system and method, which can perform the energy measurement of a mixed mode integrated circuit under a low-cost automatic test device. And with a simple logic design, the energy of the analog circuit is measured and the stability of the phase-locked loop is measured. In accordance with a feature of the present invention, the present invention provides a hybrid mode integrated circuit (mixed-mode 1C) test system comprising a hybrid mode integrated circuit and an automatic test device. The mixed mode integrated circuit includes an analog to digital converter, a phase locked loop, a timing pin, and a first in first out buffer. The analog to digital converter receives a test message 201209430 ° . ' Convert the D Hai test status number into a digital input data. The phase lock, the path receives the first-outer timing signal to generate the -input timing signal =^ f the sequence pin receives a second external timing signal. The FIFO is connected to the analog-to-digital converter, the phase-locked loop and the two-sequence-spin, according to the input timing signal, to write the digital input T into the Hz first-in first-out buffer And according to the second external timing message, X shoulders the data of the FIFO buffer. The automatic test device a mixes the mode integrated circuit to generate the test signal, the first-order, the second external timing signal, and the second external timing signal, and according to the ρ timing signal, to pick up the lock The data of the FIFO buffer. According to still another feature of the present invention, the present invention proposes a hybrid mode_circuit (mixed_mode π) test method, which is an automatic test, device s-type mixed mode integrated circuit, the mixed mode integrated circuit includes - Analog to digital converter, phase locked loop, a timing: pin and FIFO buffer, the method includes the following steps: The automatic test device generates a test signal, a first external timing signal: and a second external timing signal, wherein the test signal is generated according to a vertical bead material, and (B) the phase locked loop receives the The first outer Z sequence (four) 'to generate-input timing signal; (C) the analog to digital device (four) test (four) and the input timing minus, according to the input, the sequence is used to convert the test signal into a Digital input data; (D j in first-in first-out buffer according to the input timing signal, to input the digits into the first-in first-out buffer, and according to the second external time A唬' FIFO buffer data; (Ε) the automatic 201209430
圖4係本發明—種混合模式積體電路（mixed-mode IC) 的測試系統4 0 0之方塊圖，該混合模式積體電路測試系統 400匕括/吧5模式積體電路410及一自動測試裝置42〇。 該混合模式積體電路41〇包含一類比至數位轉換器 411、一相位鎖相迴路413、一時序接腳415、一先進先出 緩衝器417、及一控制電路419。 …該類比至數位轉換器411接收一測試訊號，並將該測 試訊號轉換成一數位輸入資料AD〇[n_〗〇]。 安叹场輸入時序訊號 一1以將該測試訊號轉換 該相位鎖相迴路4 i 3接收一第一外部時序訊號χ t，以 產生-輸入時序訊號clk」，其中，輸入時序訊號仙」的 頻率可為該第-外部時序訊號沿頻率的整數倍，例如輸 入時序訊號dkj的頻率可為該第一外部時序訊號幻頻率 的3倍或4倍，或者，輸入時序訊號仙」的頻率可為該第 一外部時序訊號糊率的非整數倍，例如輸入時序訊號 :1 k 一1的頻率可為該第一外部時序訊號XI頻率的2 · 5倍。 該類比至數位轉換器411接收該輪入 elk—I ’並依據該輸人時序訊號仙 成該數位輸入資料Α〇0[η-1:〇] 二外部時序訊號cik_〇。該第 為該第一外部時序訊號XI的 該時序接腳415接收一第二外部時 二外部時序訊號elk—〇的頻率為該第一 201209430 頻率之整數倍。同時，於本發明中，該輸入時序訊號仙 的頻率小於或等於該第二外部時序訊號cik。的頻率。 該先進先出緩衝器417連接至該類比至數位轉換器 川、該相位鎖相迴路413及該時序接腳415，依據該輸入 時序訊號clk_i，以將該數位輸入資料AD〇[ni 〇]寫入該 先進先出緩衝器417中，並依據該第二外部時序訊號 Clk-〇,以讀出該先進先出緩衝器417的資料，並中，該先 進先出緩衝ϋ依據其料的資料量，分別產生—全㈣ 標（Full)訊號及一空旗標（Empty)訊號。 該控制電路419連接至該相位鎖相迴路413及該時序 接腳41 5，依據該輸入時序訊號c 1 k 一 i及該第二外部時序訊 號c:k—〇用以產生忒先進先出緩衝器417的寫入（wriie) 及讀出（read)訊號。 泫自動測試裝置420連接至該混合模式積體電路 410用以產生該測試訊號、該第一外部時序訊號X[、及 /第外#時序汛號clk_〇，並依據該第二外部時序訊號 clk_o,進而拴鎖該先進先出緩衝器417的資料。 " 該自動測試裝置420依據内部的數位測試資料以產 生該測試訊號。由於該第二外部時序訊號係由該自 動測試裝置420所產生的，且該先進先出緩衝器417依據 ^第外。P時序汛號clk_〇及讀出（read)訊號而輸出資 料，因此該自動測試裝置42〇拴鎖的該先進先出緩衝器 417輸出之資料。於本實施例中，該先進先出緩衝器417 在該第二外部時序訊號dk一 〇的正緣時輸出資料，該自動 測。式扁置420可在該第二外部時序訊號仙—〇負緣時拴鎖 201209430 該先進先出緩衝器輸出之資料。當該自動測試 測^空旗標（Empty)訊號時，表示該先進先出 又有貝料’因此該自動測試裝置420將該先進先出 器41 7中所拴鎖之資料捨棄。 、、’ 圖5係本發明的時序圖。如圖请*，該輸入時序^ 二二的週期與該第二外部時序訊號dk—〇的週期比例 士為8,亦即’該輸人時序訊Hi的頻率略小於 該第一外部時序減clk一〇的頻率。如圖$所示，該類比 位轉換器411依序於該輸入時序訊號^的正緣時產 ^數=輸人資料彻㈣叫。該先進先出緩衝器417在 Π二寺序訊號，。的正緣輸出資料1自動測試 進先出^第一外部時序訊號clk-〇負緣時拾鎖該先 進先出緩衝器輸出之資料。當該自動測試裂 =(E—表示該先進先出緩衝器… ® A該自動測試裝置將該先進先出緩衝器 ⑴所拾鎖之㈣捨棄，其中，肖自_試裝置420拾鎖 :玄先進先出緩衝器417的輸出資料，並比對該輸出資料與 該數位測試資料，藉此即可量測該類比至數位轉換器川 的功能^ 圖6係本發明的另一時序圖。如圖6所示，該輸入時 序訊號clk—i的週期與該第二外部時序訊號仙―〇的週期 比分H可為1 . 1，亦即，該輸入時序訊號elk」的頻率等 於〇第夕卜序5fl號dk—〇的頻率。此時寫入該先進先 出緩衝器417的速度與讀出該先進先出緩衝器4i7的速度 相同® -亥自動挪5式裝置42〇伯測有全滿旗標（Fu⑴訊號 10 201209430 或空旗標（Empty)訊號產生時’即可表示該相位鎖相迴路 413不穩定。 圖7係本發明一種混合模式積體電路（mixed_m〇de 1(：) 的測試方法的流程圖’其係在一自動測試裝置420中測試 一混合模式積體電路410 ’該混合模式積體電路41〇包含 一類比至數位轉換器411、一相位鎖相迴路413、一時序 接腳415、及一先進先出緩衝器417。 首先’於步驟（A)中，該自動測試裝置42〇產生一測試 訊號、一第—外部時序訊號XI、及一第二外部時序訊號 elk—〇其中該測試訊號係依據一數位測試資料產生。 於步驟（B)中，該相位鎖相迴路413接收該第一外部時 序訊號XI’以產生一輸入時序訊號clk_i。 ;v驟（C )中’该類比至數位轉換器411接收該測試訊 號及該輸入時序訊號clk_i，依據該輸入時序訊號“、“乂 將該測試訊號轉換成一數位輸入資料ADO[n-1 :〇]。 ^於步驟（D)中，該先進先出緩衝器417依據該輸入時序 。扎號d1"-1 ’以將該數位輸入資料ADO[n-l:〇]寫入該先進 ，出緩衝器4丨7中，並依據該第二外部時序訊號clk_0，以 5貝出5玄先進先出緩衝器417的資料；以及 _於步驟（E)中，該自動測試裝置420拴鎖該先進先出緩 衝益417的輸出資料，並比對該輸出資料與該數位測試資 料。 _由前述說明可知，本發明技術可在低成本的自動測 °式裝置下進行混合模式積體電路的性能量測。但混合模 式積體電路的特性是每次啟動後的行為總是會有些許的 11 201209430 差異’將於習知自動測試裝置量測時帶來困擾，尤其在 自動測試裝置性能不佳時。而本發明的技術利用内建的 先進先出緩衝器’混合模式積體電路的與類比至數位轉 換器、相位鎖相迴路等類比電路連結，並輔以簡易控制， 即可解決習知自動測試裝置無法直接利用相位鎖相迴路 的輸出時序來擷取類比至數位轉換器資料的缺點。同時 藉由簡易的邏輯設計便能量測類比電路的整體性能並偵 測相位鎖相迴路的穩定度。 由上述可知，本發明無論就目的、手段及功效，均 =示=迥異於習知技術之特徵，極具實用價值。惟應注 思的疋，上述諸多實施例僅係為了便於說明而舉例而 已’本發日月所主張之權㈣®自應以巾請專利範圍所述 為準’而非僅限於上述實施例。 【圖式簡單說明】 混合模式積體電路 混合模式積體電路進 1係一混合模式積體電路的示意圖。 圖2係習知使用—自動測試裝置對 進行測試的示意圖。 圖3係習知使用一邏輯分析儀對一 行測試的示意圖。 圖4係本發明 圖0 種混合模式積體電路的測試系統之方塊 圖5係本發明的時序圖。 圖6係本發明的另一時序圖。 12 201209430 流程 圖7係本發明一種混合模式積體電路的測試方法的 圖0 【主要元件符號說明】 混合模式積體電路110 類比至數位轉換器120 相位鎖相迴路1 30 内部電路140 自動測試裝置150 邏輯分析儀160 混合模式積體電路的測試系統4〇〇 混合模式積體電路41 〇 類比至數位轉換器411 時序接腳415 控制電路419 自動測試裝置420 相位鎖相迴路413 先進先出緩衝器417 步驟（A)〜步驟（E) 134 is a block diagram of a test system 400 of a mixed mode integrated circuit (the mixed mode integrated circuit test system 400), which includes a /5 mode integrated circuit 410 and an automatic Test device 42〇. The mixed mode integrated circuit 41A includes an analog to digital converter 411, a phase locked loop 413, a timing pin 415, a first in first out buffer 417, and a control circuit 419. ...the analog to digital converter 411 receives a test signal and converts the test signal into a digital input data AD〇[n_〗. The sinus input timing signal 1 is used to convert the test signal to the phase locked loop 4 i 3 to receive a first external timing signal χ t to generate an -input timing signal clk", wherein the frequency of the input timing signal It may be an integer multiple of the frequency of the first external timing signal, for example, the frequency of the input timing signal dkj may be 3 times or 4 times of the magic frequency of the first external timing signal, or the frequency of the input timing signal may be The non-integer multiple of the first external timing signal rate, for example, the input timing signal: 1 k - 1 may be 2 · 5 times the frequency of the first external timing signal XI. The analog-to-digital converter 411 receives the round-up elk_I' and inputs the data Α〇0[η-1:〇] two external timing signals cik_〇 according to the input timing signal. The timing pin 415 of the first external timing signal XI receives a second external time. The frequency of the external timing signal elk_〇 is an integer multiple of the first 201209430 frequency. Meanwhile, in the present invention, the frequency of the input timing signal sen is less than or equal to the second external timing signal cik. Frequency of. The FIFO buffer 417 is connected to the analog-to-digital converter, the phase-locked loop 413, and the timing pin 415, and the digital input data AD〇[ni 〇] is written according to the input timing signal clk_i. Into the FIFO buffer 417, and according to the second external timing signal Clk-〇, to read the data of the FIFO buffer 417, and the FIFO buffer is based on the data amount of the material , respectively, generate a full (four) standard (Full) signal and an empty flag (Empty) signal. The control circuit 419 is connected to the phase locked loop 413 and the timing pin 41 5 , according to the input timing signal c 1 k i and the second external timing signal c: k — 〇 for generating a 忒 first in first out buffer The write (wriie) and read (read) signals of the device 417. The automatic test device 420 is connected to the mixed mode integrated circuit 410 for generating the test signal, the first external timing signal X[, and/or the outer # timing c c clk_〇, and according to the second external timing signal Clk_o, which in turn latches the data of the FIFO buffer 417. " The automatic test device 420 generates the test signal based on the internal digital test data. Since the second external timing signal is generated by the automatic test device 420, the FIFO buffer 417 is based on ^. The P timing signal clk_〇 and the read signal output the data, so the automatic test device 42 latches the data output by the FIFO buffer 417. In this embodiment, the FIFO buffer 417 outputs data when the positive edge of the second external timing signal dk is ,, the automatic measurement. The flat 420 can shackle the 201209430 FIFO output data during the second external timing signal. When the automatic test measures the empty signal, it indicates that the FIFO has a bedding material. Therefore, the automatic test device 420 discards the data locked in the advanced first-out device 41 7 . Fig. 5 is a timing chart of the present invention. As shown in the figure, the period of the input timing ^22 and the period of the second external timing signal dk_〇 are 8, which means that the frequency of the input timing Hi is slightly smaller than the first external timing minus clk A glimpse of the frequency. As shown in FIG. $, the analog-to-bit converter 411 sequentially generates the number of inputs when the positive edge of the input timing signal ^ is = the input data is called (four). The FIFO buffer 417 is in the signal of the second temple. The positive edge output data 1 is automatically tested. The first external timing signal clk-〇 negative edge picks up the data of the first-in first-out buffer output. When the automatic test split = (E - indicates the FIFO buffer ... ® A, the automatic test device discards the lock (4) picked up by the FIFO buffer (1), wherein the self-test device 420 picks up the lock: The output data of the FIFO buffer 417 compares the output data with the digital test data, thereby measuring the function of the analog to digital converter. FIG. 6 is another timing diagram of the present invention. As shown in FIG. 6, the period of the input timing signal clk_i and the period of the second external timing signal 〇 〇 can be 1. 1, that is, the frequency of the input timing signal elk" is equal to 〇 夕 卜The frequency of the df_〇 of the sequence 5fl. At this time, the speed of writing to the FIFO buffer 417 is the same as the speed of reading the FIFO buffer 4i7. The flag (Fu(1) signal 10 201209430 or the empty flag (Empty) signal is generated') indicates that the phase locked loop 413 is unstable. Fig. 7 is a mixed mode integrated circuit (mixed_m〇de 1(:) of the present invention Flowchart of the test method 'tested in an automated test device 420 A mixed mode integrated circuit 410' includes an analog to digital converter 411, a phase locked loop 413, a timing pin 415, and a first in first out buffer 417. In the step (A), the automatic test device 42 generates a test signal, an first external timing signal XI, and a second external timing signal elk, wherein the test signal is generated based on a digital test data. In B), the phase locked loop circuit 413 receives the first external timing signal XI' to generate an input timing signal clk_i. In the step (C), the analog to digital converter 411 receives the test signal and the input timing. The signal clk_i is converted into a digital input data ADO[n-1 :〇] according to the input timing signal “,”. In the step (D), the first in first out buffer 417 is based on the input timing. The number d1"-1' is written to the advanced input buffer ADO[nl:〇], and is outputted from the buffer 4丨7, and according to the second external timing signal clk_0, 5 The data of the buffer 417; And in step (E), the automatic test device 420 locks the output data of the FIFO buffer 417, and compares the output data with the digital test data. _ From the foregoing description, the technology of the present invention can be The low-performance automatic measuring device performs the energy measurement of the mixed mode integrated circuit. However, the characteristic of the mixed mode integrated circuit is that the behavior after each start is always a little 11 201209430 Difference 'will be learned automatically Test equipment measurement brings trouble, especially when the automatic test equipment performance is poor. The technology of the present invention utilizes the built-in FIFO buffer 'mixed mode integrated circuit' and analog to digital converter, phase lock phase The circuit is connected with analog circuits, and with simple control, it can solve the shortcomings of the analog automatic test device that can not directly use the output timing of the phase-locked loop to draw analog-to-digital converter data. At the same time, the overall performance of the analog circuit is measured by a simple logic design and the stability of the phase-locked loop is detected. It can be seen from the above that the present invention is extremely useful in terms of purpose, means, and efficacy, regardless of the characteristics of the prior art. It should be noted that the above-described embodiments are merely examples for convenience of explanation. The rights (4) of the present invention are based on the scope of the patent application, and are not limited to the above embodiments. [Simple diagram of the diagram] Mixed mode integrated circuit The mixed mode integrated circuit is a schematic diagram of a mixed mode integrated circuit. Figure 2 is a schematic diagram of a conventional test using an automated test device. Figure 3 is a schematic diagram of a conventional test using a logic analyzer. Figure 4 is a block diagram of a test system of the mixed mode integrated circuit of Figure 0. Figure 5 is a timing diagram of the present invention. Figure 6 is another timing diagram of the present invention. 12 201209430 Flowchart 7 is a diagram of a test method of a hybrid mode integrated circuit of the present invention. [Description of main component symbols] Mixed mode integrated circuit 110 Analog to digital converter 120 Phase locked loop 1 30 Internal circuit 140 Automatic test device 150 logic analyzer 160 test system of mixed mode integrated circuit 4〇〇 mixed mode integrated circuit 41 〇 analog to digital converter 411 timing pin 415 control circuit 419 automatic test device 420 phase lock circuit 413 FIFO buffer 417 Step (A) ~ Step (E) 13