TW201207621A - Method for dispatching and transmitting data stream, memory controller and memory storage apparatus - Google Patents

Abstract

A method for dispatching and transmitting data stream, which is used for a memory storage apparatus having a non-volatile memory module and a smart card chip, is provided. The method includes configuring a plurality of logical block addresses, wherein a plurality of specific logical block addresses are used for storing a specific file. The method also includes receiving a response data unit from the smart card chip and storing the response data unit in a buffer memory. The method also includes, when a logical block address corresponding to a read command from a host system belongs to the specific logical block addresses and there is a response data unit at the buffer memory, transmitting the response data unit stored at the buffer memory to the host system. Accordingly, the method can make the host system to correctly receive a response data unit from the smart card chip.

Description

201207621 10-0015 34915twf.doc/I VI. Description of the invention: [Technical field to which the invention pertains] It is a forest-related, and special method and a memory Zhao controller string using this method [Prior Art] Digital camera, action The speed of telephones and MP3 players is so rapid that the demand for storage media is also reduced to: for non-volatile record ships (for example, (four) jobs = electricity, small size, and no mechanical structure, etc. It is built into the various portable multi-ship devices exemplified above. It is suitable for users to gradually accept the use of electronic wallets and cards. Smart cards (s_c-d) have, for example, microprocessors and cards. Operating system, security module) The integrated circuit chip (IC chip) of the component, in order to allow the right-hand hidden smart card k for calculation, encryption, two-way communication and security functions, this card eliminates the bribe (four) Silk _ the function of protecting its data. The use of the Global Mobile Communication System (SIMT card) is one of the application examples of smart cards. However, the smart card itself is limited by the storage capacity, so in recent years Start to combine with a large number of storage and hiding needles, _ increase the storage of smart cards ^

201207621 --------(10)15 34915twtdoc/I amount. However, 'how to distinguish the data string from the host system in the memory card of the non-volatile memory module and the smart card chip is the command data unit belonging to the smart card chip and the response data unit from the smart card chip. Passing to the host system has become a problem to be solved by those skilled in the art. SUMMARY OF THE INVENTION The present invention provides a data string assignment and transmission method, a memory controller, and a S memory storage device that can efficiently transfer data units belonging to a smart card chip. Exemplary embodiments of the present invention provide a data string assignment and transmission method for a memory storage device having a non-volatile memory module and a smart card chip. The data string assignment and delivery method includes 'configuring a plurality of logical block addresses for the non-volatile record module, wherein a plurality of specific logical block addresses among the logical block addresses are used to store the specific (4). This data string assignment and transmission method also includes pure smart card wafer towel (4) should be the information sheet Where ‘and·1 in the buffer memory cap storage fine data unit. The data string assignment and transmission method further includes a pure spine instruction from the master age system; determining that the logical button address corresponding to the read age belongs to the ghost address of the miscellaneous area - and determining the buffer memory towel Whether to save this = should be the data unit. The data string assignment and transmission method also includes when the response block of the block block corresponding to the 2 fetch instructions is in the block address material, and the buffer unit contains the response unit, the transfer storage unit 201207621

Rar^OlO-0015 34915twf.doc/I The response data unit in this buffer memory is given to the host system. In an embodiment of the present invention, the data string assignment and transmission method further includes: when the logical block address corresponding to the read instruction belongs to one of the specific logical block addresses and the buffer memory When there is no response data unit, the second data string is transmitted to the host system, wherein each bit of the second data string is zero. In an embodiment of the present invention, the data string assignment and the transmission method are further included, and when the logical block address corresponding to the read instruction does not belong to one of the specific logical block addresses, according to Corresponding to the logical block address of the read command, the third data string corresponding to the read command is read from the non-volatile memory module and the third data string corresponding to the read command is transmitted to the host system. In an embodiment of the present invention, the data string assignment and transmission method further includes: receiving a write instruction from the host system and a first data string corresponding to the write instruction; determining whether the first data string contains a specific Mark; ^ and when the first data string contains a specific mark, the command data unit of the first data string is transferred to the smart card chip and the response data unit stored in the buffer memory is cleared. In an embodiment of the present invention, the data string assignment and transmission method further includes: when the first data string does not contain a specific tag, the first data is determined according to a logical block address corresponding to the write instruction. The string is written to the non-volatile memory module. An exemplary embodiment of the present invention provides a data string assignment and transmission method for a memory having a non-volatile memory module and a smart card chip.

34915twf.doc/I 201207621 -υ015 Storage device. The data string assignment and delivery method includes configuring a plurality of logical block addresses for the non-volatile record block module, wherein a plurality of specific logical block addresses among the logical block addresses are used to store a specific file. The data distribution and delivery method also includes receiving a response data unit from the smart card chip and storing the response data unit in the buffer memory. The data string assignment and transmission method further includes receiving a read instruction from the host system; determining whether a logical block address corresponding to the read instruction belongs to one of the specific logical block addresses and determining the buffer memory Whether there is a response data unit stored in it. The data string assignment and transmission method also includes determining that when the logical block address corresponding to the read instruction belongs to one of the specific logical block addresses and the response data unit is stored in the buffer memory Whether the logical block address of the read instruction corresponds to the access address unit. The data string assignment and transfer method further includes transmitting at least a portion of the response data unit stored in the buffer memory to the host system when the logical block address corresponding to the read instruction corresponds to the access address unit. In an embodiment of the present invention, the data string assignment and transmission method further includes: when the logical block address corresponding to the read instruction does not correspond to the address unit, the transmission is stored in the buffer memory. In response to an embodiment of the present invention, in the embodiment of the present invention, the data string assignment and the transfer method are further included: when the logical block address corresponding to the read instruction belongs to the logical block In the case of one of the addresses and the two data units in the buffer memory, the second data string is transmitted to the host system. ° In one embodiment of the present invention, the above data string assignment and transmission party 201207621

FSFU-^010-0015 34915twf.doc/I method further includes: when the logical block address corresponding to the read instruction does not belong to the - in the specific logical block record, (4) corresponds to the read finger ^ logical block bit The address is read from the non-volatile memory module corresponding to the ^ 2::: material string and the third data string corresponding to the read instruction is transmitted.

An exemplary embodiment of the present invention provides a memory controller including a memory interface, a memory management circuit, a host interface, and a buffer memory. The memory interface is coupled to the memory management circuit and coupled to the non-volatile S memory module. The host interface is coupled to the memory management circuit and is used to connect to the host system. Buffer memory_ to memory management circuit' and used to temporarily store data. The memory management circuit unit is configured to perform the above-described data string assignment and transmission method. An exemplary embodiment of the present invention provides a memory storage device including a connector, the non-volatile memory module, and a memory controller coupled to the non-volatile memory module. Here, the memory controller is configured to execute the above-described data string assignment and transmission method. Based on the above, the data string assignment and delivery method, the 己 memory controller and the memory storage system of the exemplary embodiment of the present invention can correctly transmit the instruction data unit and the response data unit of the smart card chip. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] [First Exemplary Embodiment] 201207621

---------U015 34915 tw£doc/I Figure A schematic block diagram of a host system and a cryptographic storage device according to a first exemplary embodiment of the present invention. "Monthly with reference to Figure 1 'The host system surface includes the microprocessor MN, the storage device blue, the cache memory and the smashing device brain. When the host system 1_ _, the micro-location " magic record line is installed in the storage device 11 The operating system 111G in =4, so that the host system (7) (10) provides a corresponding function according to the operation of the user. For example, in the host system, the lion is a mobile phone system and the operating system i 1 〇 8 is Symbian, Andr〇id or other operations. In the example of the system, after the master's degree, the user can operate the host system through the input/output device 11〇8 to perform communication, shadow, play, etc. Wei. Miscellaneous in this fan (four) wipes, domain system deleted However, in another exemplary embodiment of the present invention, the host system 1GGG is also a computer, a digital camera, a video camera, an audio player, or a video player. The memory storage device is used. The interface is connected to the host system 1000 to perform writing and reading of data according to an instruction from the operating system 1110 of the host system 1000. For example, in the example where the host system 1000 is a mobile phone system, the memory is stored. The device 100 can be a Secure Digital (SD) card, a Multi Media Card (MMC) card, a memory stick, a c〇mpact Flash (CF) card, or an embedded storage device. The embedded storage device includes an embedded multimedia card (EMMC). It is worth mentioning that the embedded multimedia card is directly coupled to the substrate of the host system. The memory storage device 100 includes the connector 1〇2. Memory controller 201207621

FSFD-2010-0015 34915twf.doc/I 104 and non-volatile memory module 1〇6. The connector 102 is a connector conforming to the SD standard. However, it must be understood that the present invention is not limited thereto, and the connector 102 may also be an MS standard, an MMC standard, a CF standard, an Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, and a high-speed peripheral component. Peripheral Component Interconnect Express (PCI Express) standard, Serial Advanced Technology Attachment (SATA) standard, Universal Serial Bus (USB) standard, Integrated Drive Electronics (Integrated Device Electronics, IDE) standard or other standard connector. The memory controller 104 is configured to execute a plurality of logic gates or control commands implemented in a hard type or a firmware type, and write data in the non-volatile memory module 106 according to an instruction of the host system 1000. Read and erase operations. The non-volatile memory module 106 is lightly connected to the memory controller • 丨〇 4 ' and is used to store data written by the host system 1000. The non-volatile memory module 106 includes a plurality of physical blocks. Each physical block has a plurality of physical pages respectively. Physical pages belonging to the same physical block can be independently written and erased simultaneously. In more detail, the physical block is the smallest unit of erasure. That is, each physical block contains a minimum number of memory cells that are erased. The entity page is the smallest unit that is stylized. That is, the intersecting page is the smallest element of the written data. However, it must be understood that in another exemplary embodiment of the present invention, the minimum unit of writing data may also be

2〇12〇m_ 34915twf.doc/I is a sector or other size. In the memory management method of the first exemplary embodiment of the present invention, the memory controller 104 logically groups the physical blocks of the non-volatile memory modules 1〇6 into a data area, a spare area, a system area, and a replacement. The area, wherein the physical blocks grouped into the data area and the spare area are rotated to store the data written by the host system 1000, and the physical block of the system area is used to store the system data of the memory storage device 100. The physical block of the replacement area is used to replace the bad physical block in the data area and the spare area. In addition, in order to enable the host system 1000 to conveniently access physical blocks that store data in a rotating manner, the memory controller 104 configures the logical block addresses LBA(0) to LBA(N) to map these. The physical block, whereby the host system can directly write and read data according to the logical block address. In the exemplary embodiment, the non-volatile memory module is a rewritable non-volatile memory module. For example, the non-volatile memory module is a Multi Level Cell (MLC) NAND flash memory module. However, the present invention is not limited thereto, and the non-volatile memory module 1 may be a single level cell (SLC) NAND flash memory module, other flash memory modules, or the like. Characteristic memory module. In the first exemplary embodiment of the present invention, the memory storage device 100 further includes a smart card chip 108. The smart card chip 108 is coupled to the memory controller 104 via a interface 108a, wherein the interface i〇8a is an interface specifically for communicating with the smart card chip 108. 201207621

FSPD-2010-0015 34915twf.doc/I The smart card chip 108 has a microprocessor, a security module, a read only memory (ROM), a random access memory (RAM), and a random access memory (RAM). Electronically Erasable Programmable Read-Only Memory (EEPROM), oscillator and other components. The microprocessor is used to control the overall operation of the smart card chip 108. The security module is used to encrypt and decrypt the data stored in the smart card chip 1〇8. The oscillator is used to generate the clock signal required for the smart card chip. Random access memory is used to temporarily store the data or firmware of the operation. Electronic erasable programmable read-only memory is used to store user data. The read-only memory is used to store the firmware of the smart card chip 1〇8. Specifically, when the smart card chip 1 运作 8 is operated, the microprocessor of the smart card chip 1 会 8 executes the firmware program in the read-only memory to perform the related operations. In particular, the security module of smart card chip 108 performs a security mechanism to prevent attacks that would otherwise steal data stored in smart card chip 108. For example, this attack includes a timing attack, a single shgle-power-analysis attack, or a differential-power-analysis. In addition, the security mechanism implemented by the smart card chip 1〇8 is in compliance with federal information processing standards (Federal Informati〇n

Processing Standards, FIPS) The third level or higher of 140-2 or the third level or higher of EMVEL, that is, the smart card chip 108 is certified by Level 4 or higher of FIPS 140-2 or Passed the fourth level or higher certification of EMVEL. Here, FIPS is a contractor of the government agencies and governments that the US federal government has established for all military agencies.

34915tw£d〇c/I 201207621· The public use of the 'French' FN>s 14()·2 has established a level of safety. In addition, 'EMV is the international financial industry for the smart card and the use of the chip card point of sale (pomt-〇f-saie, P0S) terminal, as well as the banking institutions are widely set up, the automatic counters and other gorges of the professional stomach The standard of the certificate. This specification is set for the related software and hardware of Crystal #卡魏金卡's supporting secret (four) Fu System). In the case of the smart card, the memory storage device 1 can provide an identity authentication service, such as a micropayment service, a ticket service, etc., by the operation of the smart card chip 108.

Figure 2 is a schematic block diagram of a memory controller according to a first exemplary embodiment of the present invention. Referring to FIG. 2, the memory controller 1〇4 includes a memory management circuit 202, a host interface 204, a memory interface 206, and a buffer memory 2〇8.

The memory management circuit 202 is used to control the overall operation of the memory controller 1〇4. Specifically, the memory management circuit 2〇2 has a plurality of control fingers 7, and when the memory storage device 100 operates, such control commands are executed to perform the data string assignment and transmission method according to the first exemplary embodiment and The memory management method is used to manage the non-volatile memory module 106. In the present exemplary embodiment, the control commands of the memory management circuit 202 are implemented in a firmware version. For example, the memory management circuit 2 (with a processor unit (not shown) and read-only memory (not shown), and this control command is burned into this read-only memory. t depends on the storage When ^00 is in operation, such (four) ages are performed by the micro-processing! I unit. According to the first exemplary embodiment of the present invention, the data string assignment and transmission method = and the memory method. 12 201207621

PSPD-201〇^)〇i5 34915twf.doc/I In another exemplary embodiment of the present invention, the control command of the memory management circuit 2〇2 may also be stored in the non-volatile memory module 106 in a code pattern. The area (for example, the system area in the memory module dedicated to storing system data). In addition, the memory management circuit 202 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). The read-only memory has a drive code segment. And when the modal controller 1 〇 4 is enabled, the microprocessor unit first performs the stimuli to load the control commands stored in the non-volatile memory module 106 into the body management circuit. 202 in random access memory. Thereafter, the microprocessor benefit 7C runs these control instructions to execute the data string assignment and transfer method and the memory management method of the first exemplary embodiment of the present invention. In addition, in another exemplary embodiment of the present invention, the control command of the memory management circuit 2〇2 can also be implemented in a hardware type.

The host interface 204 is coupled to the memory management circuit 2〇2 and is configured to receive and identify the instructions and data transmitted by the host system. That is to say, the commands and data transmitted by the host system 1000 are transmitted to the memory management circuit 2〇2 through the host interface 2〇4. In the present exemplary embodiment, the host "face 204" is an interface conforming to the SD standard. However, it must be understood that the present invention is not limited thereto, and the host interface 2〇4 may also conform to the MS standard, MMC #准, CF standard, PATA. Standard, IEEE 1394 standard, PCI

Express standard, SATA standard, USB standard, standard or other standard interface. The memory interface 206 is coupled to the memory management circuit 2〇2 and is used to access the non-volatile memory module 106. In other words, want to write to non 201207621

--------U015 34915twf.doc/I The data of the volatile memory module 106 is converted to a format acceptable to the non-volatile memory module 106 via the memory interface 206. The buffer memory 208 is coupled to the memory management circuit 202 and is used to temporarily store data and instructions from the host system 1000 or data from the non-volatile memory module 106. In an exemplary embodiment of the invention, the memory controller 1〇4 further includes a power management circuit 254. The power management circuit 254 is coupled to the memory management circuit 202 and is used to control the power of the memory storage device 1A. In an exemplary embodiment of the present invention, the memory controller 〇4 further includes an error checking and correcting circuit 256. The error checking and correcting circuit 256 is coupled to the memory management circuit 202 and configured to perform an error checking and correcting process. Ensure the correctness of the information. Specifically, when the memory management circuit 2〇2 receives a write command from the host system 1000, the error check and correction circuit 256 generates a corresponding error check and correction code for the data corresponding to the write command (Error Checking). And Correction Code, ECC Code), and the suffix system 202 writes the data corresponding to the write command and the corresponding error check and correction code into the non-volatile memory module 〇6. Thereafter, when the memory official circuit 202 reads the data from the non-volatile memory module, the error check and correction code corresponding to the data is simultaneously read, and the error check and correction circuit 256 checks and corrects according to the error. The code performs an error check and correction procedure on the data read. It is worth mentioning that the smart card chip 1 8 receives the command and data from the host system 1000 and transmits the data to the host system 1000' through the connector 102 of the memory storage device 1 instead of directly transmitting the smart card. surface

201207621 FSFU-2010-0015 34915twf.doc/I (ie, 'interface l〇8a) communicates with host system 1000. Accordingly, in the first exemplary embodiment of the present invention, the 'application 112 0 will be installed in the host system' to process the command data unit to be transmitted to the smart card wafer 108 and the response to identify the smart card wafer 108. Data unit. For example, in the present exemplary embodiment, the command data unit transmitted to the smart card chip 108 is referred to as a Command-Application Pfotoeol Data Unit (C-APDU) and is derived from the smart card chip ι8. The response data unit is called a Response-Application Protocol Data Unit (R-APDU). In particular, the memory controller 104 recognizes and transmits the C_APDU and the R-APDU of the smart card chip 1 to 8 according to the data string transmission and assignment method of the first exemplary embodiment. That is, when the host system 1 operates the memory storage device 100 having the architecture of the non-volatile memory module 106 and the smart card chip 108, the memory controller 104 cooperates with the operation of the application 1120. A data string transfer and dispatch method according to a first exemplary embodiment of the present invention transmits and dispatches a C-APDU to be distributed to a smart card chip to correctly transfer a data string belonging to the C-APDU to the smart card chip ι 8 and The R-APDU from the smart card chip 108 is correctly transmitted back to the host system 1000. In the present exemplary embodiment, the application 1120 stores one or more files in the memory storage device 100 and transmits information for storing the logical block addresses of the one or more files to the memory controller 104. ^ For example, 'When the application 1120 issues an instruction to store the file RF in the memory storage device 1,, the operating system 丨丨1〇 will be based on the memory storage device 15 2〇12〇7621 -------- -U〇15

The 34915twf.doc/I 1(8) file (4) (not shown) uses a portion of the logical block address (eg, logical block addresses LBA(0) to LBA(K)) to write to the archive. Here, the logical block address used to store the file RF is referred to as a specific logical block address (as indicated by the slanted line in Fig. 3). In particular, in the present exemplary embodiment, any operation for the smart card chip 1-8 is performed by the application 1120 accessing the file. That is to say, the application 1120 transmits the C-APDU to the § memory storage device 1 through the write command 7 for the scam, and reads the instruction from the memory RF from the memory storage device (10). It is read that the 'in other operating system' application (10) can also directly access the specific logical block address of the corresponding file RF to perform operations on the smart card chip 108. Specifically, the memory management circuit 2〇2 of the memory controller 104 will include a state machine and update the heterogeneous state according to the host system 1 to the smart card wafer 108. In addition, when the application 1120 accesses the financial RF, the memory controller determines whether to send the data string from the host system 1000 to the smart card chip (10) or (4) to respond to the message according to the state of the state machine. Returned to the host system 1〇〇〇. Figure 4 is a schematic illustration of a state machine in accordance with a first exemplary embodiment of the present invention. Referring to FIG. 4, when the memory storage device 1 starts to operate, the state machine is in an idle state (Idle) state 401. During the idle state, the memory control B 104 determines the write from the host system 1〇〇〇. Entry instruction is

201207621 FbFD-2O10-0015 34915twf.doc/I No Is the data string corresponding to the specific logical block address and corresponding to this write command (hereinafter referred to as the first data string) contain a specific tag. Specifically, when the application 1120 transmits the C-APDU to the memory storage device 100, the application 1120 encapsulates the specific tag and the C-APDU into a data string to be written to the file RF and the operating system 111 is directed to the memory. The storage device 100 issues a write command to write the data string to a particular logical block address. For example, this particular tag is recorded in the header of this data string. Therefore, when the memory storage device 100 receives the write command and the data string corresponding to the write commands from the host system 1000, the memory management circuit 2〇2 recognizes that the write command corresponds to a specific logical region. The block address and the data string corresponding to the write command contain a specific tag, thereby transferring the C-APDU in the data string to the smart card chip 1〇8. After the memory management circuit 202 transmits the C-APDU to the smart card wafer 108, the state opportunity is in an in progress state 403. During the processing state 403, the memory controller 1〇4 will wait for the R-APDU from the smart card chip 108. That is, the processing state 403 indicates that the memory management circuit 202 has not received the R-APDU from the smart card chip. If the application 1120 issues a read command corresponding to the read file RF during the processing state, the memory management circuit 202 replies to the preset data string (hereinafter referred to as the second data string) to the host system 1000. In the exemplary embodiment, both the memory controller 104 and the application 1120 transfer the instruction data unit of the smart card chip according to the access address unit. For example, in this exemplary embodiment, the access address unit is 8 kilobytes (kilobyte, KB), and the second data string is set to a data volume of 8 KB and each 17 201207621 - υ 015

The 34915twf.doc/I bit is a data string of 0. In particular, upon receiving the second data string, the application 1120 will recognize that the R-APDU was not successfully received and attempt to receive the R-APDU from the memory storage device 1 by continuously polling. Upon receipt of the R-APDU of smart card wafer 108, the state of the state machine changes from processing state 403 to data available state 405. During the data available state 405, the memory controller 1〇4 will wait for the host system 1000 to transmit a read command corresponding to a particular logical block address. Specifically, the 'memory management circuit 202 stores the R-APDUs received from the smart card chip 1 在 8 in the buffer memory 208, and when receiving a corresponding logical block address from the host system 1000 When the command is read, the stored R-APDU is transmitted to the host system (ie, in particular, after the stored R-APDU is transmitted to the host system ι〇0, the state of the state machine is from the data available state. 405 changes back to idle state 401. Thus, memory controller 104 can receive the next c_APDU from host system 1 and pass it to smart card wafer 108. In an exemplary embodiment of the invention, memory storage device 1 The data transfer with the host system 1000 passes through the cache memory 1106. Specifically, when the host system 1 reads data from the memory storage device 1 , the host system 1 The system 丨丨丨0 will improve the performance by means of prefetch. For example, when the application program 112 of the host age 1GGG starts from the logical block address LBA (〇) of the memory storage device 8 (8) Take the amount of data 8KB When the host system Shu _ operating system 1110 will be open from LBA s own memory storage apparatus 1〇〇 of LBA (square) 201 207 621

PSPD-2010-0015 34915twf.docA Start reading data with a data volume of 64 KB and store this data in 1106. Therefore, when the data to be read by the next read command is already in the cache memory 1106, the operating system of the host system will be able to directly read from the cache memory 11〇6. This data, by access speed β π

It is worth mentioning that, in order to prevent the host system 1's operating system 1110 from directly providing this data from the cache memory il〇6 to the application 1120 and affecting the transmission of the smart card chip i〇8^R_APDU, In this exemplary embodiment, the size of the file RF is designed to be larger than the size of the cache memory 11〇6. Accordingly, when the application 1120 reads the file each time, the job system 1110 must re-read the data in the memory storage device 1 . FIG. 5 is a schematic diagram of pre-read data flow according to the first exemplary embodiment of the present invention. The memory controller 104 has not obtained the R_ApDU from the smart card chip 108 when the read command is issued by the operating system 111. Example. Referring to Fig. 5, the application 1120 transmits a read request RR1 indicating that the data having a data amount of 8 KB is read from the specific remote block address LBA(O) to the operating system 1110 (data stream S501). It is assumed that the cache memory 1106 does not store the data corresponding to the specific logical block address LBA(O). Therefore, the operating system mo transmits the data of 64 KB from the specific logical block address in the pre-read mode. The read command RC is supplied to the memory controller 1〇4 (data stream S503). Since the memory controller 104 has not yet been taken from the smart card chip 1〇8

201207621 Α JU^-AV Ά v-0015 34915twf.doc/I The R-APDU is acquired, so the memory controller 104 transmits the second data string DS2 to the host system 1000 (data stream S505). It is worth mentioning that, since the size of the second data string DS2 is 8 KB, in response to the read command RC for reading data of 64 KB from the specific logical block address LBA(O), the memory controller 1〇4 will fill the whole pad bit pb with the data volume of 56KB after the second data string DS2, and then transfer the data string containing the second data string DS2 and the whole pad bit PB to the host system 1〇〇〇 . Accordingly, the data string containing the second data string DS2 and the whole pad bit pb is stored in the cache memory 1106.

Thereafter, the operating system 1110 transfers the data of the first 8 KB of the cache memory i 106 (i.e., the 'second data string DS2') to the application program 20 (data stream S507). FIG. 6 is a schematic diagram of a pre-read data stream according to a first exemplary embodiment of the present invention. FIG. 6 is a schematic diagram of the memory controller 104 having been read from the smart card chip when the read command is issued in the operating system. Example 8 of Obtaining R_ApDU in 8 Referring to FIG. 6, in the data stream S6〇1, the smart card chip 1〇8 transfers the R-APDU to the memory controller 丨〇4. In the data stream S603, the application 112 transmits a read request for reading the data of 8 KB from the specific logical block address LBA(O) to the operating system 111. ° Assume that the cache memory does not have data corresponding to the specific logical block address LBA(O), so the operating system 1UG will transmit in the pre-read mode from the specific logic (four) block (four) to read the f amount to 6 Reading of the information 20 201207621

PSPD-2010-0015 34915twf.doc/I fetches the command RC to the memory controller 104 (data stream S605).

Since the memory controller 104 has taken the R-APDU from the smart card chip 108 at this time, the memory controller 104 transmits the R-APDU to the host system 1000 (data stream S607). It is worth mentioning that due to R-APDU

The size is 8 KB, so in response to the read command rc of the data having a data volume of 64 KB from the specific logical block address LBA(O), the memory controller 104 fills in the data amount after the R-APDU. The 56KB full pad bit PB 'and then transmits the data string containing the R-APDU and the whole pad bit PB to the host system 1〇〇〇. Accordingly, the data string including the R ApDU and the whole pad pB is stored in the cache memory 11〇6. Thereafter, the operating system 111 transmits the first 8 KB of data (, R-APDU) in the cache memory 1 to 6 to the application 112 (data stream S6〇9). Miaoίΐ—Improve that although the operating system 111G is mostly in one reading, 曰I: reads pre-read data. However, in the exemplary embodiment of the present invention, the operating system U1G of the ~1429 touch is sometimes referred to by a plurality of readings. When the application of the second system_ reads the data of 8ΚΒ, the ft block address LBA (〇) starts 1110 and takes two read commands to obtain the operating system of the j system 1000. For example, the operating system uω will be ^, ^ The amount of material is 64KB. Example 10 〇 logical two-dimensional read command from memory storage

The information, but began to read the amount of information for the money.冉下心—A remaining material to read _63.5KB FIG. 7 is a pre-read according to the first exemplary embodiment of the present invention.

34915twf.doc/I 201207621_ * wa mw λ v — 0013 A data flow diagram showing that the memory controller 〇4 operates in a pre-read mode to read data from the operating system iii _ received from the smart card chip (10) An example of an R-APDU. Referring to Fig. 7, in the data stream S701, the application program 2 (3 transmits a read request RR1 indicating that the data is read from the specific logical block address LBA(G)_ is (10)^ to the operating system 111. The data of the corresponding logical block address LBA(O) is not stored in the memory file 1106. Therefore, the operating system 111G transfers the data amount from the specific logical block address to 64 KB in the pre-read mode. The reading of the data is given to the § memory controller 104. In the data stream s7 〇 3, the operating system liio will first read the data of the previous KB 5 KB with the read command rci. The processor 104 has not yet obtained the R-APDU from the smart card chip 1〇8, so the memory controller 丨04 transmits the second data string Μ2 to the host system 1000 (data stream S705). It is worth mentioning that, due to the second The size of the data string is 8 KB, so in response to reading the data from the specific logical block address LBA(O), the read command RC1 ' & the memory controller 1〇4 will only read data. The first 0.5 KB of the data in the second data string ds2 is transmitted to the host system 1〇〇〇. In the data stream S707 The memory controller 1〇4 receives the R-APDU from the smart card chip 1〇8. Thereafter, in the data stream S709, the operating system mo reads the subsequent 63.5 KB of data by the read command RC2. The memory controller 104 has taken the R-APDU from the smart card chip 1〇8, so the memory controller 104 will transmit r_apdij to 22 201207621

PSPD-2010-0015 34915twf.doc/I

Host system 1000 (data stream S711). It is worth mentioning that since the size of the R-ApDU is 8 KB, the memory controller 104 responds to the read command RC2 of the data having a data volume of 63.5 KB from the specific logical block address lba(〇). A full pad PB of 55 5 KB is filled in after the R-APDU, and then the data string containing the R-APDU and the whole pad pB is transmitted to the host system 1 〇〇〇. Accordingly, the data string including the partial second data string, the R APDU and the integer bit ρβ is stored in the cache memory φ 1106. Thereafter, the operating system 1110 transmits the data of the first 8 pages of the cache memory to the application 1120 (data stream S713). It is worth mentioning that, since the 0.5 KB data in the first 8 KB of the cache memory 1106 is part of the second data string ds2 and the subsequent 7.5 KB data is part of the R-APDU, the application 1120 The R-APDU will be received. In particular, according to FIG. 4, after the memory management circuit 2〇2 of the memory controller 104 transfers the R_ApDU to the host system 1000, the state of the state machine becomes an idle state, whereby * indicates that the transfer application has been completed. The R_APDU that is transmitted by the c_APD1J and the smart card chip 108 transmitted by the 1120. However, at this time, the application 112 识别 recognizes that the received r_APDu is incomplete and resends the request to read the R-APDU by the error detection technology. In order to deal with the above error transmission, in the exemplary embodiment of the present invention, after the stored R-APDU is transmitted to the host system 1 , the memory management circuit 2〇2 does not immediately clear the buffer memory. R-APDU in 2〇8. For example, the memory management circuit 2〇2 will receive the next 23

34915twf.doc/I 201207621 ____ »υ015 C-APDUs will be cleared by the stored R_ApDU. In addition, during the idle state 401, when the memory storage device 100 receives a read command corresponding to a specific logical block address from the host system 1_, the memory management circuit 202 will again store the buffer memory 2〇8. The r_a ugly is transferred to the host system 1000. Referring to FIG. 7, in the data stream s715, the application program 112 transmits the read request RR2 of the data having the data volume of 8 给 to the operating system 1100 again by the LBA (9). In the stream S717, the operating system 111 reads 64 KB of data by the read command RC3. Since the R-APDU has been stored in the buffer memory 208 of the memory controller 1〇4, the memory controller 1〇4 will transfer the R_ApDl^ data amount=6KB full pad a PB to the host system chat ( After the data stream, the operating system 111 transmits the data of the first 8 kappa in the cache memory 1 to 6 to the application 112 (data stream S721). Based on this, when the operating system 1_(4) phase-read command is pure When the pre-spinning operation is performed, the application 1120 can obtain the correct r_APDu. FIG. 8 is a flowchart of the data string assignment and transmission method according to the first exemplary embodiment of the present invention, which shows that the write instruction is received. Please refer to FIG. 8 'In step S8〇1, the memory management circuit 202 of the memory controller 1〇4 receives the write command and the write command from the host system 1A. The first data string. 24 201207621

FSFU-2010-0015 34915twf.doc/I In step S803, the memory management circuit 202 determines whether the logical block address corresponding to the write instruction belongs to a specific logical block address. If the logical block address corresponding to the write command does not belong to a specific logical block address, then the memory management circuit 202 writes the first data string to the non-volatile memory according to the write command in step S805. Body module 1〇6. If the logical block address corresponding to the write command belongs to a specific logical block address, then the memory management circuit 202 determines in step S807 whether the first data string contains a specific tag or not. When marking, the memory management circuit 202 transmits the C-APDU in the first data string (ie, the portion of the first data string that does not contain the specific mark) to the smart card wafer 108 in step S809, and in step S811. The middle memory management circuit 202 clears the R-APDUs stored in the buffer memory 208. In particular, at this time, the state machine changes from the idle state 401 to the processing state 403. If it is judged in step S807 that the first data string does not contain a specific flag, then the flow of Fig. 8 is ended. 9 is a flow chart of a data string assignment and transmission method according to a first exemplary embodiment of the present invention, which illustrates a processing step of receiving a read instruction. Referring to Fig. 9' in step S9〇i, the memory management circuit 202 of the memory controller 1() 4 receives the read command from the host system 1A. In step S903, the memory management circuit 202 determines whether the logical block address corresponding to the read instruction belongs to a specific logical block address. If the logical block address corresponding to this read instruction does not belong to a specific logic 25

201207621 U015 34915twf.doc/I Block Address] 'In step _5, the memory management circuit 2 (10) reads data from the non-volatile memory module 1〇6 according to the read command (hereinafter referred to as the first The three data strings are transmitted to the host system 1000. If the block address corresponding to the read command belongs to a specific logical block address, the memory management circuit 2〇2 determines whether the state machine is in the data available state 4〇5 or the idle state 4〇 in step S907. 1. If the state machine is not in the data available state 4〇5 or the intervening state 4〇1, the memory management circuit 2〇2 transmits the second data string to the host system 1000 in step S909. If the state machine is in the data available state 405 or the idle state 401, the memory management circuit 202 determines in step S9U whether or not there is an R-APDU in the buffer memory 208. If there is no R-APDU in the buffer memory 208, step S909 is executed. If R-APdu is stored in the buffer memory 202, the memory management circuit 202 transfers the R-APDU to the host system 1000 in step S913. The manner of transmitting the second data string and the R_APDU has been described above in conjunction with Figs. 5, 6 and 7, and the description will not be repeated here. [Second exemplary embodiment] The memory storage device and the host system of the second exemplary embodiment of the present invention are essentially the same as the memory storage device and the host system of the first exemplary embodiment, wherein the difference lies in the second exemplary embodiment. The memory controller uses different methods to dispatch and transmit R-APDUs for smart card chips. The second exemplary embodiment will be described below using the apparatus structure of Figs. 1 to 3. In the second exemplary embodiment, when reading from the host system 1000 26 201207621

^0-2010-0015 34915twf.doc/I When the logical block address corresponding to the fetch instruction belongs to a specific logical block address, S1, body control 1 1G4 | determine the logical block bit corresponding to the read instruction Whether the address is a multiple of the above-mentioned access address unit. Moreover, when the logical block address corresponding to the read command of the host system 1000 is not a multiple of the access address unit, the memory controller 1〇4 will recognize the host system 1 Read instructions to perform prefetching. Based on this, the memory controller 1〇4 segments the R-APDUs to the host system 1〇〇〇. 10 is a schematic diagram of a pre-read data stream according to a second exemplary embodiment of the present invention, which shows that the memory controller 104 has been slaved from the smart card chip when the operating system 111 has issued a read command. Get an example of R_APDU. Referring to Fig. 10', in the data stream S1001, the smart card chip 1〇8 transfers the R-APDU to the memory controller 1〇4. In the data stream S1003, the application 1120 transmits a read request RR1 indicating that the data having a data amount of 8 KB is read from the specific logical block address LBA(0) to the operating system 1110. Lu assumes that the cache memory Π06 does not have data corresponding to the specific logical block address LBA(O), so the operating system 1110 will transfer the read data from the specific logical block address to 64 KB in pre-read mode. The data read command is sent to the memory controller 104, wherein in the data stream S1005, the operating system 1110 first reads the first 0.5 KB of data with the read command RC1. Since the R-APDU is already stored in the buffer memory 208 at this time, the memory controller 104 transfers the first 0.5 KB of data in the R-APDU to the host system 1000 (data stream S1007). 27 201207621 .0015

After 34915twf.doc/I, the operating system ΐπ〇 in the data stream S1009 will read the next 63.5 KB of data with the read command RC2. At this time, the memory controller 104 recognizes that the logical block address of the read command RC2 is not a multiple of the access address unit, and accordingly, the memory controller 1〇4 will follow the next 7.5 KB of the R-APDU. The data is transferred to the host system 1000 (data stream S1011). Similarly, the memory controller 1〇4 fills the entire pad level pb with a data volume of 56 KB after the R-APDU in response to reading the 63.5 KB read command RC2. Thereafter, the operating system 1110 transfers the first 8 KB of data (i.e., R-APDU) in the cache memory 1106 to the application 1120 (data stream S1013). Therefore, in the second exemplary embodiment, the memory controller 104 can transmit the portion of the cache memory U 〇 6 corresponding to the R-A PDU to the host system 1000 according to the logical block address corresponding to the read command. Thus, the problem of the application system 1120 being unable to receive the correct R-APDU when the operating system 1110 uses a plurality of read commands to perform the pre-read operation is thereby prevented. FIG. 11 is a flowchart of a data string assignment and transmission method according to a second exemplary embodiment of the present invention, which illustrates a processing step of receiving a read instruction. Referring to Fig. 11, in step S1101, the memory management circuit 202 of the memory controller 104 receives a read command from the host system 1A. In step S1103, the memory management circuit 202 determines whether the logical block address corresponding to the read instruction belongs to a specific logical block address. If the logical block address corresponding to the read instruction does not belong to a specific logical block address, the memory management circuit 202 will comply with the process in step S1105.

Raru-^O 10-0015 34915twf.doc/I According to this read command, data is read from the non-volatile memory module 16 (hereinafter referred to as a third data string) and the third data string is transmitted to the host. System 1000. If the logical block address corresponding to the read command belongs to a specific logical block address, the memory management circuit 2〇2 judges whether or not r_apdu exists in the buffer memory 208 in step S1107. If R_APD1J is not stored in the buffer memory 208, the memory management circuit 202 transmits the second data string to the host system (8) in step S1109. If the R-APDU is stored in the buffer memory 208, the memory management circuit 202 determines in step S1111 whether the logical block address corresponding to the read instruction corresponds to the access address unit (ie, corresponds to the read instruction). Whether the logical block address is a multiple of the access address unit). If the logical block address corresponding to the read instruction corresponds to the access address unit, the memory management circuit 202 transmits at least part of the R_APDU to the host system 1000 according to the data read amount of the corresponding read command in step S1113. And record the part that has been transferred. If the logical block address corresponding to the read command does not correspond to the access address unit, the memory management circuit 202 continues in accordance with the previously transmitted portion and the data read amount corresponding to the read command in step S1115. The other part of the R-APDU is transferred to the host system 1 and the transmitted part is recorded. It is worth mentioning that in the second exemplary embodiment, after the complete R-APDU has been transmitted to the host system, the state of the state machine changes from the data available state to the idle state. In summary, the data string assignment and delivery method of the exemplary embodiment of the present invention stores the response data unit of the smart card chip in the buffer memory. 29 201207621 ►-O015

34915 twf.doc/I In addition, when the state machine is in an idle state and receives an instruction to read the response data unit, the data string assignment and transfer method of the exemplary embodiment of the present invention transmits the response data unit stored in the buffer memory. To the host system, thereby allowing the host system to repeatedly read the response data unit. In addition, the data string assignment and transfer method of the exemplary embodiment of the present invention identifies the segment read behavior of the host system according to the logical block address of the read command of the read response data unit, thereby being included in the response data unit. The corresponding part is transmitted to the host system. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of a host system and a delta memory storage device according to a first exemplary embodiment of the present invention. Fig. 2 is a schematic block diagram of a memory controller according to a first exemplary embodiment of the present invention. FIG. 3 is a schematic diagram of accessing an application according to a first exemplary embodiment of the present invention. 4 is a schematic diagram of a state machine according to a first exemplary embodiment of the present invention. FIG. 5 is a schematic diagram of a pre-read data flow according to a first exemplary embodiment of the present invention. 201207621 r^wOlO-00,5 34915twf.doc^ - Figure 6 is a schematic diagram of a pre-read data stream according to a first exemplary embodiment of the present invention. Figure 7 is a schematic diagram of a pre-read data stream according to a first exemplary embodiment of the present invention. Figure 8 is a flow chart showing a corresponding write command among the eight-party and transfer methods according to the first exemplary embodiment of the present invention. 77 派和: The data string shown in the first exemplary embodiment is invented to make a flow chart corresponding to the read instruction. The second embodiment of the present invention is a pre-reading data string as shown in the second exemplary embodiment. [Main component symbol description] 100 102 104 106 108 Memory storage device connector memory controller is non-volatile Memory module smart card chip 108a · interface 1〇〇〇: host system 11〇2: microprocessor 1104: storage device 1106: cache memory 31

34915twf.doc/I 201207621 _________υ〇ΐ5 1108: Input/output device 1110: Operating system 1120: Application 202: Memory management circuit 204: Host interface 206: Memory interface 208: Buffer memory 254: Power management circuit 256: Error checking and correction circuit LBA(0) to LBA(N): logical block address 401: idle state 403: processing state 405: data available state S5 (H, S503, S505, S507, S601, S603, S605, S607 , S609, S7 (H, S703, S705, S707, S709, S711, S713, S715, S717, S719, S721: data stream S801, S803, S805, S807, S809, S8U, S901, S903, S905, S907, S909 , S9U, S913: Step S10 of data string assignment and transmission (H, S1003, S1005, S1007, S1009, S1011, S1013: data stream S1101, S1103, S1105, S1107, S1109, S1111, S1113, S1115: data string assignment and Step 32 of the transfer

Claims (1)

201207621 ^JJ-2U10-0015 34915twf.doc/I VII. Patent Application Range: 1. A data string assignment and transmission method for a memory storage device having a non-volatile memory module and a smart card chip The data string assignment and transmission method includes: configuring a plurality of logical block addresses for the non-volatile memory module, wherein a plurality of specific logical block addresses among the logical block addresses are used for storing a specific file; .Φ receives a response data unit from the smart card chip, and stores the response data unit in a buffer memory; receives a read command from a host system; and determines a corresponding read command Whether the logical block address belongs to one of the specific logical block addresses and determines whether the response data unit exists in the buffer memory; and when the logical block address corresponding to the read instruction belongs to the Transmitting the response data unit stored in the buffer memory when one of the specific logical block addresses and the response data unit are stored in the buffer memory 2. For the host system, 2. The data string assignment and transmission method as described in claim 1 further includes: when the logical block address corresponding to the read instruction belongs to the specific logical block address When one of the buffer data stores does not have the response data unit, a second data string is transmitted to the host system, wherein each bit of the second data string is zero. 3. The method of assigning and transmitting the data string as described in item 1 of the scope of patent application 33 201207621 -u015 34915twf.doc/I method, further comprising: determining the logical block address of the logical block corresponding to the read instruction In one case, according to the fourth address, the third data string of the instruction that reads the instruction from the non-volatile memory modulo does not belong to the special logical block address and will correspond to the read read corresponding to the read string transfer Give the host system. The third data of the instruction 4. The method of claim 2, further comprising: assigning and transmitting a first data string from the host system to receive a write finger; Whether the write command contains a specific mark; and the first data string containing the specific mark and the - command data sheet are read to the second data string in the buffered dragon towel_return material list Clear the storage method 5, the more W rectification 帛 4 items of the article and the transmission m. If the data string does not contain the specific tag, then the logical block address corresponding to the corresponding ― Data-based memory module. 6. A data string assignment and transmission method for a memory storage device having a non-volatile memory module and a smart card chip, the data string assignment and transmission The method includes: configuring a plurality of logical block addresses for the non-volatile memory module, wherein a plurality of specific logical block addresses among the logical block addresses are used for 34 201207621 nr^rwOlO-0015 34915twf .doc/l stores a specific file Receiving a response data unit from the smart card chip, and storing the response data unit in a buffer memory; receiving a read command from a host system; determining a logical block address corresponding to the read command Whether it belongs to one of the specific logical block addresses and determines whether the response data unit is stored in the buffer memory; 'When the logical block address corresponding to the read instruction belongs to the specific logical block Recording the towel of the H Wei Kee Newton, the returning unit, the 'touching the track' command (four), the block address is ^ should be an access address unit; and _ when the corresponding instruction is read When the block address corresponds to the address unit, the at least part of the response memory is transmitted to the host system. The method (4) 6 refers to the data distribution and transmission of the pair. The logical block address is not corresponding to the transfer of one part of the response data unit in the buffer memory to the host system by the second time. And the transfer logic ===_Logo ages (4) some specific data units, the buffer memory does not have the second data string to the host system, wherein the 35 34915 tw I 201207621.υ015 Two bits of the data string are all zero. 9. If the sixth method of the patent application scope, the method further includes: the data string assignment and the transmission are in the logical block position corresponding to the read instruction. When the address of the logical block address is located, according to the corresponding field, the block address is from the non-volatile memory module; 忒=二^#曰令-the second data string and will be It should be read that the second string is transmitted to the host system. MU data method 1 〇^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Whether or not the specific tag is included; and if the data string contains the specific tag, transmitting the -instruction data unit in the first data string to the hi-fi card and clearing the response data unit stored in the buffer memory . 11. The data string assignment and delivery method according to the first aspect of the patent application scope, further comprising: when the first data string does not contain the specific identifier, according to a logical block address corresponding to the write instruction The first data string is written into the non-volatile memory module. 12. A memory controller for use in a memory storage device having a non-volatile memory module and a smart card chip, the memory controller comprising: 36 201207621 r; sri^-ziJ10 -0015 34915twf.doc/I A host interface for coupling to a host system; - Memory interface, heart-to-turn-to-buffer memory; and ^ bottle supply, and, - memory management circuit, light Connect the buffer memory, the host interface and the memory interface, and the memory program circuit program: W Ding Wang V > Multiple logical block addresses, wherein a plurality of specific logical block addresses in the logical block addresses are used to store a specific target, receive-response data unit from the smart card wafer, and Storing the response data unit in the buffer memory; receiving a read command from the host system; determining whether the logical block address corresponding to the read instruction belongs to one of the specific logical block addresses and determining the Whether the response data unit exists in the buffer memory; the logical block address corresponding to the read instruction belongs to one of the specific logical block addresses and the response data unit is stored in the buffer memory Determining whether the logical block address corresponding to the read instruction corresponds to an access address unit; and when the logical block address corresponding to the read instruction corresponds to the access address unit, the transfer is stored in At least a portion of the response data unit in the buffer memory is provided to the host system. 13. The memory controller of claim 12, wherein when the logical block address corresponding to the read instruction does not correspond to the address 37 / 015 34915 twf. doc / I 201207621 unit, View M management more (four) pass the memory _ buffer in the response to the unit of the unit - part of the charm.丨4. The memory controller according to claim 12, wherein the logical block address corresponding to the read instruction belongs to the specific logical=block: address thereof - and the buffer memory When the body does not save (4) in response to the data soap 70, the memory management circuit is further configured to transmit a second data string to the host system, wherein each bit of the second data string is zero. " K is the memory controller described in claim 12, wherein the logical block material corresponding to the read instruction belongs to the memory controller of the specific = patent range, item 12, The memory management circuit is configured to execute at least the following program: further receiving, by the system, a write command and the first data string corresponding to the write command include a specific tag; and the :::::: : Contains: the specific mark, the buffer of the first data string is recorded as "two card wafers and the memory controller stored in the middle: the 16th item of the range of the benefit range is used. In the case of the special case, the memory management data is written to the non-volatile memory model by the logical block address corresponding to the write instruction of the first 38 201207621 010-0015 34915twf.doc/I data string. 18. A memory storage device comprising: a connector for coupling to a host system; a non-volatile memory module; a smart card chip, and a memory controller coupled To the connector, the non-volatile Recovering the body module and the smart card chip, and having a buffer memory, wherein the memory controller is configured to execute at least the following program:: configuring a plurality of logical block addresses for the non-volatile memory module, wherein the A plurality of specific logical block addresses among the logical block addresses are used to store a specific file; a response data unit is received from the smart card chip, and the response data unit is stored in the buffer memory; Receiving a read command in the host system; determining whether a logical block address corresponding to the read command belongs to one of the specific logical block addresses and determining whether the buffer memory exists in the buffer memory Responding to the data unit; and when the logical block address corresponding to the read instruction belongs to one of the specific logical block addresses and the response data unit is stored in the buffer memory, the transfer is stored in the buffer The response data unit in the memory is given to the host system.