201136245 六、發明說明： 【發明所屬之技術領域】 本揭示内容是有關於一種FlexRay電路’且特別是有 關於一種FlexRay收發電路。 【先前技術】 近年來，車用網路通訊協定FlexRay蓬勃發展，相關 系統技術已愈趨成熟。此標準協定主要是針對先進自動化 控制應用而訂的通訊系統，可提供高傳輸速率、備援傳輸 通道。目前，FlexRay已逐漸取代串列控制網路(Control Area Network，CAN)，大有成為線傳控制系統(X-by-wire)車輛應 用主要技術之趨勢。 具體而言，由於車用電控應用需要具備確定性、容錯 性及支援分布式控制系統的高速匯流排系統，因此非常適 合採用FlexRay技術。FlexRay可使汽車發展成百分之百 的電控系統，進而減低後備機械系統的支援需求。然而， 目前FlexRay產品體積較大且售價頗高。在封裝化的 FlexRay產品中，首推飛利浦（Philips)公司所生產之FlexRay bb片組型號T J A10 8 0，但是，此晶片組係採用雙載子接面 電晶體(Bipolar Junction Transistor，BJT)及複雜且不公開之 電路設計，來符合FlexRay對於通訊協定的規範。 201136245 因此，目前市面上尚無公開技術，探討如何設計一電 路架構，以符合FlexRay之通訊協定規格。 【發明内容】 因此，本揭示内容之一技術態樣是在提供一種FlexRay 發射器及其接收器，且其係以CMOS邏輯閘實現之，較市 面上之產品製造成本低廉且低功耗。 依據本揭示内容一實施方式，提出一種FlexRay發射 器，包含一第一發射器及一第二發射器。第一發射器包含 一 CMOS電流鏡及一傳輸閘。第一發射器之傳輸閘係用以 根據一第一狀態編碼，決定是否使第一發射器之CMOS電 流鏡產生一電流，以提供一正壓差給一匯流排之第一端， 且同時提供一負壓差給匯流排之第二端。第二發射器亦包 含一 CMOS電流鏡及一傳輸閘。第二發射器之傳輸閘係用 以根據一第二狀態編碼，決定是否使第二發射器之CMOS 電流鏡產生一電流，以提供一負壓差給匯流排之第一端， 且同時提供一正壓差給匯流排之第二端。 依據本揭示内容之另一實施方式，提出一種FlexRay 接收器，包括一遲滯比較器、一窗口比較器及一充放電幫 浦。遲滯比較器係用以比較一第一輸入電壓與一第二輸入 電壓，並根據比較結果產生一輸出訊號。窗口比較器係並 聯遲滯比較器，用以當第一輸入電壓與第二輸入電壓位於 一預設電壓區間時，輸出一閒置狀態訊號。充放電幫浦串 聯窗口比較器，係用以消除閒置狀態訊號之脈波雜訊。 藉此，本揭示内容之FlexRay發射器及其接收器，可 5 201136245 且實現低成本及低功耗 以符合車用網路通訊協定之規格， 之產品 【實施方式】 請參考第1圖，第1圖係201136245 VI. Description of the Invention: [Technical Field of the Invention] The present disclosure relates to a FlexRay circuit' and in particular to a FlexRay transceiver circuit. [Prior Art] In recent years, FlexRay, a vehicle network communication protocol, has flourished and related system technologies have become more mature. This standard protocol is primarily a communication system for advanced automation control applications that provides high transmission rates and redundant transmission channels. At present, FlexRay has gradually replaced the Control Area Network (CAN), which has become a major trend in the application of X-by-wire vehicle applications. Specifically, because automotive electronic control applications require deterministic, fault-tolerant, and high-speed bus systems that support distributed control systems, FlexRay technology is well suited. FlexRay enables cars to develop into 100% electronic control systems, which in turn reduces the need for backup mechanical systems. However, FlexRay products are currently large and expensive. Among the packaged FlexRay products, the FlexRay bb chipset model TJ A10 80 from Philips is the first to be used. However, this chipset uses a Bipolar Junction Transistor (BJT) and Complex and undisclosed circuit design to comply with FlexRay's specifications for communication protocols. 201136245 Therefore, there is currently no open technology on the market to explore how to design a circuit architecture to comply with FlexRay's protocol specifications. SUMMARY OF THE INVENTION Accordingly, it is a technical aspect of the present disclosure to provide a FlexRay transmitter and receiver thereof, which is implemented by a CMOS logic gate, which is relatively inexpensive to manufacture and low in power consumption. In accordance with an embodiment of the present disclosure, a FlexRay transmitter is provided that includes a first transmitter and a second transmitter. The first transmitter includes a CMOS current mirror and a transfer gate. The transmission gate of the first transmitter is configured to determine whether to cause a current of the CMOS current mirror of the first transmitter to generate a positive voltage difference to the first end of the bus bar according to a first state encoding, and simultaneously provide A negative pressure difference is applied to the second end of the bus bar. The second transmitter also includes a CMOS current mirror and a transmission gate. The transmission gate of the second transmitter is configured to determine whether to generate a current of the CMOS current mirror of the second transmitter according to a second state code to provide a negative voltage difference to the first end of the bus bar, and simultaneously provide a The positive pressure difference is given to the second end of the bus bar. In accordance with another embodiment of the present disclosure, a FlexRay receiver is provided that includes a hysteresis comparator, a window comparator, and a charge and discharge pump. The hysteresis comparator is configured to compare a first input voltage with a second input voltage and generate an output signal according to the comparison result. The window comparator is a parallel hysteresis comparator for outputting an idle state signal when the first input voltage and the second input voltage are within a predetermined voltage interval. The charge and discharge pump is connected to the window comparator to eliminate the pulse noise of the idle state signal. Therefore, the FlexRay transmitter and receiver thereof of the present disclosure can realize the low cost and low power consumption to meet the specifications of the vehicle network communication protocol, and the product [implementation method] Please refer to FIG. 1 , 1 graphic system
FlexRay發射器的結構示意圖。第不* —實施方式之 ⑽主要包含一第一發射器u〇U二⑽吖發射器 發射器110包含—CMOS電产锫 —X射器130。第一 -發射器m之傳輸閑112電;=^ 決定是否使第一發射器11〇之c 狀態編碼， 流’以提供一正壓差給 s電流鏡111產生-電 眠洲排120之篦一锉10 ί 時提供一負壓差給匯流排12〇 鳊121，且同 130亦包含—CMOS電流鏡 一:^22。第二發射器 射器130之傳輸閘132係用 第一發 是否使第二發射器13〇2Cm 第-狀L、編碼，決定 以提供-負壓差給匯流排12〇 j 131產生—電流’ 一正壓_祕my n22—端12卜且同時提供 具體而言，在FlexRay @ 訊號為兩組電位邏輯相反的 S疋中，要求輪入資料 一狀態編碼與第二狀態編碼:==，狀態下第 = 狀態編碼與第 邏輯電：與一低邏輯電位時’表示此 ：1 可以依據輸人訊號，產生兩組 y1時器100 而當第-狀態編碼與第二狀態::=:=。 位時，表不此輸入訊號並不可靠或FlexRay發射器 201136245 於閒置狀態，FlexRay發射器100不應依據此一對輸入訊 號，產生有意義的輸出電位訊號。這是因為在車用電子中， 電路所承受的電磁干擾、漏電干擾、接地位準飄移等負面 因素’遠較一般靜置於固定環境之電路為高。 因此’細究本實施方式之FlexRay發射器1 〇〇，可以清 楚知悉如下操作規則： 當傳輸閘112與傳輸閘132收到邏輯相反的第一狀態 編碼與第一狀態編碼時，若第一狀態編碼代表驅動CM〇s 電流鏡111映射一電流到匯流排12〇，則第二狀態編碼代表 不驅動CMOS電流鏡131映射一電流到匯流排120。此時， 第一發射器110便提供一正壓差給匯流排12〇之第一端 121 ’且同時提供一負壓差給匯流排120之第二端122。換 句話說’匯流排12〇的輸出電位訊號為電位邏輯相反的第 一端121高電位邏輯與第二端122低電位邏輯，記作（1，〇)。 而當傳輸閘112與傳輸閘132所收到之輸入訊號為第 一狀態編碼代表不驅動CMOS電流鏡111映射一電流到匯 流排120，而第二狀態編碼代表驅動CMOS電流鏡131映 射一電流到匯流排12〇時；第二發射器130便提供一正壓 差給匯流排120之第二端122，且同時提供一負壓差給匯 流排120之第一端12卜記作（0, 1)。 至於其他不工作狀態或受干擾狀態，皆會使第一發射 器110之電流鏡111與第二發射器130之電流鏡131同時 映射電流或不映射電流到匯流排120，則匯流排120之第 一端121與第二端122自然不會產生一組邏輯電位相反的 輪出電位訊號。 201136245 綜上所述，本實施方式之FlexRay發射器100即可符 合車用網路通訊協定FlexRay之規格要求。 請繼續參考第2圖，第2圖是第1圖之匯流排120的 電路圖。第2圖中，匯流排120更包括一第一電阻123、 一偏壓電源124及一第二電阻125。此處係提供一可行之 匯流排120的設計方式，以使前述CMOS電流鏡111及 CMOS電流鏡131所映射之電流可以轉換為正壓差或負壓 差於匯流排120之第一端121與第二端122上；而非用以 限制本實施方式之FlexRay發射器100在匯流排120設計 上的其他可行態樣。 具體而言，當第一發射器110驅動CMOS電流鏡111 產生映射電流時，一映射電流由節點a流經第一電阻123 到達偏壓電源124,使第一端121之電位高於偏壓電源124 一壓差，此即所謂正壓差。與此同時，CMOS電流鏡111 亦產生一映射電流，從偏壓電源124經第二電阻125流向 節點c，而使第二端122之電位低於偏壓電源124 —壓差， 此即所謂負壓差。有趣的是，透過電路上的匹配設計，上 述兩組映射電流可實為同一股電流。相同地，透過電路上 的匹配設計，正壓差之絕對值可以等於負壓差之絕對值。 值得注意的是，此時第二發射器130不可同時驅動 CMOS電流鏡131，使節點b與節點d有電流通過；否則 第一端121與第二端122便無法產生穩定的正壓差與負壓 差，以及所謂第一狀態編碼與第二狀態編碼需互為電位邏 輯相反的訊號。 另一方面，第二發射器130的作動方式，與前述第一 201136245 發射器110相同；其差異僅在於當第二發射器130作動時， 映射電流由節點d流入第二端122，且由節點b流出第— 端121 ’而使正負壓差易位。 請繼續參考第3圖，第3圖是第1圖之傳輸閘的電路 * 圖。具體而言，為了利用CMOS電路實現FlexRay發射器Schematic diagram of the FlexRay transmitter. The first embodiment (10) mainly includes a first transmitter u〇U two (10) 吖 transmitter The transmitter 110 includes a CMOS electric 锫-X il emitter 130. The transmission of the first-transmitter m is idle; =^ determines whether to cause the first transmitter 11 to encode the c state, and the stream 'to provide a positive voltage difference to the s current mirror 111. A negative voltage difference is provided to the busbar 12〇鳊121 at 10 ί, and the same 130 also includes a CMOS current mirror: ^22. The transmission gate 132 of the second transmitter 130 uses the first transmitter to cause the second transmitter 13 〇 2Cm to be L-coded, and is determined to provide a negative voltage difference to the busbar 12 〇j 131 to generate a current 'current' A positive pressure _ secret my n22 - end 12 b and at the same time provide specific, in the FlexRay @ signal for the two sets of potential logic opposite S ,, requires the wheeled data a state code and the second state code: ==, state The next = state code and the first logic: when a low logic potential 'represents this: 1 can generate two sets of y1 timer 100 according to the input signal and when the first state code and the second state::=:=. In the case of a bit, the input signal is not reliable or the FlexRay transmitter 201136245 is idle. The FlexRay transmitter 100 should not generate a meaningful output potential signal based on the pair of input signals. This is because in the vehicle electronics, the negative factors such as electromagnetic interference, leakage interference, and grounding level shifting of the circuit are much higher than those of the circuit that is normally placed in a fixed environment. Therefore, the following operation rules can be clearly understood when the FlexRay transmitter 1 of the present embodiment is used: When the transmission gate 112 and the transmission gate 132 receive the first state code and the first state code which are opposite in logic, if the first state code The representative CM 〇 current mirror 111 maps a current to the bus bar 12 〇, and the second state code represents that the CMOS current mirror 131 is not driven to map a current to the bus bar 120 . At this time, the first transmitter 110 provides a positive pressure difference to the first end 121' of the bus bar 12's while providing a negative voltage differential to the second end 122 of the busbar 120. In other words, the output potential signal of the bus bar 12 is the high potential logic of the first end 121 of the potential logic opposite to the low potential logic of the second terminal 122, which is denoted as (1, 〇). When the input signal received by the transmission gate 112 and the transmission gate 132 is the first state code, the CMOS current mirror 111 is not driven to map a current to the bus bar 120, and the second state code represents the driving CMOS current mirror 131 to map a current to When the bus bar is 12 ;, the second transmitter 130 provides a positive pressure difference to the second end 122 of the bus bar 120, and simultaneously provides a negative voltage difference to the first end 12 of the bus bar 120 (0, 1) ). As for other non-operating states or disturbed states, the current mirror 111 of the first transmitter 110 and the current mirror 131 of the second transmitter 130 simultaneously map current or do not map current to the bus bar 120, and the bus bar 120 is One end 121 and the second end 122 naturally do not generate a set of turn-off potential signals having opposite logic potentials. In summary, the FlexRay transmitter 100 of the present embodiment can meet the specifications of the automotive network protocol FlexRay. Please refer to FIG. 2 again, and FIG. 2 is a circuit diagram of the bus bar 120 of FIG. 1. In FIG. 2, the bus bar 120 further includes a first resistor 123, a bias power source 124, and a second resistor 125. Here, a feasible bus bar 120 is provided in such a manner that the current mapped by the CMOS current mirror 111 and the CMOS current mirror 131 can be converted into a positive voltage difference or a negative voltage difference at the first end 121 of the bus bar 120. The second end 122 is on; rather than limiting other possible aspects of the FlexRay transmitter 100 of the present embodiment in the design of the busbar 120. Specifically, when the first emitter 110 drives the CMOS current mirror 111 to generate a mapping current, a mapping current flows from the node a through the first resistor 123 to the bias power source 124, so that the potential of the first terminal 121 is higher than the bias power source. 124 A pressure difference, this is the so-called positive pressure difference. At the same time, the CMOS current mirror 111 also generates a mapping current from the bias power source 124 to the node c via the second resistor 125, so that the potential of the second terminal 122 is lower than the bias voltage of the bias power source 124. Pressure difference. Interestingly, the above two sets of mapped currents can be the same current through the matching design on the circuit. Similarly, the absolute value of the positive pressure difference can be equal to the absolute value of the negative pressure difference through the matching design on the circuit. It should be noted that at this time, the second transmitter 130 cannot simultaneously drive the CMOS current mirror 131 to pass the current between the node b and the node d; otherwise, the first end 121 and the second end 122 cannot generate a stable positive pressure difference and negative The voltage difference, and the so-called first state code and the second state code, need to be mutually opposite to each other. On the other hand, the second transmitter 130 operates in the same manner as the first 201136245 transmitter 110; the difference is only that when the second transmitter 130 is actuated, the mapping current flows from the node d to the second end 122, and the node b Flow out of the first end 121' to make the positive and negative pressure difference translocation. Please continue to refer to Figure 3, which is a circuit diagram of the transmission gate of Figure 1. Specifically, in order to implement a FlexRay transmitter using a CMOS circuit
. 100，使其具有平衡的電路特性，除了電流鏡可採CMOS 電流鏡以外，傳輸閘112及傳輸閘132亦可採用CMOS傳 輸閘140之電路結構。換句話說，CMOS傳輸閘140可由 φ 一個N型場效電晶體141與一個P型場效電晶體142所組 成。P型場效電晶體142的源極與N型場效電晶體141之 汲極共點，P型場效電晶體142的汲極與N型場效電晶體 141之源極共點。 接下來，請參考第4圖，第4圖是第1圖之CMOS電 流鏡的電路圖。第一發射器110之CMOS電流鏡111及第 二發射器130之CMOS電流鏡131 ’皆可採用第4圖所繪 示之結構設計。具體而言，CMOS電流鏡150是由一個 • PMOS電流源151及一個NMOS電流槽152所組成，且受 控於前述CMOS傳輸閘140。由於第一發射器110與第二 發射器130皆為CMOS電路設計方式，本實施方式之 FlexRay發射器100較諸飛利浦所用之BJT電路省電且低 製作成本。 最後，請參考第5圖，第5圖是第1圖之詳細電路圖。 第五圖中，第一發射器110之PMOS電流源包括一第一 P 型場效電晶體Ml及一第二P型場效電晶體M5’第一 P型 場效電晶體Ml之源極電性連接一電壓源Vdd，其閘極與 201136245 其汲極共點，且其汲極電性連接傳輸閘112。傳輸閘in 則由Ν型場效電晶體M2與Ρ型場效電晶體M3所組成。 第二Ρ型場效電晶體Μ5之源極電性連接電壓源Vdd，其 閘極與第一 P型場效電晶體Ml之閘極共點，且其汲極電 . 性連接第一端121。 . 第一發射器11〇之NMOS電流槽包括一第一 N型場效 電晶體M4及一第二N型場效電晶體M6。第一 N型場效 電晶體M4之源極接地，其汲極與其閘極共點，且其汲極 φ 電性連接傳輸閘112。第二N型場效電晶體M6之閘極與 第一 N型場效電晶體M4之閘極共點，其源極接地，其沒 極電性連接第二端122。 同理’第二發射器13〇之PMOS電流源包括一第一 P 型場效電晶體ml及一第二ρ型場效電晶體m5(注意其位 置）’第一 P型場效電晶體ml之源極電性連接電壓源Vdd， 其閘極與其汲極共點，且其汲極電性連接傳輸閘132。第 二P型場效電晶體m5之源極電性連接電壓源Vdd，其閘 • 極與第一 P型場效電晶體ml之閘極共點，且其汲極電性 連接第一端122，而非第一端121。 第二發射器130之NMOS電流槽包括一第一 N型場效 電晶體m4及一第二ν型場效電晶體m6(注意其位置）。第 一 N型場效電晶體m4之源極接地，其汲極與其閘極共點， •且其汲極電性連接傳輸閘132。第二N型場效電晶體m6 之閑極與第一 N型場效電晶體m4之閘極共點，其源極接 地，其汲極電性連接第一端121，而非第二端122。 請參考第6圖，第6圖是本揭示内容另一實施方式之 201136245100, to make it have balanced circuit characteristics, in addition to the current mirror can be used CMOS current mirror, the transmission gate 112 and the transmission gate 132 can also adopt the circuit structure of the CMOS transmission gate 140. In other words, the CMOS transfer gate 140 can be comprised of φ an N-type field effect transistor 141 and a P-type field effect transistor 142. The source of the P-type field effect transistor 142 is co-located with the drain of the N-type field effect transistor 141, and the drain of the P-type field effect transistor 142 is co-located with the source of the N-type field effect transistor 141. Next, please refer to Fig. 4, which is a circuit diagram of the CMOS current mirror of Fig. 1. The CMOS current mirror 111 of the first transmitter 110 and the CMOS current mirror 131' of the second transmitter 130 can be designed using the structure shown in Fig. 4. Specifically, the CMOS current mirror 150 is composed of a PMOS current source 151 and an NMOS current sink 152, and is controlled by the aforementioned CMOS transmission gate 140. Since both the first transmitter 110 and the second transmitter 130 are in a CMOS circuit design, the FlexRay transmitter 100 of the present embodiment saves power and has a lower manufacturing cost than the BJT circuit used by Philips. Finally, please refer to Figure 5, which is a detailed circuit diagram of Figure 1. In the fifth figure, the PMOS current source of the first transmitter 110 includes a first P-type field effect transistor M1 and a second P-type field effect transistor M5'. The source of the first P-type field effect transistor M1 A voltage source Vdd is connected, and its gate is co-located with the 201136245, and its drain is electrically connected to the transmission gate 112. The transmission gate in is composed of a 场-type field effect transistor M2 and a Ρ-type field effect transistor M3. The source of the second-type field effect transistor Μ5 is electrically connected to the voltage source Vdd, and the gate thereof is co-located with the gate of the first P-type field effect transistor M1, and the gate is electrically connected to the first end 121. . The NMOS current slot of the first emitter 11 includes a first N-type field effect transistor M4 and a second N-type field effect transistor M6. The source of the first N-type field effect transistor M4 is grounded, its drain is co-located with its gate, and its drain φ is electrically connected to the transfer gate 112. The gate of the second N-type field effect transistor M6 is co-located with the gate of the first N-type field effect transistor M4, the source of which is grounded, and which is not electrically connected to the second terminal 122. Similarly, the PMOS current source of the second emitter 13 includes a first P-type field effect transistor ml and a second p-type field effect transistor m5 (note its position) 'the first P-type field effect transistor ml The source is electrically connected to the voltage source Vdd, the gate is co-located with the drain thereof, and the drain is electrically connected to the transfer gate 132. The source of the second P-type field effect transistor m5 is electrically connected to the voltage source Vdd, and the gate electrode thereof is co-located with the gate of the first P-type field effect transistor ml, and the drain is electrically connected to the first end 122. Instead of the first end 121. The NMOS current slot of the second emitter 130 includes a first N-type field effect transistor m4 and a second ν-type field effect transistor m6 (note its position). The source of the first N-type field effect transistor m4 is grounded, its drain is co-located with its gate, and its drain is electrically connected to the transfer gate 132. The idle pole of the second N-type field effect transistor m6 is co-located with the gate of the first N-type field effect transistor m4, the source thereof is grounded, and the drain is electrically connected to the first end 121 instead of the second end 122. . Please refer to FIG. 6 , which is another embodiment of the present disclosure.
FlexRay接收器200的結構示意圖。第6圖中，FlexRay接 收器200包括一遲滯比較器210、一窗口比較器220及一 充放電幫浦230。遲滯比較器210係用以比較一第一輸入 電壓201與一第二輸入電壓202，並根據比較結果產生一 輸出訊號。窗口比較器220係並聯遲滯比較器210，用以 當第一輸入電壓210與第二輸入電壓220位於一預設電壓 區間221時，輸出一閒置狀態訊號222。充放電幫浦230 串聯窗口比較器220，係用以消除閒置狀態訊號222之脈 波雜訊。 具體而言，前述FlexRay發射器100之第一端121與 第二端122的電壓值會被傳輸到FlexRay接收器200,以作 為第一輸入電壓201與第二輸入電壓202。當第一輸入電 壓201與第二輸入電壓202之電位邏輯相反，也就是其產 生是根據有意義的第一狀態編碼與第二狀態編碼時，遲滞 比較器210會根據第一輸入電壓201與第二輸入電壓202 之比較結果產生輸出訊號。更正確的說，遲滯比較器210 是在確保第一輸入電壓201與第二輸入電壓202兩者之間 存在一定的差值；也就是說，當第一輸入電壓201與第二 輸入電壓202邏輯轉態時(一個由高電位變低電位，另一個 由低電位變高電位），遲滯比較器210可以確認兩輸入比較 訊號電壓其中之一，必須再大於或小於另一輸入電壓一個 所設計的電壓值，這樣作的主要目的是消除雜訊的影響， 以取得正確的輸出訊號。 舉例而言，如果第一狀態編碼與第二狀態編碼為一高 一低（1，0)，則遲滯比較器210之輸出可假設為邏輯高電位 m 11 201136245 (l);反之，第一狀態編碼與第二狀態編碼為一低一高（〇」）’ 則遲滯比較器210之輸出為邏輯低電位(〇);重點是，當第 一狀態編碼與第二狀態編碼同為高電位（1山或低電位 (〇,〇)i第一端121與第二端122之電位不可預知，而遲滯 -比較器210便因第一輸入電壓201與第二輸入電壓202並 未能存在一定的差值（預期高電位與低電位之差值），而不 理會此一雜訊擾動或閒置狀態。所以，遲滯比較器210之 輸出汛號可以正確反應第一狀態編碼與第二狀態編碼所代 鲁 表的訊號意義。 窗口比較器220的功能是當輸入電壓，亦即第一輸入 電壓201與第二輸入電壓2〇2之差值，落在某一設計的電 壓區間時，能夠偵測並指示出來。承上所述，此一區間即 代表第一狀態編碼與第二狀態編碼並未呈現邏輯電位相反 的狀態，是閒置狀態(Idle);窗口比較器22〇因而產生間置 狀態訊號222。由此觀之，遲滯比較器210所產生的輸出 訊號即可作為車用網路通訊協定FlexRay所要求之資料訊 | 號R-data，而窗口比較器22〇所產生之閒置狀態訊號222 即符合車用網路通訊協定FlexRay所要求之間置指標 R-idle。 然而，由於輸入訊號的轉態，必定會經過所設計的電 壓區間，亦即預設電壓區間22卜進而造成窗口比較器22〇 的輸出值，亦即閒置狀態訊號222，出現短脈波雜訊。所 以，本實施方式將充放電幫浦230的兩輸入接在一起，配 合所設計的負載電容值，以濾除短脈波雜訊。 最後，請參考第7圖，第7圖是第ό圖之詳細電路圖。 12 201136245 第7圖中，本實施方式之FlexRay接收器200更包括一取 樣電路240 ;取樣電路240係串聯於遲滯比較器210，以取 樣輸出訊號，產生數位形式的資料訊號。更進一步的說， 取樣電路240可以包括一延遲電路241及一 D型正反器 ' 242 ;當FlexRay接收器200處於非低功耗模式，亦即 . FlexRay發射器1〇〇傳過來的資料不是代表閒置狀態時，取 樣電路240可以讓資料訊號符合最初始的輸入訊號，亦即 第一狀態編碼與第二狀態編碼。因此，延遲電路241可以 % 使資料訊號在時間上匹配閒置狀態訊號222 ;而D型正反 器242可以使資料訊號符合最初始的輪入訊號。 另一方面，充放電幫浦23〇可再串聯一反向器250， 則當FlexRay接收器200處於非低功耗模式時，反向器250 可以讓差動訊號（第一輸入電壓201與第二輸入電壓202之 差值）的大小符合FlexRay協定的要求。具體而言，FlexRay 協定要求邏輯1表示訊號很小’匯流排120狀態應為Idle 或Idle_LP。邏輯〇表示訊號足夠大，指示匯流排狀態應 _ 為Data。但閒置狀態訊號222之邏輯關係正好相反，故可 經反向器250調整之，使閒置狀態訊號在相位邏輯上匹配 資料訊號。 接下來，本揭示内容以雙向差動電壓傳輸架構進行點 野點傳輸，來測試上述實施方式所揭露之FlexRay發射器 100與FlexRay接收器200，以驗證其效能如下。 請參照第8圖，第8圖是傳輸訊號之波形圖。第8圖 中，實線是前述FlexRay發射器1〇〇與FlexRay接收器2〇〇 間訊遗之波形眼圖’而虛線是FlexRay通訊協定最低需求 13 201136245 之波形眼圖。 具體而言，從一個資料序列的波形眼圖可觀察一個訊 號的各種品質。一個接收器的訊號有許多特性，像是振幅 雜訊、插入符號干擾或者抖動，這都會影響從信號中萃取 * 正確資訊的機率。一個訊號的波形眼圖可用以判讀這些訊 . 號特性的資訊。在雙向差動電壓傳輸架構中，假設FlexRay 發射器100要傳送訊號給FlexRay接收器200,則第8圖中 實線是代表在FlexRay發射器100上第一端121和第二端 • 122的電壓差，而虛線則是FlexRay所要求最小規格的波 形眼圖。實線部分所形成的波形眼圖很明顯的包含虛線部 分，因此符合FlexRay規格的要求。相同的現象也可以在 FlexRay接收器200的第一輸入電壓201與第二輸入電壓 202間電壓差之波形眼圖中觀察到。由第8圖可知悉，本 實施方式之訊號符合FlexRay通訊協定所要求之訊號需求。 請一併參照第9A圖與第9B圖；第9A圖是nexRay 接收器200接收資料正確性指標之波形圖，第9b圖是 FlexRay接收器200接收資料之波形圖。由第9a圖與第9B 圖亦可知悉’本實施方式之接收器2〇〇在輸出轉移函數 時’亦符合FlexRay通訊協定所要求之訊號需求。具體比 較數據如下表所示： ~ 201136245Schematic diagram of the structure of the FlexRay receiver 200. In Fig. 6, the FlexRay receiver 200 includes a hysteresis comparator 210, a window comparator 220, and a charge and discharge pump 230. The hysteresis comparator 210 is configured to compare a first input voltage 201 with a second input voltage 202 and generate an output signal according to the comparison result. The window comparator 220 is a parallel hysteresis comparator 210 for outputting an idle state signal 222 when the first input voltage 210 and the second input voltage 220 are in a predetermined voltage interval 221 . The charge and discharge pump 230 series window comparator 220 is used to eliminate the pulse noise of the idle state signal 222. Specifically, the voltage values of the first end 121 and the second end 122 of the aforementioned FlexRay transmitter 100 are transmitted to the FlexRay receiver 200 as the first input voltage 201 and the second input voltage 202. When the first input voltage 201 is logically opposite to the potential of the second input voltage 202, that is, when the generation is based on the meaningful first state code and the second state code, the hysteresis comparator 210 according to the first input voltage 201 The comparison of the two input voltages 202 produces an output signal. More correctly, the hysteresis comparator 210 is to ensure a certain difference between the first input voltage 201 and the second input voltage 202; that is, when the first input voltage 201 and the second input voltage 202 are logic In the transition state (one from low to low and the other from low to high), the hysteresis comparator 210 can confirm that one of the two input comparison signal voltages must be greater than or less than another input voltage. The main purpose of the voltage value is to eliminate the effects of noise to obtain the correct output signal. For example, if the first state code and the second state code are one high and one low (1, 0), the output of the hysteresis comparator 210 can be assumed to be a logic high potential m 11 201136245 (1); otherwise, the first state The code and the second state code are one low-high (〇")', and the output of the hysteresis comparator 210 is a logic low (〇); the emphasis is that when the first state code and the second state code are both high (1) The potential of the first end 121 and the second end 122 of the mountain or low potential (不可, 〇) i is unpredictable, and the hysteresis- comparator 210 does not have a certain difference due to the first input voltage 201 and the second input voltage 202. The value (the difference between the expected high potential and the low potential) ignores the noise disturbance or the idle state. Therefore, the output nickname of the hysteresis comparator 210 can correctly reflect the first state code and the second state code. The function of the window comparator 220 is that when the input voltage, that is, the difference between the first input voltage 201 and the second input voltage 2〇2, falls within a certain design voltage range, it can detect and indicate Come out. As stated above, this section is the next generation. The first state code and the second state code do not exhibit a state opposite to the logic potential, which is an idle state (Idle); the window comparator 22 thus generates an intervening state signal 222. From this, the hysteresis comparator 210 generates The output signal can be used as the R-data required by the automotive network protocol FlexRay, and the idle state signal 222 generated by the window comparator 22 is in accordance with the requirements of the automotive network protocol FlexRay. The index R-idle. However, due to the transition of the input signal, the designed voltage range, that is, the preset voltage interval 22, is caused to cause the output value of the window comparator 22, that is, the idle state signal 222 appears. Short pulse noise. Therefore, in this embodiment, the two inputs of the charge and discharge pump 230 are connected together, and the designed load capacitance value is used to filter out short pulse noise. Finally, please refer to Fig. 7, 7 is a detailed circuit diagram of the second diagram. 12 201136245 In Fig. 7, the FlexRay receiver 200 of the present embodiment further includes a sampling circuit 240; the sampling circuit 240 is connected in series to the hysteresis comparator 210 to take The output signal generates a digital signal in the form of a digit. Further, the sampling circuit 240 can include a delay circuit 241 and a D-type flip-flop '242; when the FlexRay receiver 200 is in a non-low power mode, ie, FlexRay When the data transmitted by the transmitter 1 is not representative of the idle state, the sampling circuit 240 can make the data signal conform to the initial input signal, that is, the first state code and the second state code. Therefore, the delay circuit 241 can make the data The signal matches the idle status signal 222 in time; the D-type flip-flop 242 can cause the data signal to conform to the initial round-robin signal. On the other hand, the charge and discharge pump 23〇 can be connected in series with an inverter 250. When the FlexRay receiver 200 is in the non-low power mode, the inverter 250 can make the differential signal (the first input voltage 201 and the first The magnitude of the difference between the two input voltages 202 is in accordance with the requirements of the FlexRay protocol. Specifically, the FlexRay protocol requires a logic 1 to indicate that the signal is small. The status of the bus 120 should be Idle or Idle_LP. The logic 〇 indicates that the signal is large enough to indicate that the bus status should be _. However, the logical relationship of the idle state signal 222 is reversed, so that it can be adjusted by the inverter 250 so that the idle state signal logically matches the data signal in phase. Next, the present disclosure performs point-to-point transmission with a bidirectional differential voltage transmission architecture to test the FlexRay transmitter 100 and the FlexRay receiver 200 disclosed in the above embodiments to verify their performance as follows. Please refer to Figure 8. Figure 8 is a waveform diagram of the transmission signal. In Figure 8, the solid line is the waveform eye diagram of the aforementioned FlexRay transmitter 1〇〇 and FlexRay receiver 2, and the dashed line is the waveform eye diagram of the FlexRay protocol minimum requirement 13 201136245. Specifically, the various qualities of a signal can be observed from the waveform eye diagram of a data sequence. A receiver's signal has many characteristics, such as amplitude noise, interpolated interference, or jitter, which can affect the probability of extracting *correct information from the signal. A waveform eye diagram of a signal can be used to interpret information about these characteristics. In the bidirectional differential voltage transmission architecture, assuming that the FlexRay transmitter 100 is to transmit a signal to the FlexRay receiver 200, the solid line in FIG. 8 represents the voltage at the first end 121 and the second end 122 of the FlexRay transmitter 100. Poor, and the dotted line is the waveform eye diagram of the minimum size required by FlexRay. The undulating eye diagram formed by the solid line portion clearly includes the dotted line and is therefore compliant with the FlexRay specification. The same phenomenon can also be observed in the waveform eye diagram of the voltage difference between the first input voltage 201 and the second input voltage 202 of the FlexRay receiver 200. As can be seen from Figure 8, the signal of this embodiment conforms to the signal requirements required by the FlexRay protocol. Please refer to FIG. 9A and FIG. 9B together; FIG. 9A is a waveform diagram of the nexRay receiver 200 receiving the data correctness index, and FIG. 9b is a waveform diagram of the FlexRay receiver 200 receiving the data. It can also be seen from Figures 9a and 9B that the receiver 2 of the present embodiment also meets the signal requirements required by the FlexRay protocol when outputting the transfer function. The specific comparison data is shown in the following table: ~ 201136245
測試項目名稱 實測數據 規格最小值 規格最大值 輸出端壓差主 動上升 295mV 150mV 425mV 輸出端壓差主 動下降 -295mV -425mV 150mV 第一狀態編碟 225mV 150mV 300mV 第一狀態編碼 -225mV -300mV -150mV 負緣輸出延遲 6.47nS lOOnS 正緣輸出延遲 6.63nS lOOnS 下降電壓差 6.20nS 3.75nS 18.75nS 上升電壓差 6.21nS 3.75nS 18.75nS 負緣接收延遲 43.53nS lOOnS 正緣接收延遲 43.53nS lOOnS 請一併參照第10圖與第11圖。第10圖是本揭示内容 於測試中，根據FlexRay通訊協定，定義一發射器之訊號 時序的波形圖。第11圖是模擬前述FlexRay發射器100延 遲時間規格的波形圖。由第10圖與第11圖可知悉，前述 FlexRay發射器1 〇〇所產生之訊號波形亦符合FiexRay通訊 協定之規定。相關數據之比較亦一併列於上表。 請一併參照第12圖與第13圖。第12圖是本揭示内容 於測試中，根據FlexRay通訊協定，定義一接收器之訊號 時序的波形圖。第13圖是模擬前述FlexRay接收器200延 遲時間規格的波形圖。由第12圖與第13圖可知悉，前述 m 15 201136245Test item name measured data specification minimum specification maximum output terminal differential pressure active rise 295mV 150mV 425mV output terminal differential pressure active drop -295mV -425mV 150mV first state editing disc 225mV 150mV 300mV first state code -225mV -300mV -150mV negative Edge output delay 6.47nS lOOnS Positive edge output delay 6.63nS lOOnS Falling voltage difference 6.20nS 3.75nS 18.75nS Rising voltage difference 6.21nS 3.75nS 18.75nS Negative edge receiving delay 43.53nS lOOnS Positive edge receiving delay 43.53nS lOOnS Please refer to the same Figure 10 and Figure 11. Figure 10 is a diagram of the present invention. In the test, a waveform diagram of the signal timing of a transmitter is defined according to the FlexRay protocol. Figure 11 is a waveform diagram simulating the aforementioned FlexRay transmitter 100 delay time specification. It can be seen from Fig. 10 and Fig. 11 that the signal waveform generated by the aforementioned FlexRay transmitter 1 is also in compliance with the FiexRay communication protocol. A comparison of relevant data is also included in the above table. Please refer to Figure 12 and Figure 13 together. Figure 12 is a cross-sectional view of the signal timing of a receiver in accordance with the FlexRay protocol. Figure 13 is a waveform diagram simulating the aforementioned FlexRay receiver 200 delay time specification. It can be seen from Figures 12 and 13 that the aforementioned m 15 201136245
FleXRay接收器2〇〇所產生之訊號波形亦符合FlexRay通訊 協疋之規定°相關數據之比較亦一併列於上表。 清參照第14圖，第14圖是模擬工作狀態下，上述實 施方式之FlexRay發射器1〇〇與FlexRay接收器2〇〇的波 ' =圖。從第14圖中可看出，當FlexRay發射器100處於正 * 常收發狀態時’假設傳送資料(TxD)每100ns變化一次， 則當匯流排傳輸指標(BusGuardian_Enable, BGE)為邏輯1 且發射資料正確性指標（ΤχΕΝ)為邏輯〇時，接收資料正確 φ 性指標(RxEN)為邏輯0，若匯流排上的電壓差（ΤΡ1)為正， 接收資料(RxD)為邏輯卜若匯流排上的電壓差（τρ1)為負， 接收資料(IUD)為邏輯〇;當匯流排傳輸指標(BGE)為邏輯 〇或輸出資料正確性指標(TxEN)為邏輯i時，匯流排上的 電壓差（TP1)為〇，接收資料正確性指標(RxEN)和接收資料 (RxD)同時為邏輯i。因此FlexRay發射器1〇〇與 接收器200動作正確，符合FlexRay通訊協定之要求。 雖然本發明已以諸實施方式揭露如上，然其並非用以 # 限^本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 ' ^讓本揭示内容之上述和其他目的、特徵、優點與實 • 施例能更明顯易懂，所附圖式之說明如下： 第1圖是本揭示内容一實施方式之FlexRay發射器的 結構不意圖。 201136245 第2圖是第1圖之匯流排120的電路圖。 第3圖是第1圖之傳輸閘^2/132的電路圖。 第4圖是第1圖之CMOS電流鏡111/131的電路圖。 第5圖是第1圖之詳細電路圖。 第6圖是本揭示内容另一實施方式之FlexRay接枚器 ' 的結構示意圖。 第7圖是第6圖之詳細電路圖。 鲁 第8圖是傳輸訊號之波形圖。 第9A圖是FlexRay接收器200接收資料正確性指栂少 波形圖。 ' 第9B圖是FlexRay接收器200接收資料之波形圖。 第10圖是本揭示内容於測試中，根據FlexRay通訊協 定，定義一發射器之訊號時序的波形圖。 第11圖是模擬FlexRay發射器100延遲時間規格的波 形圖。 φ 第12圖是本揭示内容於測試中，根據FlexRay通訊協 定，定義一接收器之訊號時序的波形圖。 第13圖是模擬FlexRay接收器2〇〇延遲時間規格的波 形圖。 第14圖是模擬工作狀態下，FiexRay發射器1〇〇與 . FlexRay接收器200的波形圖。 【主要元件符號說明】 100 : FlexRay發射器 110 :第一發射器 m 17 201136245 111、131、150 : CMOS 電流 112 鏡 121 :第一端 123 :第一電阻 - 125 :第二電阻 ， 140: CMOS傳輸閘 142 : P型場效電晶體 152 : NM0S電流槽 φ 201 :第一輸入電壓 210 :遲滯比較器 221 :預設電壓區間 230 :充放電幫浦 241 :延遲電路 250 :反向器 132 :傳輸閘 12 0 .匯流排 122 :第二端 124 :偏壓電源 130 :第二發射器 141 : N型場效電晶體 151 : PMOS電流源 200 : FlexRay 接收器 202 :第二輸入電壓 220 :窗口比較器 222 :閒置狀態訊號 240 :取樣電路 242 :正反器The signal waveform generated by the FleXRay receiver 2 is also in accordance with the FlexRay communication protocol. The comparison of the relevant data is also listed in the above table. Referring to Fig. 14, Fig. 14 is a diagram showing the wave '= of the FlexRay transmitter 1〇〇 and the FlexRay receiver 2〇〇 of the above embodiment in a simulated operation state. As can be seen from Figure 14, when the FlexRay transmitter 100 is in the normal transmission and reception state, 'assuming the transmission data (TxD) changes every 100 ns, then when the bus transmission indicator (BusGuardian_Enable, BGE) is logic 1 and the data is transmitted When the correctness indicator (ΤχΕΝ) is logic, the correct data index (RxEN) of the received data is logic 0. If the voltage difference (ΤΡ1) on the bus is positive, the received data (RxD) is the logical bus. The voltage difference (τρ1) is negative, and the received data (IUD) is logical 〇; when the bus transmission indicator (BGE) is logic 〇 or the output data correctness index (TxEN) is logic i, the voltage difference on the bus (TP1) As a result, the received data correctness indicator (RxEN) and the received data (RxD) are both logical i. Therefore, the FlexRay transmitter 1 and receiver 200 operate correctly and comply with the FlexRay protocol. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [ ^ The above and other objects, features, advantages and embodiments of the present disclosure will be more apparent and understood. The description of the drawings is as follows: FIG. 1 is an embodiment of the present disclosure. The structure of the FlexRay transmitter is not intended. 201136245 Fig. 2 is a circuit diagram of the bus bar 120 of Fig. 1. Fig. 3 is a circuit diagram of the transmission gate ^2/132 of Fig. 1. Fig. 4 is a circuit diagram of the CMOS current mirror 111/131 of Fig. 1. Fig. 5 is a detailed circuit diagram of Fig. 1. Figure 6 is a block diagram showing the structure of a FlexRay combiner of another embodiment of the present disclosure. Figure 7 is a detailed circuit diagram of Figure 6. Lu Figure 8 is a waveform diagram of the transmission signal. Figure 9A is a waveform diagram of the FlexRay Receiver 200 receiving data correctness. Figure 9B is a waveform diagram of the data received by the FlexRay receiver 200. Figure 10 is a waveform diagram of the present invention in which the signal timing of a transmitter is defined in accordance with the FlexRay communication protocol. Figure 11 is a waveform diagram of the delay time specification of the simulated FlexRay transmitter 100. φ Figure 12 is a waveform diagram of the timing of the signal defined by the receiver in accordance with the FlexRay communication protocol. Figure 13 is a waveform diagram of the 2-D delay time specification for a simulated FlexRay receiver. Figure 14 is a waveform diagram of the FiexRay transmitter 1 and the FlexRay receiver 200 under simulated operation. [Main component symbol description] 100 : FlexRay transmitter 110 : First transmitter m 17 201136245 111, 131, 150 : CMOS current 112 Mirror 121 : First end 123 : First resistance - 125 : Second resistance, 140 : CMOS Transmission gate 142: P-type field effect transistor 152: NM0S current tank φ 201: first input voltage 210: hysteresis comparator 221: preset voltage interval 230: charge and discharge pump 241: delay circuit 250: inverter 132: Transmission gate 12 0. Bus bar 122: second terminal 124: bias power supply 130: second transmitter 141: N-type field effect transistor 151: PMOS current source 200: FlexRay receiver 202: second input voltage 220: window Comparator 222: idle state signal 240: sampling circuit 242: flip-flop
Ml〜M6、ml〜m6 :電晶體 m 18Ml~M6, ml~m6: transistor m 18