TW201119396A - Multi-standard video decoding system and method - Google Patents

Abstract

A multi-standard video decoding system comprises a memory, a multi-master bridge interface, a peer-to-peer bus, a plurality of processors and a plurality of hardware accelerators. The memory is employed to store bit stream and temporal data produced during decoding flow. The multi-master bridge interface is connected to the memory. At least one of the plurality of processors receives bit stream from the memory via the multi-master bridge interface. Each of the plurality of hardware accelerators receives instructions from a processor of the plurality of the processors and operates related video decoding flow, and also accesses the memory via the multi-master bridge interface. The peer-to-peer bus is employed to connect the plurality of processors and the plurality of the hardware accelerators.

Description

201119396 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a video decoding system, and more particularly to a multiple standard video decoding system. [Prior Art] [0002] In order to enable a large amount of original data of video and video applications to be quickly transmitted in a limited network bandwidth, the original data is encoded and compressed before being transmitted, and then received by the receiving end and then decoded and restored. The source material is already necessary. With the increasing popularity of multimedia digital applications, consumers' demand for image resolution and the increasing number of video codec operations have also increased. [〇〇〇3] As far as video decoding technology is concerned, in order to achieve the requirement of 'high-definition picture quality video instant decoding, it is generally implemented by hardware, and the large-scale operation generated by hardware design to cope with high-resolution image quality the amount. However, hardware design is usually for a single video decoding standard. To support other different video decoding standards, the circuit in the hardware design must be removed or added, lacking flexibility and scalability. If video decoding is implemented by software, although various video decoding standards can be supported, the performance improvement of general-purpose processors is limited by a large amount of data bus access, and it is difficult to meet the requirements of high-definition video quality instant decoding. SUMMARY OF THE INVENTION [0004] In view of the above, it is desirable to provide a software and hardware integrated multiple standard video decoding system. The present invention provides a multi-standard video decoding system including a memory, a multi-master bridge interface, a complex processor, and a complex hardware accelerator. This memory is used to store the bit stream and the temporary data in the decoding process. 098139845 Form No. A0101 Page 4 of 27 0982068407-0 201119396 This multi-master bridge interface is connected to this memory. The complex processor includes at least one processor that receives the bit stream from the memory via the multi-master bridge interface; and each of the plurality of hardware accelerators receives a processor from the plurality of processors The video decoding related process is executed by the instruction, and the memory is accessed via the multi-master bridge interface. The present invention also provides a multiple standard video decoding system including a memory, a multi-master bridge interface, a point-to-point bus, a complex processor, and a complex hardware accelerator. The complex processor includes a processor that receives the bit stream from the memory via the multi-master bridge interface. Each of the plurality of hardware accelerators receives an instruction from a processor of the plurality of processors to perform a video decoding related process, and accesses the memory via the multi-master bridge interface .V2=.:-p' plane And connected to each of the plurality of processors via a point-to-point bus. The present invention also provides a multiple standard video decoding method, which is implemented in a system. A first processor of the system receives the bit stream, and performs a variable: length weight through a first hardware accelerator of the system, and performs discrete cosine inverse conversion through a second hardware accelerator of the system. Motion compensation is performed through a third hardware accelerator of the system, and finally a deblocking is performed through a fourth hardware accelerator of the system. [Embodiment] The present invention utilizes a complex processor to share the computational amount of the video decoding process, and implements a decoding process commonly used by different video standards through a hardware module. Please refer to the hardware module 1〇〇 shown in Figure 1, including entropy decoding (En_ tr0py Decode) 11〇, inverse conversion (Inverse Transf〇rm 098139845 Form No. A0101 Page 5 / 27 pages 0982068407-0 201119396 ) 111 , hardware compensation (Motion Compensation) 112 and block noise filtering (De-Blocking Filter) 113 and other hardware accelerators. The extractive decoding 11〇 mainly performs the inverse process of entropy encoding (Entropy Encode) to obtain information such as Variable Length Code (VLC) and motion vector (Motion Vector) as information for decoding and reconstructing the image. The conversion 111 is used to restore the frequency domain image data to the spatial domain image data, and the motion compensation 112 uses the previously restored image data to predict and compensate the decoded image data, and finally the block noise filtering U3. Perform post processing of the reconstructed image. [00〇9] Please refer to FIG. 2, which shows a block diagram of the structure of the video decoding system 200. The video decoding system 200 includes a plurality of processors 210-212, a plurality of hard accelerators in the hardware module 100 in FIG. 1, such as Entropy Decode 220, Inverse Transform 221, and Motion Compensation 222. With block noise filtering (De-

Blocking Filter) 223, memory controller 231, memory *·. 232, video output unit 240, bridge interface 251 and point-to-point bus 2521-2528. The complex processors 210-212 can be any type of general purpose processor such as a Digital Signal Processor (DSP) or a reduced instruction set processor (Reduceci).

Instruction Set Computing (RISC). The video decoding system 200 uses the point-to-point bus 2521-2528 as the interconnection between the complex processors 210-212 and the complex hardware accelerators, so that there is no need between the processor and the processor, and between the processor and its associated hardware accelerator. Passing bus arbitration can be used to transfer 098139845 Form No. A0101 Page 6 / Total 27 Page 0982068407-0 201119396 Order flow and data flow. The bridge interface 251 is a multi-master bridge interface (

The multi-master bridge interface can directly access the memory 232 through the memory controller 231 via the bridge interface 251 'the complex processor 21 〇 _212 and the plurality of hardware accelerators. The memory 232 can be a Rand〇m Access Memory (RAM), such as a static random access memory (SRAM) or a dynamic random access memory (Dynamic RAM). Referred to as DRAM), it is used to store coefficient data and image data generated during the decoding process. The plurality of hardware accelerators in the memory 232 may have their own buffers for accessing data during operation, or a set of shared buffers may be used as data exchanges for the video decoding system. It is outputted by the video output unit 24〇 and output. [0010] The video decoding system 200 can be implemented in a device or transmission system having various video application fields, including a wireless multimedia device, a standard resolution and a high-resolution television broadcasting application, an Internet video application, and a transmission high resolution. Video digital video discs, digital set-top boxes and handheld electronic devices. It should be understood that the decoding process and the hardware acceleration H operation of the complex processor y〇_212 will be different according to different video coding standards. In order to balance the system performance and the hardware cost, the decoding program responsible for the processor and the decoding program responsible for the hardware accelerator can also be allocated in time to obtain a performance balance between the hardware and the hardware. For example, in the processor 202 The decoding program is responsible for the inverse quantization of the decoding program. The inverse conversion 221 is responsible for reducing the inverse quantized image data from the frequency domain to the spatial domain' or the inverse decoding and 221 decoding process of the inverse quantization and inverse conversion. 098139845 Form No. A0101 Page 7 of 27 Page 0982068407-0 201119396 [0011] [(8) 12] [0013] Please refer to FIG. 3 ' is a schematic diagram of a method 300 for performing general video decoding using the video decoding system of FIG. 2, wherein The processors 3〇1_3〇3 are respectively implementations of the processor 210212, and the entropy decoding 3〇4, the inverse conversion 3〇5, the motion compensation 306, and the block noise 遽307 are respectively 嫡 decoding 220 and inverse conversion 221 In the embodiment of the hardware accelerator such as the motion compensation 222 and the block noise transition 223, the memory 3QQ is an embodiment of the memory 232. The processor 301 receives the encoded bit stream from the memory 33, and discriminates the video encoding standard used by the bit stream according to the syntax structure via the syntax analysis program 3〇8. After learning the video coding standard, the data is transmitted to the entropy solution hardware 3Q4 and commanded to perform decimation, and the transmission speed of the command stream and the data stream is controlled by controlling the clock cycle. The input of the decoding hardware accelerator 304 may be a bit stream or a macro block. If it is a macro block, the block header data in the bit stream is already in the processor 3G1. The decoding is done in the syntax parser. In another embodiment, the processor 3(1) can determine whether to dynamically start the internal program by knowing the video coding standard. For example, the processor 301 dynamically starts the motion vector reconstruction procedure to reduce the next step. Decode the load of other processors in the program. The output processed by the entropy decoding hardware accelerator 3〇4 includes a motion vector block quantization parameter and a quantized discrete cosine transform coefficient matrix, etc., which are transmitted by the entropy decoding hardware accelerator 304 to the processor 3G2 for further decoding processing. After receiving the motion vector, the block quantization parameter and the quantized discrete cosine transform coefficient matrix, the processor 302 uses the block quantization parameter and the quantized discrete cosine transform coefficient matrix as the input data of the inverse quantization program 309, and reconstructs the motion vector as the motion vector. The input data of the program 310. Anti-quantization program 098139845 Form No. A0101 Page 8/Total 27 Page 0982068407-0 201119396 309 Decode the program for the quantized discrete cosine transform coefficient matrix with the received block quantization parameter, and output the inverse quantized discrete cosine transform The coefficient matrix is passed to the inverse conversion hardware accelerator 305 while it is instructed to perform the inverse conversion. The motion vector reconstruction program 310 is responsible for the decoding process of the motion vector prediction and reconstruction, outputs the predicted macroblock, and transmits it to the motion compensation hardware accelerator 306, and simultaneously commands the motion compensation decoding program. The inverse conversion hardware accelerator 305 can be implemented by a butterfly algorithm to support discrete cosine inverse conversion of a multi-signal coding standard. For example, the inverse conversion hardware accelerator 305 can support 8x8 discrete cosine inverse conversion of the MPEG-2 video coding standard. 'H. 264 video coding standard 4x4 integer inverse conversion and WMV9/VC-1 video coding standard 8x8, 8x4, 4x8, 4x4 integer inverse conversion. The inverse conversion hardware accelerator 305 obtains a coefficient matrix by discrete cosine inverse conversion operation, which is a residual system data (Residual Values), and the inverse conversion hardware accelerator 305 performs the operation of discrete cosine inverse conversion, that is, the residual coefficient The data is stored in a buffer 331 in the memory 330. The buffer 331 is shared by the inverse conversion hardware accelerator 305, the motion compensation hardware accelerator station 6, and the block noise filtering hardware plus the 307. That is, the inverse conversion hardware accelerator 305, the motion compensation hardware accelerator 306, and the block noise filtering hardware accelerator 307 can all access the buffer 331. [〇〇14] After receiving the command and data of the processor 302, the motion compensation hardware accelerator 306 reads the above residual pixel data output from the inverse conversion hardware accelerator from the shared buffer 331 and the above predicted macroblock block. Adding the residual pixel data to obtain a reconstructed macroblock and storing it in the buffer 331. The reconstructed macro block still has to pass the block noise filtering hard 098139845 Form No. A0101 Page 9 / Total 27 pages 0982068407-0 201119396 After the block accelerator is removed, the macro block is completed. Complete decoding. The operation of the block noise filtering hardware accelerator 307 is controlled by the filter control program 311 in the processor 303. The filter controller knows whether it completes the decoding process by monitoring the state register of the motion compensation hardware accelerator 306. Once it is known that the motion compensation hardware accelerator 306 completes the decoding process, the command block noise filtering hardware accelerator 307 is buffered. The area 331 reads the reconstructed macro block, and after the block removal effect is completed, the macro block is stored into the currently reconstructed face of the memory 330, and the complete decoding of the macro block is completed. [0015] An embodiment of decoding a video encoded bitstream such as H.264 and VC-1 using the present invention will now be described. [0016] The H.264 standard, also known as MPEG-4 Part 10, is the ITU Telecommunication Standardization Sector (ITU-T) and the International Organization for Standardization (International Organization for Standardization). The video coding standard jointly developed by the Motion Picture Experts Group (MPEG) under the Interna-Tational Electrotechnical Commission (IEC), the official name is Advanced Video Coding (AVC), with block as the basic unit, provides a variety of macro block types for motion estimation (Mo-tion Estimation) and motion compared to previous video coding standards. Motion Compensation, a 4x4 macroblock, enables more precise segmentation of motion regions in an image sequence. 098139845 Form No. A0101 Page 10/Total 27 Page 0982068407-0 201119396 [0017] 264. When performing motion compensation calculation on 264, it provides a reference value that is most similar to the current decoding macroblock in multiple reconstructed pictures, called the picture. Inter-frame prediction, the referenced reconstructed picture can be up to 31 sheets and 31 sheets in the future. H.264 also provides pixels that are decoded without reference to other reconstructed pictures' extrapolation, called intra-frame prediction. In the entropy coding part, H.264 uses a single coding table for non-conversion coefficients, and uses content adaptability (C〇ntext_adaptive ❹) coding technique for the quantized conversion coefficients, depending on the probability of occurrence of the code word. Generate a suitable code table to increase the compression ratio. Content adaptive coding techniques are divided into two types: one is adaptive variable length coding (Context_adaptive)

Variable-Length Codes </ acronym CAVLC), another context-based adaptive one-bit arithmetic (C. ontext-based

Arithmetic Coding (abbreviated as CABAC), [0018] ❹ Please refer to FIG. 4, which is a decoding solution of FIG. 2: code system 2〇〇 decoding Η. 264 bits

~ r4 1 I-stream flow method 400, wherein processor 4 404 is an implementation of processor 210-212, entropy decoding 4〇4, inverse conversion 405, motion compensation 406, and block noise filtering 407 The memory 430 is an implementation of the memory 232, such as an implementation of a hardware accelerator such as entropy decoding 220, inverse conversion 221, motion compensation 222, and block noise filtering 223. [0019] The processor 401 receives the 264 bit stream 420 from the memory 430, and the syntax parser program 408 knows that the video encoding standard is Η. 264, and the lower instruction decodes the bit stream to the network decoding hardware accelerator 404. . The entropy decoding hardware adder 404 decodes the received bit stream according to the syntax structure and the main data required for the next solution process, including motion vector, quantization coefficient, and 098139845 form number Α 0101 page 11 / A total of 27 pages 0982068407-0 [0020] [0021] 201119396 Forecast mode indicators, etc., and transmitted to the processor 4〇2. After receiving the quantized coefficients, the processor 402 obtains the dequantized coefficients through the inverse quantization program _, transmits the dequantized coefficients to the inverse conversion hardware accelerator 4G5, and performs a 4x4 integer inverse conversion, and stores the dequantized inter-domain pixel data to the same. One of the memory classes still shares the buffer, and the spatial domain pixel data is also called residual pixel data. After the processor 4〇2 is connected to the (4) motion vector, 'via the motion vector reconstruction program 4ig, the singular or the reconstructed picture from the singular or plural pre-decoded secrets is read from the memory 43〇 according to the offset of the motion vector record. The plural number is divided into 3 areas and 1 number and the inter-picture _ macro block is generated. When the predicted macro block data is generated, it is transmitted to the motion compensation hardware accelerator 4〇6, and the 8 and 8 motion compensation is conceived. Accelerating the H4_reverse conversion hard ship plus the fascination to the residual pixel data of the shared buffer 431 in the memory 430, storing the remaining pixel data and receiving the predicted macro block like the data reconstruction of the huge money block, and then The reconstructed macroblock is stored in the shared buffer 431 of the 430. &apos;&quot; Basket When the processor 402 receives the indication of the intra-picture prediction mode, 3 no, the anti-screen prediction program 412 of the notification processor 403 regenerates the written intra-block. Once the intra-frame prediction macroblock is generated, the processing pre-:= is sent to the motion compensation hardware to accelerate H4G6, and the motion compensation hardware adder 406 is read to read the inverse conversion hardware accelerator 405 to the recording body acceleration. The residual pixel data of the buffer is added to the reconstructed macroblock pixel data to obtain the reconstructed 'pre-^ block, and then the reconstructed macro block is stored in the memory 43〇 One of the ~ drought buffer 4 31 C1 〇 098139845 Form No. A0101 Page 12 / Total 27 page 0982068407-0 201119396 [0022] The filter control program of the processor 403 4 monitors the state of the motion compensation hardware accelerator 406 Once the motion compensated hardware accelerator 406 completes the reconstruction of the macroblock and stores the macroblock to the shared buffer 431 in the memory 430, the command block noise filtering hardware accelerator 407 is shared from the memory 430. The buffer 431 reads the reconstructed macroblock to remove the block effect' and writes the reconstructed macroblock after removing the block effect back to the currently reconstructed picture stored in the memory 430 to complete the macro block integrity. solution 0 [_ VC-1 predecessor to WMV version 9. WMV, full name Windows Media

Video, a generic term for a series of video codec formats developed by Microsoft itself, was submitted to the Society of Motion Picture and Television Engineers (Society of Motion i&gt;icture and

Television Engineers (SMPTE), in order to make WMV9 one of the video coding standards, WMV9 officially became the video coding standard in April 2006 and was named 1 by SMPTE. The encoding process of VC-1 is similar to that of H.264. It is encoded by the part of the spatial domain and the time domain that human vision cannot detect, and the effect of video compression is achieved. [0024] VC-1 also uses block as the basic unit of coding. Compared with H.264, it provides seven different sizes of macroblocks for motion estimation and motion compensation, and VC-1 provides 16x16, 16x8, and 8x16. Split with four sizes of macroblocks such as 8x8. VC-1 also provides inter-picture prediction and intra-plane prediction. Two dynamic prediction modes. For inter-picture prediction, the reconstructed picture that VCy provides for reference can only be forwarded one at a time and backward (10). For intra-picture prediction, H. 264 uses spatial domain pixel data for intra-picture prediction. 'VC-1 makes the (four) near-block quantized conversion coefficient as prediction data 098139845 Form No. A0101 Page 13/27-100' H 0982068407-0 201119396 Also known as AC/DC prediction. Compared to the previous video coding standard, which uses 8x8 macroblocks or 4x4 blocks as conversion units, VC-1 allows four different sizes of Adaptive Block Size Transform. In addition, VC_1 has a different deblocking solution called 'Overlap Transform'. The traditional block noise is too low, although it can effectively reduce the block effect, but block noise filtering is a step that will be performed after the reconstruction is restored, which may result in loss of image details. The overlap conversion technique of VC-1 is performed by pre-processing in the spatial domain during encoding, and with post-processing in decoding, and is performed only for the block type. As for the entropy coding part, ν〇1 is variable length coded for both the non-transformation coefficient and the quantized conversion coefficient. Referring to FIG. 5, a schematic diagram of a method 500 for decoding a VC-1 bitstream using the video decoding system 200 of FIG. 2, wherein the processors 501-503 are implementations of the processors 210-212, respectively, entropy decoding 504. The inverse 505, the motion compensation 506, and the block noise filtering 507 are implementations of the hardware accelerator such as entropy decoding 220, inverse conversion 221, motion compensation 222, and block noise filtering 223, respectively. Embodiment of body 232. The processor 501 receives the bit stream 520 from the memory 530, and the syntax parser program 508 knows that the video coding standard is VC-1, and the next instruction sends the entropy decoding hardware accelerator 504 to decode the bit stream. The hardware accelerator 5〇4 decodes the bit stream according to the syntax structure to the main data required for the next process, including motion vectors, quantization coefficients, AC/DC prediction indicators, and so on. The decimation code hardware accelerator 504 passes back the motion vector to the processor 501 and the remainder to the processor 502. 098139845 Form No. 1010101 Page 14/Total 27 Page 0982068407-0 201119396 [0027] Ο = _ After receiving the quantized coefficient, the inverse conversion program _ to the summerization coefficient is used to accelerate the inverse conversion hardware (4) $ and command it Into the whole limb conversion, the above dequantization coefficients are restored from the frequency domain to the space. The pixel data is read to a shared buffer 531 in the memory 53. The pixel data of the gate field is also referred to as residual pixel data. After receiving the motion vector, the processor 501 reads the reference macroblock in the reconstructed picture in the pre-decoding flow from the memory coffee via the motion vector reconstruction program 509 according to the offset of the motion vector record, and generates a picture. The macro block, when the predicted macro block pixel data is generated, is transmitted to the motion compensation hardware accelerator 5〇6, and commands the motion compensation hardware accelerator 506 to read the inverse conversion hardware accelerator 505 storage. The residual pixel data of the shared buffer 531 in the memory 530 is shared, and the residual pixel data is added to the macroblock image data received by the prediction to obtain the reconstructed macroblock. The shared buffer mi is stored in the memory 530. [0028] When the processor 502 receives the AC/DC prediction indicator, the intra-picture prediction macroblock is regenerated via the reverse AC/Q DC prediction procedure 511. Once drawn, I &quot;, sr A ::^ in-plane prediction macroblock generation is then transmitted by processor 502 to motion-compensated hardware accelerator 506' and commands motion-compensated hardware accelerator 506 to read the inverse-conversion hardware The accelerator 505 stores the residual pixel data of the shared buffer 531 in the memory 530, and adds the residual pixel data to the macroblock pixel data received by the prediction to obtain a reconstructed macroblock, and then the reconstructed macro. The block is stored in the shared buffer 531 in the memory 530. [0029] The processor 503 includes two programs, one being an overlap conversion program 512 and the other being a filter control program 513. Overlap conversion program 512 is used to monitor the inverse conversion hard 098139845 Form No. A0101 Page 15 / Total 27 Page 0982068407-0 201119396 Volume Acceleration 11505 Status Register, - Reverse Conversion Hardware Accelerator 5〇5 Complete integer inverse conversion and save The residual pixel data is shared in the buffer 53 in the memory 53, and the residual pixel data is read for overlap conversion, and then written back to the shared buffer 531 in the memory 530. The transition control program 513 monitors the state register of the motion compensation hardware accelerator 506. Once the motion compensation hardware accelerator 506 completes the reconstruction of the macro block and stores the shared buffer 53 in the macro memory resident memory 530, the command block The noise filtering hardware accelerator 507 reads the reconstructed macro block from the shared buffer 531 in the memory 530 to remove the block effect, and after the filtering is completed, writes the reconstructed macro block back. Stored in the memory 53〇Η currently reconstructed, complete the decoding of the giant box. [0030] In summary, the present invention meets the requirements of the invention patent and abandons the patent application according to law. However, the above-mentioned embodiments are merely preferred embodiments of the present invention, and equivalent modifications or variations made by those skilled in the art to the present invention are included in the following claims. [Simple description of the map]

[0031] FIG. 1 is a schematic diagram of one embodiment of a hardware module 100. U

2 is a block diagram showing the structure of an embodiment of a video decoding system 200. 3 is a schematic diagram of a method for performing general video decoding using the video decoding system 200 of FIG. 2. 4 is a schematic diagram of a method of decoding a 264 bit stream using the video decoding system 200 of FIG. 2. 5 is a schematic diagram of a method of decoding a V C -1 bit stream using the video decoding system 200 of FIG. 2. 098139845 Form No. 101 0101 Page 16 / Total 27 Page 0892068407-0 201119396 [Main Element Symbol Description] [0036] Entropy decoding 110, 220, 304, 404, 504 [0037] Reverse conversion 111, 221, 305, 405, 505 [ 0038] Motion Compensation 112, 222, 306 '406, 506 [0039] Block Noise Filter 113, 223, 307, 407, 507 [0040] Processors 210, 211, 212, 3 (Π, 302, [0041] 303, 401, 402, 403, 501, 〇 [0042] 502, 503 [0043] Memory Controller 131 [0044] Memory 232, 330, 430, 530 [0045] Video Output Unit 240 [0046] Bridge Interface 251 [0047] Point-to-point bus 2251, 2522, 2523, 2524, 〇 [0048] 2525, 2526, 2527, 2528 [0049] Syntax parsing 308, 408, 508 [0050] Motion vector reconstruction 310, 410, 509 [0051] Filtering Control 311, 411, 513 [0052] Encoded bitstream 320 [0053] Buffer 331, 431, 531 [0054] Intra-picture prediction 412 098139845 Form number A0101 Page 17 of 27 page 0982068407-0 201119396 [0055] 264. 264 bit stream 420 [0056] inverse AC/DC prediction 511 [0057] Overlap conversion 512 [0058] VC -1 bit stream 520 09820684 0 098139845 Form number Α0101 Page 18 of 27

Claims (1)

201119396 VII. Patent application scope: 1. A multiple standard video decoding system, comprising: • a memory for storing bit stream and temporary data during decoding; a multi-master bridge interface connected to the memory a complex processor, wherein the complex processor includes at least one processor, receiving the bit stream from the memory via the multi-master bridge interface; and a plurality of hardware accelerators, each of which receives from the hardware accelerator The instruction of one of the plurality of processors performs a video decoding process and accesses the memory via the multi-master bridge interface. 2. The multiple standard video decoding system of claim 1, wherein the plurality of processors are coupled via a point-to-point bus. 3. The multiple standard video decoding system of claim 1, wherein the plurality of processors are coupled to the corresponding hardware accelerator via a point-to-point bus. 4. The multiple standard video decoding system of claim 1, wherein the plurality of hardware accelerators comprise a first hardware accelerator, the first hardware accelerator receiving from one of the plurality of processors The decoding instructions perform variable length decoding. 5. The multiple standard video decoding system of claim 1, wherein the plurality of hardware accelerators comprise a second hardware accelerator, the second hardware accelerator receiving decoding instructions from one of the plurality of processors Perform discrete cosine inverse conversion. 6. The multi-standard video decoding system of claim 1, wherein the plurality of hardware accelerators comprise a third hardware accelerator, the third hardware 098139845, form number A0101, page 19, total 27 pages 0982068407- 0 201119396 The accelerator receives motion decoding from another of the complex processors to receive a decoding instruction. 7. The multiple standard video decoding system of claim 1, wherein the plurality of hardware accelerators comprise a fourth hardware accelerator, the fourth hardware accelerator receiving decoding from one of the plurality of processors The instruction performs a deblocking transition. 8. The multiple standard video decoding system of claim 1, wherein the plurality of hardware accelerators share a buffer with the memory for data exchange. 9. A multiple standard video decoding system, comprising: a memory; a multi-master bridge interface; a point-to-point bus; a complex processor, wherein at least one processor receives the memory from the memory via the multi-master bridge interface a bit stream; and a plurality of hardware accelerators, each of the plurality of hardware accelerators receiving an instruction from the plurality of processors to perform a video decoding process, accessing the memory via the multi-master bridge interface, and via a point-to-point The bus connects the processors. The multi-standard video decoding system of claim 9, wherein the plurality of processors are connected via a point-to-point bus. 11. The multiple standard video decoding system of claim 9, wherein the plurality of hardware accelerators comprise a first hardware accelerator, the first hardware accelerator receiving decoding instructions from one of the plurality of processors Start with variable length decoding. 12. The multiple standard video decoding system according to claim 9 of the patent application, 098139845 Form No. A0101, page 20/27 pages 0982068407-0 201119396 13 . 14 . ❹ ' 15 . 16 . The plural hardware accelerator Including - a second hardware accelerator, the second hardware accelerator performs a discrete cosine inverse conversion starting from a number of (4) other (4) code instructions. The multiple standard video decoding system of claim 9, wherein the plurality of hardware accelerators include a third hardware accelerator, and the third hardware accelerator receives decoding instructions from the plurality of the plurality of processors. And perform motion compensation. Such as Shen. The multi-standard video decoding system of claim 9, wherein the plurality of hardware accelerators include a fourth hardware accelerator, the fourth hardware accelerator is executed by receiving the decoding instruction from the plurality of processors Go to block filtering. : The multi-standard video decoding system described in claim 9 of the patent scope, wherein the "number of hardware accelerators" and the recording unit are used for data exchange. A multi-standard video decoding method, in the multi-standard video decoding system, comprising: 4 G, the multi-standard video decoding system transmits the multi-standard video decoding length-length coding; Cosine inverse conversion; dynamic compensation through the multi-standard video decoding; and filtering of the φ block by the multi-standard video. a first processor receives the bit stream; a first hardware accelerator of the system performs a second hardware accelerator to perform a third hardware accelerator execution of a third hardware accelerator 098139845. The second hardware accelerator, the third hardware accelerator and the second hardware accelerator of the 09820 17 201119396, as described in claim 16 of the patent scope of the patent application. The fourth hardware accelerator shares a buffer to exchange data. 098139845 Form No. A0101 Page 22 of 27 0982068407-0