TW201117347A - Multi-chip stack structure - Google Patents

Abstract

A multi-chip stack structure is disclosed herein. The present invention includes a substrate, a plurality of memory chips, an interposer substrate, a logic chip and a plurality of wires. Those memory chips are stacked on the substrate and electrically connects to the upper surface of the substrate. The interposer substrate are set on those memory chips, wherein a plurality of first contacts and plurality of second contacts are set on a upper surface of the interposer substrate, and those second contacts are arranged around the edge of the interposer substrate; and a plurality of first bumps are set on the botton surface of the interposer substrate to electrically connect with those memory chips. The logic chip set on the upper surface of the interposer substrate and electrically connected to those first contacts. Those wires utilized to electrically connect those second contacts with the upper surface of the substrate. An interposer substrate is set between the memory chip and the logic chip to reduce the fabrication process and economize the use of the substrate.

Description

201117347 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a multi-wafer stack structure. [Prior Art]

With the rapid improvement of functions such as computer and network communication, it is necessary to have the needs of diversification, portability and lightness and miniaturization, so that the chip packaging process industry is out of the traditional test_高神, high density, light High-precision processes such as thinness and miniaturization, and with the increasing demand for miniaturization and high operating speeds, multi-chip package structures are becoming more and more common. The multi-wafer construction can be minimized by combining two or more crystals in the f-slit structure. There are roughly two ways to install a three-dimensional package, namely the package upper seam (pa «package ’ PoP) and the package package bing 匕 咖 咖 咖, pip). The state's two typical 3D seals are designed to be packaged and tested on both sides to reduce process risk and increase product time. However, the combination of the two sides of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The technology of vertical integration into the two-dimensional space has been proposed to achieve the benefits of 2Fs. The integration with the existing planar wafers has the same solution, and the three-dimensional space is relatively time-dependent, _ 嶋 嶋 and delay consumption. However, when the power efficiency is improved and the wafer work is reduced, the input/output wiring design is greatly different. Therefore, in order to solve the above problems, one of the objects of the present invention is to provide a multi-wafer stack structure, which is utilized in memory. An interposer is placed between the bulk wafer and the logic wafer to simplify process complexity and save substrate cost. An object of the present invention is to provide a multi-wafer stack structure comprising: a substrate; a plurality of memory chips disposed on the substrate and electrically connected to the upper surface of the substrate; an interposer substrate disposed above the memory wafer, wherein the plurality of first contacts And the plurality of second contacts are disposed on an upper surface of the interposer, and the second contacts are located on the periphery of the interposer; and the plurality of first bumps are disposed on the lower surface of the interposer, and the first bumps and the memory pads are electrically The logic chip is disposed on the upper surface of the substrate and electrically connected to the first contact; and the plurality of gold wires are used to electrically connect the second contact of the interposer with the upper surface of the substrate. The purpose, technical contents, features and effects achieved by the present invention will be more readily understood from the following detailed description of the embodiments. [Embodiment] The detailed description is as follows, and the preferred embodiment is not intended to limit the invention. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a multi-wafer stack structure according to an embodiment of the present invention. As shown, the multi-chip package structure includes a substrate 10, a plurality of memory chips 20, an interposer substrate 30, a logic wafer 40, and a plurality of gold lines 50. As shown, the memory chips 20 are stacked on the substrate 10 and electrically connected to the upper surface 11 of the substrate 10. The interposer substrate 30, for example, is formed on the memory chip 20, wherein the interposer substrate 30 includes a plurality of first contacts 32 and a plurality of second contacts 34 disposed on an upper surface 31 thereof, and the second contacts The 34 series is located on the periphery of the interposer substrate 30. The plurality of first bumps 36 are disposed on a lower surface 35 of the interposer substrate 30, and the first bumps 36 are electrically connected to the memory chip 20 disposed therebelow. The logic chip 40 is placed on the upper surface 31 of the interposer substrate 30 and electrically connected to the first contact 32. The plurality of gold wires 50 are electrically connected to the second contact 34 of the interposer substrate 30 and the upper surface 11 of the substrate 10. The use of the interposer substrate 30 can improve the complicated process resulting from the difference in the input/output wiring design (I/Olayout) of the memory-wafer 20 and the logic chip 40. Continuing the above, please refer to FIG. 2 'In this embodiment, the logic chip 40 is disposed at the top of the multi-wafer stack structure to facilitate heat dissipation management. Therefore, an embodiment of the present invention further includes a heat sink 60 disposed on the logic chip 40. The heat dissipation is enhanced. Further, the logic wafer 40 is disposed at the top of the multi-wafer stack structure to reduce the complexity of the design of the lower substrate 10, thereby reducing the substrate cost. Referring to Figure 2, the structure further includes a plurality of solder balls 70 disposed on the lower surface 13 of the substrate 10 for mounting on an external device. With continued reference to FIG. 1, in one embodiment, the memory chips 20 are electrically connected to each other using a plurality of turns via structures 22. As shown in FIG. 1 , a plurality of second protrusions 26 may be disposed under the via hole structure 22 such that the memory chip 2 located above is supported by the second bump 26 and the memory chip 20 located below. The through-hole structure 22 is electrically connected. In addition, the first bumps 36 of the interposer substrate 30 and the memory chip 2's disposed underneath are also electrically connected by the via via structure 22. Utilizing the via structure as the bridge of the electrical connection φ can reduce the space of the wire stacking to reduce the size of the multi-wafer stack structure. In one embodiment, as shown in FIG. 1, a plurality of solder balls 42 are disposed under the logic wafer 40 for electrically connecting the logic wafer 40 with the first contact 32 on the interposer substrate 30. The logic wafer 40 is electrically connected to the interposer 3 by the manner and structure of the recording ball 42, and the warpage problem which may occur due to the difference in thermal expansion coefficient can be improved. In another embodiment, as shown in FIG. 3A, the multi-chip package structure further includes an upper surface 11 of the package substrate 80, the memory chip 2, the interposer substrate 30, the logic wafer 40, and the gold line. 50. In still another embodiment, as shown in FIG. 3B, the encapsulant 80 exposes a portion of the logic die 4, such as the upper surface 41' of the logic die 40, and a heat sink 62 is disposed on the encapsulant.

r C 201117347 and a portion of the exposed logic die 40, such as the upper surface 41 of the logic die 40, is attached to enhance the heat dissipation function. In another embodiment, as shown in FIG. 3C, the multi-wafer stack package further includes a primer 90 filled between the substrate 10 and the memory wafer 20, between the memory chip 20 and the memory wafer 20, and an interposer substrate. 30 is between the memory chip 20. In another embodiment, referring to FIG. 3D, when stacking the memory chips 20, the through-hole structure 22 can also be directly used as a bridge for electrical connection without providing bumps. In accordance with the above, one of the features of the present invention is to place a logic die at the top of the multi-wafer stack structure to enhance the heat dissipation function. In addition, the logic wafer is electrically connected to the first contact on the substrate by the plurality of solder balls, thereby improving the problem of warpage and electrical joint failure which may occur due to the difference in thermal expansion coefficient between the interposer substrate and the logic chip. Moreover, the logic chip is disposed on the interposer substrate, and the input and output wiring design of the different logic chips can be re-wired on the intermediate substrate, which is quite flexible in the process. Furthermore, the interposer substrate and the plurality of stacked memory chips can be electrically connected to each other using a via via structure, and the thickness of the multi-wafer stack package can be effectively improved. In summary, the present invention utilizes an interposer between the memory chip and the logic die to simplify process complexity and save substrate cost. The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a multi-wafer stack structure according to an embodiment of the present invention. 2 is a cross-sectional view showing a multi-wafer stack structure according to still another embodiment of the present invention. 3A, B, 3C, and 3D are cross-sectional views showing a multi-wafer stack structure in accordance with various embodiments of the present invention. [Requires symbol description]

10 Substrate 11, 31, 41 Upper surface 13, 35 Lower surface 20 Memory chip 22 Stone-to-ear hole structure 26, 36 Bump 30 Interposer 32 First contact 34 Second contact 40 Logic wafer 42, 70 Ball 50 Gold wire 60, 62 Heat sink 80 Encapsulant 90 Primer 8

Claims (1)

201117347 VII. Patent Application Range: L A multi-wafer stack structure comprising: a substrate; a plurality of memory chips are stacked on the wire board and connected to the substrate; and an interposer substrate is disposed above the memory chips, wherein a plurality of first contacts and a plurality of third contacts are disposed on an upper surface of the interposer, and the second contacts are located on the periphery of the interposer, and are disposed on the lower surface of the interposer. And the first _ bumps are electrically connected to the memory chips; the electrical slab = the social filaments disposed on the towel substrate and the first contact plates = gold wire The plurality of wafer contacts electrically connected to the interposer substrate and the multi-wafer stack structure as described in claim i, wherein the plurality of diametrical via structures are electrically connected to each other. The multi-wafer stack structure described in claim 2, further comprising a plurality of second bumps disposed under the 石 通 通 结构 , , , , , , , , , , , , , , , , , , , , , The second bumps are electrically connected to the (four) via structure of the underlying memory cell wafer. If the request item 2 is used for turning and turning, the towel projection is below the plurality of the memory chips of the memory chip disposed under it, for electrically connecting the logic chip and the The multi-wafer stack structure of the interposer substrate 6·==1, further comprising a plurality of solder balls disposed on the substrate 7. The multi-wafer stack structure described in Item 1 further includes a heat sink disposed on the logic 8. The multi-wafer stack structure of item 1, further comprising an upper surface, the memory wafers, the interposer substrate and the logic wafer, the earth wafer 201117347. The multi-wafer stack structure according to claim 7, wherein the encapsulant A portion of the logic chip is exposed, and a heat sink is disposed on the encapsulant and attached to the exposed portion of the logic chip. 10. The multi-wafer stack structure of claim 1, further comprising a primer filled between the substrate and the memory chips, between the memory chips, and the interposer and the memory chip. between.