201115329 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種匯流排介面之測試方法，尤其係關於一種 針對主機pc正插槽上匯流排介面之測試方法。 【先前技術】 周邊裝置元件互連（Peripheral Component Interconnect，簡稱 pci)疋一種連接電腦主機板和周邊設備的匯流排標準，由 公司所制定發表。它可以與中央處理單元（Ce_ ρΓ〇_ίη§ Unit，簡稱CPu)的位址匯流排、資料匯流排、大部分的控制匯 流排接腳銜接，但必須透過控制晶片轉接訊號。pci標準規定了該 匯流排的實體尺寸（包括線寬）、電力特性、岐排時序和協議等， 其具有匯流排結構簡單、成本低、設計簡單等優點。 快速周邊裝置元件互連（PCI Express，簡稱pc正），是一種 最新的匯流排和介面標準，是Ρα的更高的發展，它沿用了習知 的PCI編程概念及通訊標準，但建基於更快的串列通信系統。扣正 最大的_在於它的通祕，不僅可以讓它用於南橋和其他設備 的連接’也可以延伸到晶片組_連接，甚至也可以用於連接圖 形晶片’這樣，整個輸入/輸出⑽）系統重新統一起來，將更進 一步簡化電腦系統’增加電腦的可攜性和模塊化。此外，由於pc正 採用了目别業内机行的點對點串列連接，比起ρα以及更早期的 電月自匯机排的共賴行雜，其每個設備都有自己的專用連接， 不需要向整倾流排請求帶寬，而且可以㈣料傳輸率提高到一 201115329 個很高的頻率’達到Ρα所不能提供的高帶寬。相對於習知的ρα 匯流排在單一時間週期内只能實現單向傳輸，PC正的優點在於能 夠提供更高的傳輸速率和品質β 目前，主機PCIE插槽（Slot)上的匯流排介面類型包含：系 統管理匯流排（System Management Bus，以下簡稱SMBus )、nc (Inter Integrated Circuit )匯流排以及智慧平台管理匯流排 (Intelligent Platform Management Bus，以下簡稱 π>ΜΒ )。針對主 機PCIE插槽上的這些匯流排介面進行測試時，習知的測試方法是 例如透過測試程式掃描SMBus匯流排上已有的從設備位址（s^ve Address)，此方法只能進行讀取操作，不能進行寫操作，因此並不 能實現真正意義上的SMBus介面之測試。 【發明内容】 為了解決上述習知技術中的問題與陷，本發明提出一種針 對主機PC正插槽上匯流排介面㈤响沈）之測試方法該測試 方法通用性強’真正實現了駐機PCIE鋪上£流排介面的自動 化與智旎化測試，並能夠大幅提高測試之準確性、穩定性及可靠 性。 本發明所提出之-種針對主機pc正插槽上匯流排介面之測 試方法，包括一用以測試主機PC正插槽上匯流排介面是否正常的 方法，係包含以下步驟： 將POE測試治具起始化設定為主設備（Master)模式，並將 主機PC正插槽上的匯流排上的其他設備設定為從設備（Slave); 201115329 透過pc正戦治具依次掃描該主機咖插槽上的匯流排上 的從設備； 判岐奸從設賴POE職治具之糊灿正確回應；以 及 ^ 如果有從設備對PCIE職治具之訪間作出正確回應，則表示 匯流排介©正常，紐絲職；如賴麵上沒有任何從設備 對PC正測試治具之訪問作出正確回應，則表示匯流排介面不正 常，隨後報錯並退出測試。 其中’上述本發撕提出之-種針對主機pcffi插槽上匯流排 介面之測試方法中’所述的PC正測試治具係為基於Msp43〇晶片 與PEX8632晶片的Himalia治具；所述的主機pcE插槽上的匯流 排係為SMBus/nC/EPMB匯流排。 本發明所提出的-種針對主機POE插槽上匯流排介面之測 試方法中，所述的POE測試治具係從位址〇到127依次掃描主機 PCIE插槽上的匯流排上的從設備。 本發明的測試方法還包括針對主機PCIE插槽上匯流排介面 之言買寫測試方法，此測試方法包含以下步驟： 掃描被測主機中所有的從設備（Slave)，藉以尋找空間的從設 備位址（Slave Address ); 將找到的空閒的從設備位址傳輸給PCIE測試治具，並將正 測试治具設定為從設備（Slave)模式； 201115329 透過主機PCIE插槽上的匯流排從PCIE測試治具讀取資料及 向PCIE測試治具寫入資料；以及 判斷主機PCIE插槽上的匯流排之資料讀寫操作是否均正 確’如果是’則表示匯流排介面正常，隨後結束測試；如果否， 則表示匯流排介面不正常，隨後報錯並退出測試。 其中，上述本發明所出之一種針對主機PCIE插槽上匯流排介 面之讀寫測試方法中’所述的PC正測試治具係為基於MSp43〇晶 片與PEX8632晶片的Himalia治具；戶斤述的主機PCIE插槽上的匯 流排係為SMBus匯流排。 此外’上述本發明所出之一種針對主機PC正插槽上匯流排介 面之讀寫測試方法中，係由被測主機之測試應用程式（DiagApp) 透過一輸入/輸出控制器中心（I/O Controller Hub，ICH )的SMBus 控制器掃描被測主中所有的從設備，並且所述的主機pci£插槽 上的匯流排係透過SMBus控制器與PCIE測試治具進行通訊，藉 以從PC正測試治具讀取資料及向PC正測試治具寫入資料。 綜上所述’本發明所提供之針對主機PC正插槽上匯流排介面 之測試方法，由於採用基於MSP430晶片與PEX8632晶片的PC正 測試π具（Himalia治具）以上述兩種方式實現了針對主機正 插槽上匯流排介面之全面測試，因此，本發明所提供之針對主機 PCffi插槽上匯流排介面之測試方法的通用性強，真正實現了對主 機PC正插槽上匯流排介面的自動化與智能化測試，並能夠大幅提 高測試之準確性、穩定性及可靠性。 201115329 【實施方式】 有關本發日㈣雜與實作，賊合_作較佳實施例詳細說 明如下。 請參考「第1圖」’關為本發明之針對域觀 插槽上匯流排介面之賴方法的步驟流程圖，如圖所示，本發明 所提供之—種針駐機PQE插槽上匯流齡面之戰方法，^透 過rciE測試治具對主機POE插槽上的匯流排介面進行測試，此 測試方法包含以下步驟： 將PCIE測試治具起始化設定為主設備（Master)模式，並將 主機PCIE插槽上的匯流排上的其他設備設定為從設備(siave乂步 驟KU) ’其中’所述的PCIE測試治具係可為基於Msp43〇晶片 與PEX8632晶片的Himalia治具，而所述的主機Pc正插槽上的匯 流排係可為SMBus/IIC/IPMB匯流排； 透過pc正測試治具依次掃描該主機PCIE插槽上的匯流排上 的從設備（步驟102)，其中，所述的PC正測試治具係從位址〇 到127依次掃描主機pC正插槽上的匯流排上的從設備； 判斷是否有從設備對PC正測試治具之訪問作出正確回應（步 驟103);以及 如果有從設備對PC正測試治具之訪問作出正確回應，則表示 匯流排介面正常，隨後結束測試；如果匯流排上沒有任何從設備 對PCIE測試治具之訪問作出正破回應，則表示匯流排介面不正 常’隨後報錯並退出測試（步驟104)。 201115329 本發明的測試方法方法還包括針對主機pci£插槽上匯流排 介面之讀寫測試方法’此測試方法的實施例步驟如「第2圖」所 示，包含以下步驟： 掃描被測主機中所有的從設備（slave)，藉以尋找空閒的從設 備位址（SlaveAddress)(步驟201)，其中，係可由被測主機之測 試應用程式（Diag App)透過-輸人/輸出控制器中^ (ICH)的 SMBus控制器掃描被測主機中所有的從設備； 將找到的空閒的從設備位址傳輸給pc正測試治具，並將pci£ 測忒治具設定為從設備（Slave)模式（步驟2〇2)，其中，所述的 PCIE測試治具係可為基於Msp43〇晶片與ρΕχ8632晶片的 Himalia 治具； 透過主機PCIE插槽上的匯流排從pc正測試治具讀取資料及 向PCIE測試治具寫入資料（步驟2〇3)，其中，所述的主機pci£ 插槽上的匯流排係可為SMBus匯流排，並且所述的主機？〇£插 槽上的匯流排係可透過SMBus控制器與PCIE測試治具進行通 訊，藉以從PCIE測試治具讀取資料及向pc正測試治具寫入資料； 以及 判斷主機PCIE插槽上的匯流排之資料讀寫操作是否均正確 (步驟204) ’如果是，則表示匯流排介面正常，隨後結束測試； 如果否’則表示匯流排介面不正常，隨後報錯並退出測試（步驟 205)。 201115329 現在請參考「第3圖」及「第4圖」，「第 針對主機喝槽上匯流排介面之測試方法二^ 試治具與被_之連接_顧，「_」為本發日對 主機PC正插槽上匯流排介面之測試方法中所採用的pc正測办 具之結構方塊圖’如「第3圖」及「第4圖」所示，本發明之列 試方法中所採_ POE職治具财為基於Msp43Q晶片盘 PEX8632晶片的Hlmalia治具1〇，其中，聰％晶片可用作核 心微控制器單元（Core MCU)，ΡΕΧ8632晶片則可用作pc正開關 (PC正 Switch )。201115329 VI. Description of the Invention: [Technical Field] The present invention relates to a test method for a busbar interface, and more particularly to a test method for a busbar interface on a positive slot of a host PC. [Prior Art] Peripheral Component Interconnect (Pci), a busbar standard for connecting computer motherboards and peripheral devices, was published by the company. It can be connected to the address bus, data bus, and most of the control bus pins of the central processing unit (Ce_ ρΓ〇_ίη§ Unit, CPu for short), but the signal must be transferred through the control chip. The pci standard specifies the physical size (including line width), power characteristics, rearrangement timing and protocol of the busbar, which has the advantages of simple busbar structure, low cost, and simple design. Fast peripheral device component interconnection (PCI Express, referred to as pc positive), is a new bus and interface standard, is a higher development of Ρα, it uses the well-known PCI programming concepts and communication standards, but based on more Fast serial communication system. The biggest thing is that it's the secret, not only can it be used for the connection between the south bridge and other devices', but also can be extended to the chipset_connection, and even can be used to connect the graphics chip, so the whole input/output (10) The reunification of the system will further simplify the computer system 'increasing the portability and modularity of the computer. In addition, since the PC is using a point-to-point serial connection in the industry, it has its own dedicated connection compared to ρα and the earlier electric moon. It is necessary to request bandwidth from the inverting flow, and the (four) material transmission rate can be increased to a high frequency of 201115329 'to reach the high bandwidth that Ρα cannot provide. Compared with the conventional ρα busbar, only one-way transmission can be realized in a single time period. The positive advantage of PC is that it can provide higher transmission rate and quality. Currently, the type of bus interface on the host PCIE slot (Slot). Including: System Management Bus (SMBus), nc (Inter Integrated Circuit) bus, and Intelligent Platform Management Bus (hereinafter referred to as π>ΜΒ). When testing these bus interfaces on the host PCIE slot, the conventional test method is to scan the existing slave address (s^ve Address) on the SMBus bus through the test program. This method can only be read. The operation is performed, and the write operation cannot be performed, so the test of the SMBus interface in the true sense cannot be realized. SUMMARY OF THE INVENTION In order to solve the problems and the above problems in the prior art, the present invention proposes a test method for the busbar interface (5) on the positive slot of the host PC. The test method is highly versatile and truly implements the resident PCIE. Automated and intelligent testing of the flow interface, and can greatly improve the accuracy, stability and reliability of the test. The method for testing the bus interface on the positive slot of the host PC includes a method for testing whether the bus interface on the positive slot of the host PC is normal, and the method includes the following steps: The initial setting is set to the master mode, and the other devices on the busbar on the positive slot of the host PC are set as slave devices (Slave); 201115329 scans the host coffee slot in turn through the pc positive jig The slave device on the busbar; the smuggling of the correct response from the singer POE job; and ^ if there is a correct response from the device to the PCIE service, it means that the bus is normal, Niss job; if there is no correct response from the device to the PC test fixture, it means that the bus interface is not normal, and then the error is reported and the test is exited. The PC positive test fixture described in the above-mentioned test method for the busbar interface on the host pcffi slot is a Himalia fixture based on the Msp43(R) chip and the PEX8632 wafer; the host The busbar on the pcE slot is the SMBus/nC/EPMB bus. In the test method for the bus interface on the host POE slot, the POE test fixture sequentially scans the slave devices on the bus bar on the host PCIE slot from the address 〇 to the 127. The test method of the present invention further includes a method for buying and writing a bus interface for a host PCIE slot. The test method includes the following steps: scanning all slave devices in the tested host to find a slave device bit in the space. Slave Address; Transfer the found free slave address to the PCIE test fixture and set the test fixture to Slave mode; 201115329 Pass the bus on the host PCIE slot from PCIE Test fixture reading data and writing data to the PCIE test fixture; and determining whether the data read and write operations of the bus bar on the host PCIE slot are correct 'if yes', indicating that the bus interface is normal, and then ending the test; No, it means that the bus interface is not normal, then an error is reported and the test is exited. The above-mentioned PC positive test fixture for the bus interface interface on the PCIE slot of the host is a Himalia fixture based on the MSp43(R) chip and the PEX8632 chip; The bus on the host PCIE slot is the SMBus bus. In addition, the above-mentioned reading and writing test method for the bus interface on the positive slot of the host PC is performed by the test application (DiagApp) of the tested host through an input/output controller center (I/O). The SMBus controller of the Controller Hub, ICH) scans all the slave devices in the tested master, and the busbars on the host pci£ slot communicate with the PCIE test fixture through the SMBus controller, so that the slave PC is testing The fixture reads the data and writes the data to the PC test fixture. In summary, the test method for the busbar interface on the positive slot of the host PC provided by the present invention is implemented in the above two ways by using the PC-based test π (Himalia fixture) based on the MSP430 chip and the PEX8632 chip. For the comprehensive testing of the bus interface on the positive slot of the host, the test method for the bus interface on the host PCffi slot provided by the present invention is highly versatile, and truly realizes the bus interface on the positive slot of the host PC. Automated and intelligent testing, and can greatly improve the accuracy, stability and reliability of testing. 201115329 [Embodiment] The following is a detailed description of the preferred embodiment of the present invention. Please refer to "FIG. 1" for the flow chart of the method for the bus interface interface on the domain view slot of the present invention. As shown in the figure, the present invention provides a converging on the PQE slot of the needle parking station. The method of age-level battle, ^ test the bus interface on the host POE slot through the rciE test fixture. The test method includes the following steps: The PCIE test fixture is initialized to the master mode, and The other device on the busbar on the host PCIE slot is set as the slave device (siave乂step KU). The PCIE test fixture described in the above can be a Himalia fixture based on the Msp43(R) chip and the PEX8632 chip. The bus line on the positive slot of the host Pc may be an SMBus/IIC/IPMB bus; the slave test fixture sequentially scans the slave devices on the busbar on the host PCIE slot (step 102), where The PC test fixture is sequentially scanning the slave device on the bus bar on the positive slot of the host pC from the address 〇 to 127; determining whether the slave device correctly responds to the access of the PC to the test fixture (step 103) ); and if there is a slave device to the PC If the test fixture accesses the correct response, it means that the bus interface is normal, and then the test is terminated. If there is no positive response from the device to the PCIE test fixture on the bus, it means that the bus interface is not normal. And exit the test (step 104). 201115329 The test method method of the present invention further includes a method for reading and writing the bus interface interface on the host pci £ slot. The embodiment step of the test method is as shown in FIG. 2, and includes the following steps: scanning the host under test All slave devices are used to find the idle slave address (SlaveAddress) (step 201), which can be passed by the test application (Diag App) of the tested host through the input/output controller ^ ( The ICH) SMBus controller scans all the slave devices in the tested host; transmits the found free slave device address to the pc positive test fixture, and sets the pci£ test fixture to the slave (Slave) mode ( Step 2〇2), wherein the PCIE test fixture can be a Himalia fixture based on the Msp43(R) chip and the ρΕχ8632 wafer; reading data from the PC positive test fixture through the busbar on the host PCIE slot and The PCIE test fixture writes data (step 2〇3), wherein the bus line on the host pci£ slot can be an SMBus bus, and the host? The busbar on the slot can communicate with the PCIE test fixture through the SMBus controller to read data from the PCIE test fixture and write data to the pc test fixture; and determine the PCIE slot on the host. Whether the data read and write operations of the bus are correct (step 204) 'If yes, it means that the bus interface is normal, then the test ends; if no, it means that the bus interface is not normal, then the error is reported and the test is exited (step 205). 201115329 Please refer to "3rd" and "4th" now. "The test method for the bus interface on the host is the second test. The test fixture is connected with the _ _, "_" is the date of the issue. The block diagram of the PC test equipment used in the test method of the bus interface on the positive slot of the host PC is shown in the "Test Mode" of the present invention as shown in "Figure 3" and "Figure 4". _ POE is a Hlmalia fixture based on the Mex43Q wafer PEX8632 chip. Among them, the Cong% chip can be used as the core microcontroller unit (Core MCU), and the ΡΕΧ8632 chip can be used as the pc positive switch (PC positive) Switch ).
Himalia治具1〇與被測之主機2〇上的ραΕ插槽相連用以 檢測主機上的PQE簡之各觀號，啊包括對本發明中所 述的SMBus/IIC/IPMB匯流排進行測試。 被測主機20之測試應用程式⑽agApp)透過一輸入/輸出控 制器中心（I/O Controller Hub，簡稱ICH，係英代爾的南橋晶片系 列名稱，南橋晶片是主機板晶片組的重要組成部分，一般位於主 機板上離CPU插槽較遠的下方，PC正插槽的附近，負責連接1>(：：正 匯流排及I/O設備等）的SMBus控制器掃描被測主機20中所有的 從設備，即，主機20之測試應用程式先掃描目前有多少個從設備 之編號’再把空閒的編號指定給Himalia治具10，接著可進行資 料6買寫測试’其測試流程及細節屬於習知技術，在此不再贅述。 這裡還需要特別說明的一點就是主機20之測試應用程式與 Himalia治具1〇上的核心微控制器單元（即：MSP430晶片）之通 201115329 訊方法，測試應用程式係透過訪問主機2〇的pc正配置空間來操 作pc正開關（即：p·632晶片）的通用型輸入輪出（G_i Purpose I/O，簡稱Gpi〇)暫存器並利用ρΕχ驗晶片的側〇暫 存器來模擬串列周邊設備介面（Senal㈣⑹丨如略⑶，簡稱 ϋ)協定進而與核心微控制器單元進行通訊，即，向核心微控制 器皁π發送測試命令並讀取相應的測試結果。The Himalia fixture 1 is connected to the ραΕ slot on the host 2 被 tested to detect the PQE simplifications on the host, including testing the SMBus/IIC/IPMB busbars described in the present invention. The test application (10) agApp of the host 20 under test passes through an I/O Controller Hub (ICH), which is the name of the Southbridge chip series of the Indy, which is an important part of the motherboard chipset. Generally located on the motherboard below the CPU slot, near the PC positive slot, the SMBus controller responsible for connecting 1> (:: positive bus and I/O devices, etc.) scans all the tested host 20 The slave device, ie, the test application of the host 20, first scans how many slave devices are currently numbered and then assigns the free number to the Himalia fixture 10, and then can perform the data 6 buy and write test. The test flow and details belong to The conventional technology will not be described here. The point that needs to be specially explained here is that the test application of the host 20 and the core microcontroller unit on the Himalia fixture (ie: MSP430 chip) pass the 201115329 method. The application program accesses the PC-positive switch (ie, p. 632 chip) by using the pc positive configuration space of the host 2〇 (G_i Purpose I/O, Gpi for short) register. And use the side buffer of the chip to simulate the serial peripheral device interface (Senal (4) (6), such as abbreviated (3), referred to as ϋ) agreement and then communicate with the core microcontroller unit, that is, send test to the core microcontroller soap π Command and read the corresponding test results.
—雖然本侧赠述之較佳實施方式揭露如上，财並非用以 限疋本發明。本領域之麟人貞應當意識到在不麟本發明所附 之申請專利麵所揭示之本發明之細和精神之情況下，所為之 ，動”潤飾’均屬本發明之專利保護範圍之内。關於本發明所界 定之保護範圍請參考所附之申請專利範圍。 【圖式簡單說明】 '第1圖為本發明-實關之針對域PCIE^上匯流排介面 之測試方法的步驟流程圖； 第2圖為本發明另—實施例之針對主機pc正插槽上匯流排介 面之讀寫测試方法的步驟流程圖； 、、第3圖為本發明之針對主機PC正插槽上匯流排介面之測試方 '、^採用的PC正測試治具與被測主機之連接結構方塊圖；以及 、、第4圖騎發明之針對主機PC正制t上匯流排介面之測試方 法中所抹用的PC正測試治具之結構方塊圖。 【主要元件符號說明】 ⑺ Himalia治具 11 主機 201115329 20- Although the preferred embodiment of the present invention is disclosed above, it is not intended to limit the invention. It should be appreciated that in the context of the invention and the spirit and spirit of the invention disclosed in the appended claims, the invention is in the scope of the invention. Please refer to the attached patent application scope for the scope of protection defined by the present invention. [Simplified description of the drawing] 'The first figure is the flow chart of the steps of the test method for the bus interface of the domain PCIE^ according to the invention. 2 is a flow chart of steps of a read/write test method for a bus interface on a positive slot of a host PC according to another embodiment of the present invention; and FIG. 3 is a convergence of a positive slot on a host PC of the present invention; The test panel of the interface is used, and the PC used to test the connection between the fixture and the host under test is shown in the block diagram; and, in Figure 4, the invention is applied to the test method of the bus interface on the host PC. The PC used is the block diagram of the test fixture. [Key component symbol description] (7) Himalia fixture 11 host 201115329 20
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