201021190 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種可程式化陣列模組（programmable array module )。特定言之，本發明係關於一種多層疊設式 的可程式化陣列模組。 【先前技術】 g 隨著工業技術的高速發展，要求專用集成電路（ASIC) 的功能越來越強’功耗越來越低，生產周期越來越短，這 些都對晶片設計提出了巨大的挑戰。傳統的晶片設計方法 已經不再能適應複雜的應用需求。系統單晶片（System on a Chip, SoC)以其高集成度，低功耗等優點應運而生，並 越來越受歡迎。 除了現有的集成電路處理器（IC microprocessors)之 ❿ 外，目前市面上還有另一種處理元件（processing element)，此等處理元件具有可重整組態（reconfigurable) 之特性。此等具有可重整組態特性之處理元件相較於現有 的集成電路處理器，在許多方面展現出多樣化的彈性與優 點。此等具有可重整組態特性之處理元件，一般稱之為可 程式化邏輯閘陣列（field programmable gate array, FPGA)。 可程式化邏輯閘陣列是一種可以重複改變組態的電 5 201021190 路。這種可隨使用者的需求任意進行編程的邏輯閉元件， 特細於產品開發時必須不斷變更設計的=L 力速產。口上市時間。可程式化邏輯閘陣列的邏輯閘特性， 可依設計者的需要加以改變，並提供各種基本功能。今日 傳統的集成電路處理器晶片多半是由多層電路所構成而 每層電路都需要獨立設計並製賴對應製程步驟的光罩。 ❹ 一般而言’每枚晶片必須要建立錄光罩，然後使用在晶 圓加工的過程中，來完成完整的晶片。 過去在專用集成電路作法上，是每層電路都要開設光 罩。眾所週知，光罩的設計與製造成本極為可觀。現在大 宗的晶片趨勢已不再是傳統的資訊市場，反而是在變動快 速、少量多樣的消費性電子市場，晶片不僅必須快速、及 時上市’還必須能快速修改變更以因應市場變化。但是很 不幸的，傳統的集成電路處理器的電路設計受限於預定好 ❹ 的光罩，修改不僅耗費高昂成本，同時速度緩不濟急。可 程式化邏輯閘陣列的優點是極有彈性，像可以不斷重新拆 解組合（reconfigurable)的字母（letters)，隨時因應不同 的應用而重整可程式化邏輯閘陣列的邏輯組態。大多數電 路固定的邏輯晶片和微處理器無法重新設計’但可程式化 邏輯閘陣列具有可程式的特性，設計者可藉改變電晶體的 開關來重畫電路。 201021190 然而，可程式化邏輯閘陣列本身也有一個十分嚴重的缺 陷，那就是對製造過程中無可避免會產生的瑕疵元件的容 忍度非常低。相較於隨機存取記憶體（random access memory)可以藉由冗餘電路（redundancy)來替代任何有 瑕疵的元件以維持整體的運作正常，對於一個n*n單元排 列的可程式化邏輯閘陣列而言，只要其中任何一個單元有 瑕疵，整個可程式化邏輯閘陣列即會被宣告無法正常運 ❹作。有鑒於此，可程式化邏輯閘陣列的良率一直以來被視 為不可接受的低，生產成本也因為良率一直過低而水漲船 尚。 所以，急需要一種新穎的可程式化陣列模組。在實際地 考量到可程式化邏輯閘陣列的生產過程一定會出現固定比 例的瑕疵元件下，仍然能戲劇性的提升可程式化陣列模組 整體的良率，有效地降低生產成本以維持最高的產業競爭 〇 力。 【發明内容】 本發明於是提出-種新穎的可程式化陣列模組。在實際 地考量到可程式化邏輯閘陣列的生產過程一定會出現固定τ' 比例的瑕疵元件下，本發明的新穎可程式化陣列模組仍然 能無懼於可程式化邏輯閘陣列中有瑕疵的單元於是有效 地提升可程式化陣列模組整體的良率，並降低生產2本以 201021190 維持最同的產業競爭力。此外，本發明的卿、可程式化陣 歹J模組的3 g優點是，可以在有限的晶片面積下盡量容 納最多的可程式化邏輯閘陣列，如此—來就可以盡量放大 本發明的新穎可程式化陣列模組的運算能力，—直到接近 最佳化。 本發明所提出—種可程式化陣列模組，其包含基礎電路 Q ( base元件與複數個核心電路（core circuit)元件。 基礎電路7L件包含一介面電路。介面電路另與一電腦系統 電連接。複數個核心電路元件係疊設於基礎電路元件上並 與基礎電路元件電連接。核心電路係由矩陣形式排列之複 數個金氧半導體與電連接複數個金氧半導體之金屬内連線 電路所組成。 〇 本發明其:欠提I種可程式化陣賴組，其包含一基礎 電路元件與魏個㈣轉元件。減轉元件包含記憶 晶胞、處理器、控制電路與介面電路。而複數個核心電路 心牛，則疊設於誠電路元件上料麵電路以牛電連 =核心電路係由矩陣形式排列之複數個金氧半導體與電 連接複數個金氧半導體之金屬_線電路所組成。 本發明又提出-種可程式㈣龍組，其包含基礎電路 凡件與複數層元件可程式化邏輯間陣列。基礎電路元件， 201021190 U 3 Μ面電路。複數層元件可程式化邏㈣陣列，則疊 設於频電路树上並與細電路元件電連接。 【實施方式】 本發明在於提供-種新賴的可程式化陣列模組。將複數 健包含金氧半導體與金屬内連線電路之核心電路元件叠 於基礎電路元件上並與此基礎電路元件電連接，可以 ❹使得在可程式化邏輯閘陣列的生產過程中一定會產生的瑕 藏元件不再干擾整個可程式化邏輯閘陣列的正常運作。於 是可以有效地提升可程式化陣列模組整體的良率，並降低 生產成本以維持最高的產業競爭力。此外，本發明將複數 個核心電路元件疊設於一基礎電路元件上並與此基礎電路 兀件電連接的另-項優點是，可以在有限的晶片面積下盡 量容納最多層的可程式化邏輯閘陣列，來盡量放大本發明 的新賴可程式化陣列模組的運算能力，到接近最佳化。 ❹ 第1圖例示本發明所提供之一種可程式化陣列模組一較 佳實施例之示意圖。本發明之可程式化陣列模組100，包 含兩個部份’即第一部份之基礎電路（base circuit)元件 與第二部份之複數個核心電路（core circuit)元件12〇。 複數個堆疊層的核心電路元件120係疊設於一基礎電路元 件110上並與此基礎電路元件110電連接，而形成本發明 之可程式化陣列模組1〇〇。 201021190 在本發明之實施態樣中，基礎電路元件110會包含一介 面電路111。而記憶晶胞112與處理器113則可以為内建 (internal)或是外接（external)。例如第1圖所示，記憶 晶胞112與處理器113為内建者，基礎電路元件會同 時包含介面電路111、記憶晶胞Π2與處理器113。 ❺第2圖例示本發明之基礎電路元件11〇另一較佳實施態 樣之示意圖。若是記憶晶胞112與處理器113為外接者， 則介面電路111又會另外與一外接之電腦系統13〇電連 接。電腦系統130可以直接位於基礎電路元件no之下方， 而係電腦元件。電腦系統13〇即包含記憶晶胞112與處理 器113。但無論是以上的何種實施態樣，本發明之基礎電 路元件110都不會包含有可程式化邏輯閘陣列。 G 還有，本發明之基礎電路元件110還可以進一步包含控 制電路114 ’控制電路114則包含一邏輯電路115。換句話 說’本發明之基礎電路元件110可以包含介面電路m、記 憶晶胞112、處理器in與包含一邏輯電路ns之控制電路 114。 叠設於基礎電路元件11〇上之複數個核心電路元件12〇 通常以多層的形式表現，層與層之間亦相互電連接。本發 201021190 明之核心電路元件120具體言之，即可為可程式化邏輯開 陣列⑵。第3圖例示本發明單層之可程式化邏輯間陣列 之示意圖。此等可程式化邏輯間陣列121通常即由矩陣形 式排列之複數個金氧半導體122與接錢個金氧半導 體122之金屬内連線電路123所組成。複數個金氧半導體 122即扮演可程式化邏輯閘陣歹〇21中之關鍵元件一邏輯 閘之角色，又藉由金屬内連線電路123而彼此導通。 ❹ 此外，本發明疊設於基礎電路元件11〇上之複數個核心 電路70件120更可以有多種之實施態樣。例如，多層的核 心電路元件120，每一層可以具有相同的形狀，如第i圖 所示，於是均具有相同之面積。或者是，如第4圖所例示 本發明複數個核心電路元件堆疊之實施態樣，複數個核心 電路元件120之面積不同。於此實施態樣中，堆疊之複數 個核心電路元件120之面積可以由下而上漸減，類似於金 © 字塔之結構。然後相同或不同面積之複數個核心電路元件 120再藉由打線、覆晶(Flip Chip)、球柵陣列(BGA)、矽穿 孑L (through-silicon via, TSV)等技術來彼此電連接。 值得注意的是，本發明多層的核心電路元件120之單一 各層，不需為一片完整的可程式化邏輯閘陣列晶片’而可 以由一完整的晶片切割得來。切割的方式可以依據不同的 需求而有所變化。因此，可以藉由特殊的裁切方式來剔除 11 201021190 晶片中的瑕疲元件的部份而成一非吿I丨4 式規格之陣列纽合。 例如，一片12*12的完整晶片，可以士 ° ^有 7*5、6*6、4*4、 3*3 、 2*2 、 1*1 、 6*4 、 6*3 、 6*2 、 4*3 > 4*2 '4*1' 3*2、3*1、2*1等等多種的裁切尺寸，、 ’進而再選取堪用之 可程式化邏輯閘陣列晶片來堆疊組入士 < t Q成所需邏輯閘數的可 程式化陣列模組。適^的裁切尺寸可c 一 1、 』U順利剔除晶片中的 瑕疵》元件又同時追求晶片的最大可用t J用面積。此外，由於核 ❹ 心電路元件120單一各層之面積雖然減小，曰 / 用堆疊的方式來增加總面積’亦即邏輯閘數增=發：: 以在不增加可程式㈣顺組面積之條件下，卻又得到效 能更佳的可程式化陣列模組。 本發明的新顆可程式化陣列模組中，將複數個分別僅包 含金氧半導體與金屬内連線電路之核心電路元件叠設於基 礎電路70件上並與基礎電路元件電連接，而基礎電路元件 ❿則同時包含介面電路、記憶晶胞或處理器等。這樣的安排， 可以使得在可程式化邏輯閘陣列的生產過程卜定會產生 的瑕窥元件被適當剔除而不再影響整個可程式化邏輯閉陣 列的正常運作，於是有效地提升可程式化陣列模組整體的 良率，並降低生產成本以维持最高的產業競爭力。此外， 本發明的新穎可程式化陣列模組的還有一項優點，就是可 以在有限的曰曰片面積下盡量容納最多的可程式化邏輯間陣 列’來盡量放大本發明的新賴可程式化陣列模組的運算能 12 201021190 力到接近最佳化。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖例示本發明所提供之一種可程式化陣列模 較佳實施例之示意圖， 、 第2圖例示本發明之基礎電路元件一較佳實施 組 不意圖 態樣之 圖 第3圖例示本發明單層之可程式化邏輯間陣列之示 意 樣 第4圖例林發明複數個核^電路元件堆疊之實施熊 G 【主要元件符號說明】 110基礎電路元件 112記憶晶胞 114控制電路 120核心電路元件 122金氧半導體 130電腦系統 可程式化陣列模組 111介面電路 113處理器 115邏輯電路 121可程式化邏輯閘陣列 123金屬内連線電路 13201021190 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a programmable array module. In particular, the present invention relates to a multi-layer programmable programmable array module. [Prior Art] g With the rapid development of industrial technology, the functions of application-specific integrated circuits (ASICs) are becoming more and more powerful. 'The power consumption is getting lower and lower, and the production cycle is getting shorter and shorter. These are huge for the chip design. challenge. Traditional wafer design methods are no longer able to accommodate complex application needs. System on a Chip (SoC) has emerged with its high integration and low power consumption, and is becoming more and more popular. In addition to the existing integrated circuit processors (IC microprocessors), there is another processing element on the market that has reconfigurable characteristics. These processing elements with reconfigurable configuration characteristics exhibit diverse flexibility and advantages in many respects compared to existing integrated circuit processors. These processing elements with reconfigurable configuration characteristics are generally referred to as field programmable gate arrays (FPGAs). The programmable logic gate array is a type of circuit that can be repeatedly changed in configuration. This kind of logic closed component that can be arbitrarily programmed according to the user's needs, must be constantly changed in the product development time to change the design's speed. Time to market. The logic gate characteristics of the programmable logic gate array can be changed according to the designer's needs and provide various basic functions. Today, traditional integrated circuit processor chips are mostly composed of multi-layer circuits, and each layer of circuit needs to be independently designed and relied on the mask for the corresponding process steps. ❹ In general, each wafer must be built with a hood and then used in the process of wafer processing to complete the wafer. In the past, in the ASIC practice, a mask was built for each layer of circuitry. As is well known, the design and manufacturing cost of the reticle is extremely impressive. Nowadays, the trend of large-scale chips is no longer the traditional information market. Instead, in the fast-changing and small-volume consumer electronics market, chips must not only be quickly and timely listed, but must also be able to quickly modify changes to respond to market changes. However, unfortunately, the circuit design of the conventional integrated circuit processor is limited by the predetermined mask, and the modification is not only costly but also inconvenient. The advantage of a programmable logic gate array is that it is extremely flexible, like the ability to constantly reassemble the reconfigurable letters, and to reconfigure the logical configuration of the programmable logic gate array at any time depending on the application. Most circuit-fixed logic chips and microprocessors cannot be redesigned', but programmable logic gate arrays have programmable features, and designers can redraw the circuit by changing the transistor's switches. 201021190 However, the programmable logic gate array itself has a very serious drawback, that is, the tolerance of the germanium components that are inevitably generated during the manufacturing process is very low. Compared to random access memory, any defective component can be replaced by a redundant circuit to maintain the overall operation. A programmable logic gate array for an n*n cell arrangement. In any case, as long as any one of the units is defective, the entire programmable logic gate array will be declared unusable. In view of this, the yield of programmable logic gate arrays has long been regarded as unacceptably low, and production costs have also risen due to low yields. Therefore, there is an urgent need for a novel programmable array module. In the actual consideration of the production process of programmable logic gate arrays, there will be a fixed proportion of germanium components, which can still dramatically increase the overall yield of programmable array modules and effectively reduce production costs to maintain the highest industry. Competitive power. SUMMARY OF THE INVENTION The present invention thus proposes a novel programmable array module. Under the consideration of the fact that the production process of the programmable logic gate array must have a fixed τ' ratio of the germanium component, the novel programmable array module of the present invention can still be fearless in the programmable logic gate array. The unit thus effectively improves the overall yield of the programmable array module and reduces the production of 2 copies to maintain the same industry competitiveness with 201021190. In addition, the 3 g advantage of the singular and programmable J-module J module of the present invention is that it can accommodate as many programmable clock gate arrays as possible in a limited wafer area, so that the novelty of the present invention can be maximized. The computing power of the programmable array module - until near optimization. The present invention provides a programmable array module comprising a base circuit Q (a base element and a plurality of core circuit elements. The base circuit 7L comprises an interface circuit. The interface circuit is further electrically connected to a computer system The plurality of core circuit components are stacked on the basic circuit component and electrically connected to the basic circuit component. The core circuit is a plurality of metal oxide semiconductors arranged in a matrix form and a metal interconnection circuit electrically connected to the plurality of metal oxide semiconductors. The invention is characterized in that: a type of programmable array is not mentioned, which comprises a basic circuit component and a Wei (four) rotation component. The rotation reduction component comprises a memory cell, a processor, a control circuit and an interface circuit. The core circuit is built on the circuit components of the circuit. The circuit is composed of a plurality of MOS circuits arranged in a matrix form and a metal _ line circuit electrically connected to a plurality of MOS circuits. The invention further proposes a programmable (four) dragon group, which comprises an array of basic circuit components and a plurality of layer elements programmable logic. Basic circuit components , 201021190 U 3 kneading circuit. The complex layer element can be programmed into a logic (four) array, which is superimposed on the frequency circuit tree and electrically connected to the fine circuit element. [Embodiment] The present invention provides a new type of programmable The array module stacks the core circuit components of the MOS and the metal interconnect circuit on the basic circuit component and is electrically connected to the basic circuit component, so that the process can be performed in the process of the programmable logic gate array The hidden components that must be generated no longer interfere with the normal operation of the entire programmable logic gate array, thus effectively improving the overall yield of the programmable array module and reducing production costs to maintain the highest industrial competitiveness. Another advantage of the present invention for stacking a plurality of core circuit components on a basic circuit component and electrically connecting to the basic circuit component is that the maximum number of programmable logic gates can be accommodated as much as possible under a limited wafer area. The array is used to maximize the computing power of the new Lazy programmable array module of the present invention to near optimization. ❹ Figure 1 illustrates the present invention. A schematic diagram of a preferred embodiment of a programmable array module provided by the present invention. The programmable array module 100 of the present invention comprises two parts, namely a first part of a base circuit component and a first a plurality of core circuit components 12. A plurality of stacked core circuit components 120 are stacked on a base circuit component 110 and electrically coupled to the base circuit component 110 to form the present invention. The programmable circuit module 1 is used in the embodiment of the present invention. The basic circuit component 110 includes an interface circuit 111. The memory cell 112 and the processor 113 can be internal or Externally, for example, as shown in FIG. 1, the memory cell 112 and the processor 113 are built-in, and the basic circuit component includes the interface circuit 111, the memory cell 2, and the processor 113. Fig. 2 is a view showing another preferred embodiment of the basic circuit component 11 of the present invention. If the memory cell 112 and the processor 113 are external, the interface circuit 111 is additionally electrically connected to an external computer system 13A. The computer system 130 can be located directly below the base circuit component no, but is a computer component. The computer system 13 includes a memory cell 112 and a processor 113. However, in any of the above embodiments, the basic circuit component 110 of the present invention does not include a programmable logic gate array. Further, the basic circuit component 110 of the present invention may further include a control circuit 114'. The control circuit 114 includes a logic circuit 115. In other words, the basic circuit component 110 of the present invention can include an interface circuit m, a memory cell 112, a processor in and a control circuit 114 including a logic circuit ns. The plurality of core circuit elements 12 叠 stacked on the base circuit component 11 are typically represented in multiple layers, and the layers are also electrically connected to each other. In particular, the core circuit component 120 of the present invention 201021190 can be an array (2) for programmable logic. Figure 3 illustrates a schematic diagram of a programmable inter-logic array of single layers of the present invention. The programmable inter-logic arrays 121 are typically comprised of a plurality of MOS semiconductors arranged in a matrix and a metal interconnect circuit 123 that receives a MOS transistor 122. A plurality of MOS semiconductors 122 play the role of a key component in the programmable logic gate 歹〇 21, and are also electrically connected to each other by a metal interconnect circuit 123. In addition, the plurality of core circuits 70 of the present invention stacked on the base circuit component 11 can have a plurality of implementations. For example, the multi-layered core circuit elements 120, each of which may have the same shape, as shown in Figure i, then have the same area. Alternatively, as shown in Fig. 4, the implementation of the plurality of core circuit component stacks of the present invention differs in the area of the plurality of core circuit components 120. In this embodiment, the area of the plurality of stacked core circuit elements 120 can be reduced from bottom to top, similar to the structure of a gold © word tower. The plurality of core circuit elements 120 of the same or different areas are then electrically connected to each other by techniques such as wire bonding, flip chip, ball grid array (BGA), through-silicon via (TSV), and the like. It should be noted that the single layers of the multi-layer core circuit component 120 of the present invention can be cut from a complete wafer without the need for a complete programmable logic gate array wafer. The way of cutting can vary depending on the needs. Therefore, it is possible to eliminate the portion of the fatigue component in the 201021190 wafer by a special cutting method to form an array of non-吿I丨4 specifications. For example, a complete 12*12 wafer can be 7*5, 6*6, 4*4, 3*3, 2*2, 1*1, 6*4, 6*3, 6*2 4*3 > 4*2 '4*1' 3*2, 3*1, 2*1 and many other cutting sizes, 'and then select the programmable logic gate array wafers to stack A group of programmable logic modules that are set to ± t Q into the required number of logic gates. The appropriate cutting size can be c1, "U smoothly removes the 瑕疵" component in the wafer and at the same time pursues the maximum usable area of the wafer. In addition, since the area of the single layer of the core unit circuit component 120 is reduced, the total area is increased by the stacking method, that is, the number of logic gates is increased by =: to increase the programmable (four) grouping area. Then, get a more efficient programmable array module. In the new programmable array module of the present invention, a plurality of core circuit components respectively including only a metal oxide semiconductor and a metal interconnect circuit are stacked on the basic circuit 70 and electrically connected to the basic circuit component, and the basis is The circuit component includes both an interface circuit, a memory cell, or a processor. Such an arrangement can make the peek elements generated in the production process of the programmable logic gate array be properly rejected without affecting the normal operation of the entire programmable logic closed array, thus effectively improving the programmable array. The overall yield of the module and the reduction of production costs to maintain the highest industrial competitiveness. In addition, another advantage of the novel programmable array module of the present invention is that it can accommodate the most programmable logic arrays as much as possible under a limited chip area to maximize the new program of the present invention. The operational power of the array module is 12 201021190 and the force is nearly optimized. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a preferred embodiment of a programmable array module according to the present invention, and FIG. 2 is a schematic view showing a preferred embodiment of the basic circuit component of the present invention. Fig. 3 is a view showing a schematic diagram of a programmable logic array of a single layer of the present invention. Fig. 4 is an embodiment of a plurality of core circuit component stacks. [Gear of main component symbols] 110 basic circuit component 112 memory cell 114 control Circuit 120 core circuit component 122 MOS semiconductor 130 computer system programmable array module 111 interface circuit 113 processor 115 logic circuit 121 programmable logic gate array 123 metal interconnect circuit 13