TW200949690A - Processor and early execution method of data load thereof - Google Patents

Abstract

A processor and an early execution method of data load thereof are provided. The early execution method fetch and pre-estimation an instruction for obtaining the estimation result in the instruction fetch stage. According to the estimation result, determine to be early loaded the pre-fetch data with corresponding the instruction. The target data is fetched according to the instruction in the instruction execution stage if the pre-fetch data have not been written into correctly. If the pre-fetch data have been written into correctly, has regarded the pre-fetch data as the target data.

Description

200949690 r^.ui//ixuuJ 27005twf.doc/n IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a processor, and more particularly to a pipeline processor. [Prior Art] FIG. 1 is a diagram illustrating a conventional pipelined processor. The conventional processor in Figure 1 only depicts the pipeline 100. The pipeline 100 has an instruction fetch stage 110, an instruction queue 120, an instruction decode stage 130, an instruction execution stage 140, and a data write-back level (data). Write-back stage) 150. In the conventional processor design, between the instruction fetch stage 110 and the instruction decode stage 130, the two stages 110 and 130 are separated by the instruction queue 120, thereby reducing the issue rate and the FetchRate instability to cause processor performance. loss. Therefore, most instructions will not enter the instruction decode stage 13 after being fetched into the processor. It will wait for a while in the instruction queue 12〇. The instruction fetch stage 11 extracts the instruction from the instruction cache (or from the main memory) and sends the instruction to the instruction file 120. The order 12Q is stored in the first-in first-out (FIFO) principle to extract the instruction extracted by the instruction level, and the instruction is sequentially supplied to the instruction decoding stage 130. First, the processor needs to decode the "instruction code" by the instruction decode stage 130 before executing the instruction. The instruction to complete the decoding is transmitted to the execution level 140. The instruction execution level 14〇 includes an arithmetic logic unit (ALU), which can be decoded according to the instruction level 5

200949690 Executes the instruction operation with the decoding result of wmw3 27005twf.d〇c/n 130. If the f-order operation performed by the instruction execution stage produces an operation result, the data write-back stage 150 is responsible for writing the result of the operation back to the data cache (or the main memory). In the traditional processor design, the delay of data loading _ will increase with the increase of the depth of the tube. The delay of loading_usage will seriously affect the performance of the processing state. For example, observe the following command string: LOAD Rm> [mem addr] ADD Rd, Rn, Rm will sequentially extract the upper command from the instruction memory and store it in the instruction queue 120. After the instruction is executed, the instruction execution level (10) will execute first: data 曰 饤 饤 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 This = the resuming action will be completed at the instruction execution level (10)' requires η clocks to complete the above L_ instruction, 1〇===) must wait for the depth of the n-line clock lines (levels) [Invention] The invention proposes a process of extracting and judging - instruction \ method in the process of processing 5|. This method extracts the judgment result in the instruction. According to the judgment -3 27005twf.doc/n 200949690, the decision is to compare the early manned instructions. If the preloaded data has been loaded correctly, the preloaded data is used as the target data. In an embodiment of the invention, if the preloaded data is not correctly loaded, the target data is extracted at the instruction execution level in accordance with the instruction. ❹ ❹ The present invention proposes a processor, including an instruction fetch stage, an instruction decode 2, an instruction execution stage, and an early manned (four) b instruction fetch stage for providing an instruction 'where the instruction fetch stage includes a pre-decoding unit, and more The instruction β takes the pre-emptive order and turns the result. The instruction decode stage ίίϊ instruction extracts the m decoding instruction and converts the decoding result. Refers to the second execution level=to the instruction decoding level'. (4) The finger is executed according to the decoding result. The early carrier is connected to the pre-decoding unit to determine whether to preload the preloaded data corresponding to the instruction according to the foregoing. Where =4 is not loaded correctly' then the instruction execution level is based on the instruction. If the pre-loaded data has been correctly loaded, it should be loaded into the child 1 early, and the pre-loaded data will be used as the target data. $Invention--implementation, if the result indicates that the instruction is of the type 'and the register state of the register corresponding to the instruction in the register status table', the preloaded data corresponding to the instruction is loaded into the early r Column fit Ming - the implementation of the towel, in the command of the deliberation check early loading 32 = is money and legal. If the data is loaded early, the destination register address specified by the instruction is changed to the address of the preloaded data in the queue. 200949690 /1 ivuj 27005twf.doc/n The present invention uses the instruction to fetch the waiting time into the sequence of the instruction j, and preloads the preloaded data corresponding to the instruction, so that the deep official line processor design can be solved. , loading _ use delay is too long. The above described features and advantages of the present invention will become more apparent from the following description. [Embodiment] FIG. 2 is a flow chart showing a preloading method of a processor according to an embodiment of the invention. When the instruction fetch stage fetch instruction, the instruction fetch stage prejudges the instruction to obtain the judgment result (step S21). Based on the result of the judgment, the processor can decide whether to preload the preloaded data corresponding to the instruction (step S220). If the preloaded data is not loaded correctly, the instruction execution stage extracts the target data according to the instruction (step S23). If the preloaded data has been correctly loaded, the processor uses the preloaded data as the target data (step S240). Those skilled in the art to which the invention pertains may modify the above-described embodiments in any manner, depending on the needs thereof. For example, Figure 3A is a flow chart illustrating a method of preloading a processor in accordance with another embodiment of the present invention. Compared with the previous embodiment, the present embodiment further performs a judging step between steps S210 and S220 (step S310). Please refer to FIG. 3A. In step S21, the instruction fetch stage fetches the instruction from the instruction memory (or instruction fetch) and prejudges (or pre-decodes) the instruction. Therefore, before the instruction enters the instruction queue, step S210 can discriminate early that the instruction does not need to extract data from the data cache (or data memory). 27005twf.doc/n 200949690 JL Z. W / l± X/V/3 According to the judgment result of step S210, 'Step S310 determines whether to store the instruction into the early-load queue (ELQ). . If the instruction does not belong to the target type (e.g., does not need to extract data from the data cache), then only the instructions are stored in the instruction queue (the instructions are not stored in the early loading queue). Therefore, the instruction is executed by the instruction decode stage and the instruction execmi〇n stage (step S320). Of course, if the instruction does not belong to the target type, but still needs to extract data from the data cache, in step S320, the instruction execution level will extract data from the data cache according to the instruction. Step S310 may also decide to put the instruction into the early loading queue and the command queue according to the judgment result. If the instruction is placed in the early loading queue in step S31, step S220 checks whether the state of the register specified by the register status table is ready, and then the preloaded data corresponding to the instruction. Load from the data cache to the early loading queue. Therefore, it can be executed before the instruction execution level (the instruction is still waiting to be executed in the instruction queue). The instruction is executed from the early loader column to load the corresponding preloaded material, and then the preloaded data is put into the early stage. In addition, after the instruction stored in the instruction queue has passed the waiting time, the implementation will be decoded (4) in the decoding of the instruction. According to the decoding result, the processor checks the temporary H. The county 'off' is expected to be loaded correctly before loading = two if the pre-requisite is not correctly loaded, the instruction is executed to go to the data cache to extract the target data (step S230). t 200949690 r 厶, i jl Vv3 27005twf.doc/n has been correctly loaded, then the processor uses the preloaded data as the target data (step S24G), and the instruction execution level does not need to spend the amount (4) depending on the data cache to extract the target data. Those who have the usual knowledge can set the invalidation mechanism (invalidati〇n mechanism) by any means in the above embodiments according to their needs in order to prevent the above-mentioned early manned operation from accessing the wrong data. For example, in the instruction solution Level if the second instruction (instruction refers to any) is

❹ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Then search for all the records of the early manned system. If there are two records in the early manned queue pointing to the destination register specified by the second instruction, the record is set to be invalid (not legal). Therefore, you can avoid data dependency Dependency errors. Jiang Ci 2, such as "At the instruction execution level, if there are f two instructions (referred to as any instruction), a certain address of the human memory, the job seeks to preload the person. If the certificate is the same as the one specified in the second instruction, then the singularity is invalid (not legal). This is a memory dependency error. Avoid the occurrence of the step 'With the premise T of setting the invalid_, the above c may include the following operations. At the instruction level, if the inspection data is ready and legal, the address specified in the instruction is changed to the address of the preloaded data in the early loading column. Benefits 200949690 Those skilled in the art having the knowledge of the present invention can implement the above-described embodiments in conjunction with the design of any pipelined processor. For example, Figure 3B illustrates a pipelined processor in accordance with an embodiment of the present invention. The processor shown in Figure 3B depicts only the pipeline 300. Pipeline 300 has an instruction fetch stage 310, an instruction queue 320, an instruction decode stage 330, an instruction execution stage 340, and a data write-back level (data ❹). Wrlte-back stage) 350. The instruction fetch stage 31 and the instruction decode stage 330 are configured with an instruction queue 320, thereby reducing the issue rate and the Fetch Rate (fetch) into the processor, and then entering the processor is unstable and causing processor performance. loss. The instruction fetch stage 31 fetches instructions from the instruction cache (or from the main memory). The instruction will enter the instruction decode stage 33〇 after being fetched. The instruction queue 32 stores the instructions fetched by the instruction fetch stage 31 in a first in first out (FIF0) principle, and sequentially supplies the instructions to the instruction decode stage 330. Need to use the aunt __ before executing the instruction

It will first wait for a period of time in the command queue 320 200949690 χ -i-ww/ ijiuv3 27005twf.doc/n to perform the operation in eight according to the decoding result of the instruction decoding stage 330. If the instruction operation executed by the instruction execution stage 340 generates a transport = result ', then the data write back stage 350 is responsible for writing the result of the operation; the data memory (or the main memory).

In the present embodiment, the instruction fetch stage 310 includes an extracting unit 311 and a pre-decoding unit 312. The extracting unit 3n extracts an instruction from the instruction memory (or from the main memory). The pre-decoding unit 312 preliminarily determines the instruction extracted by the extracting unit 311 to obtain a judgment result. The official line 300 has an early loading queue (eariy seven ad jobs (four). For the instruction stream, the early loading queue 36 can be a small table parallel to the command queue 320. Loading the queue 36提 early To the f element 312. The pre-decoding unit 312 determines, according to its judgment node*, that the instruction is written into the preloading queue 360. In another embodiment, the result of the determination may be determined by the loading column 360. Determining whether to record the fingerprint. In this embodiment, if the result of the determination indicates that the instruction extracted by the extracting unit 3n belongs to the target type (for example, LDR, LDRB, etc., the data is loaded into the command surface of the temporary $), then the pre-decoding unit 312 (4) When the instruction is written to: • column 320 and the early loading queue 36. Conversely, if the instruction extracted by the judgment result table taking unit 311 does not belong to the target type, the pre-solution ^ early το M2 will only command Write the command column no, not write the battle queue 360. According to the _ result of the 码 code unit ,, the moment can decide: ^, so that the corresponding preloaded data is captured to the early carrier list The fine right preloaded data was not correctly captured to the early loading list 36〇 Then 12 200949690 rs,w/ nw3 27005twf.d〇c/n The instruction level 340 extracts the data according to the instruction (herein referred to as the target data). The right job (4) has been correctly captured to the early loading 360'=Processing the information stored in the early stage (4) as the target poor material. Take the LDR instruction as an example, the instruction is still in the order of 32〇$waiting period. 'Processing H can prematurely invalidate the LDR instruction. The poor material of the site (herein referred to as preloaded data) is captured into the early loading symbol. Therefore, when the LDR instruction enters the instruction execution level 34, it can be used to load the baby, J 360 The data is preloaded without going to the data cache memory (or the main memory) to capture the target data. The above operation of loading the data early can be implemented in any manner. For example, the embodiment shown in FIG. 3B is used early. The loading unit 370 performs the operation of loading the data early. The early loading queue 360 retains the instruction provided by the extracting unit 311, and requests the early loading unit 37 to extract the target data. The early loading of the queue 360 can refer to the table. The data structure shown in 1 is implemented. The 'status field State[l:0] in 1 is used to record the status of each entry/instruction in the preloaded queue 360, for example, 〇〇 indicates invalid (Invalld), 01 indicates busy (Busy), 10 Indicates that Ready and 11 indicate Usage. The program count field PC[l:〇] is used to record the contents of the program counter (pr〇gram c〇unter) of the record/instruction, that is, the instruction. The address of the scratchpad information fields Base_ID[3:0] and 〇ffset[ii:〇] are used to record the destination register address (base value and offset value) of the instruction to store data. The interceptor Adr_mode[l:0] is used to record the addressing mode of the instruction, such as pre-index, post-index, auto-index, and so on. The memory address field Adr[31:0] is used to record the 13 200949690 i 2 v/v / Nong 27005twf.doc/n command memory address to be loaded into the data 指令 command extraction level 310 pre-decoding unit of the towel Fff and decode the base temporary index II index of the instruction, the offset value _et), and the addressing mode. If the instruction has the address form of -..., then the age will be pre-loaded into the SIS early loading list (10). Table 1 I is loaded into the data structure of the child column 360 Statpri m orr- Ji-m n— I ~:-—~ —

The early loading unit 370 is coupled to the early loading queue 36〇. When the load unit 370 is advanced, the early load queue 360 will select the instruction that was originally registered in it and send the instruction to the soap loading unit 370 for execution. Therefore, before the instruction (eg, LDR instruction) enters the instruction execution stage 340 (also in the instruction queue 320), the instruction is executed early by the early loading unit 370 and the preloaded data corresponding to the instruction is placed into the early stage. Load the preloaded data block of the queue 360 in Loaded__data. Figure 3B depicts the early loading unit 370 as a dedicated circuit within the processor', a detailed embodiment of which will be described in detail later. However, this example only describes the implementation of the early loading unit 370 in an intuitive manner and should not be limited to this. 14 200949690 J. / Jl i. w3 27005twf.doc/n Its implementation. For example, a person skilled in the art to which the present invention pertains can use the conventional loading/storing unit (not shown) in the execution stage 34 to implement the function of loading the single 7〇370 early, that is, to load the unit early and The load/store unit in the command execution level shares its hardware. In this embodiment, the second early load unit 37G includes a register read unit 371, an address generation early 372, and a data extracting unit 373. The scratchpad reading unit π ❹ 2 checks whether there is a need to store the data in the early loading queue 360, and then reads the base temporary storage from the temporary storage queue (not shown) in the processing H. The device is used to pass the instruction to the address generation unit = 2 address generation unit 372 is responsible for generating an address for extracting data according to the instruction and its base temporary storage device: the data extraction unit 373 According to the address generation generated by the generating unit 372, the data cache memory (or the main memory) is loaded early, and the preloaded data is written back into the queue 360. The θ private decoding stage 33 can be checked. Is it ready to load the data in queue 360 early? And legally. When the instruction has been sent from the command line 320 to the instruction level 330', the decoding stage 330 checks the status of the pre-loaded queue 360. If it is loaded earlier, it is loaded into the ranking 360. The information is ready and the address of the destination temporary address specified by the legal S' 'ride order is changed to the address of the preloaded data in the first column of 360. Therefore, the instruction no longer needs to be fast. Extracting the data 'or it can be said that the instruction execution stage 340 does not have to execute the instruction again. Therefore, the instruction that depends on the same destination register can then obtain the required resources from the early loading queue 360. 15 200949690 nwJ 27005twf. doc/π ϊ 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现 现All the internal memory of the processor, if the instruction fetch stage 310 determines that the = 22 type (such as the LDR instruction or the LDRB instruction), and the record according to the temporary = (10) indicates the register specified by the instruction. The state is the prepared j state, then the instruction is to be extracted. The data is preloaded into the list 360. The register status table 380 can be implemented by referring to the data t shown in Table 2. In Table 2, the 'storage field record records the internal registers of the processor. The status block State[l:0] is used to record the status information of each register. For example, 00 means Ready, 〇1 means Forwarding, 1〇 means Renaming, u means Busy. (Busy). The field address field ELQjd[2:〇] is used to record the address whose own register is renamed to the early loading queue 360. Data structure of the register status table 380

The instruction decode stage 330 is responsible for decoding the instruction and checking the scratchpad status table 380' based on the decoded result to determine if the preloaded data required by the instruction was correctly loaded into the early loading queue 360. Finally, the instruction decode stage 330 transmits the decoded instruction to the instruction execution stage 340 in accordance with the foregoing checks and processing results. 200949690 rz.w/ ιχν/ui 27005twf.doc/n Table 3 is a table showing the processing timing of each instruction in the pipeline using the above-mentioned preload method block as an example. Table = 仃, 二明 The processor does not use the preload method and performs phase 3 with the table == say the processing schedule of each instruction in the pipeline. The towel is indicating that the work refers to the instruction decoding, and the face-to-face binding order, MEM Yang material 1D WB indicates the data is written back. In addition, it also indicates that the "preload method" occurs. Table 3 makes the inner color method one instruction in the pipeline sergeant ^^ word

Command ---w giant mouth, J 枉 CHJ* pound clothes. --- cycle 1 2 3 4 5 6 7 Q g CMPrl, #10 IF ID MEM MEM WB BEQ loop IF ID MEM MEM WB LOAD γ2, ΓγΟ #01 IF ID EXE MEM WB ADD r3, r3, r2 IF ID stall stall EXE mem WB ADD rl, rl.#l IF stall stall ID EXE MEM WB ❹ As can be seen from Table 4, the data is extracted from the poor material cache by waiting for the command "L〇ADr2, [r〇#〇]" To the scratchpad r2, the next instruction "ADDr3, r3, r2" and "ADDrl, rl, #1" will be delayed for several cycles (as indicated by the stall in Table 4) until the instruction "l〇ad r2, [r〇#〇]” Complete the operation of data extraction (marked in MEM in Table 4). As shown in Table 3, the preloading method of the above embodiment is used, and the command "L〇ADr2, [r〇#〇]" is already transmitted through the early loading unit 37 at the instruction decoding stage of 17 200949690 27005twf.doc/n. The data is extracted from the data cache to the early loading queue 360, so that the data extraction operation MEM does not need to go to the data cache to extract the data again.

Therefore, the next instruction "ADDr3, r3, r2" can be executed without waiting, but after the instruction decode operation ID is completed, the instruction execution operation is performed. Obviously, the above embodiment uses the instruction to be extracted (the color ratio (1) enters the waiting time in the deduction order, and the preloading corresponding to the instruction is loaded earlier, 'can be solved;|> line processor design towel, People _ use the delay is too long, the deeper the depth (the number of levels) of the official line, the effect of the above preloading method on improving the load-use delay will be more obvious. Whether the data is correctly loaded and entered, in the column 36G, the processor of this embodiment can perform invalid name: correct. If the instruction decodes the level 330 corner: /tl (refers to any instruction), the register In the status table 380, the status_bit of the payload of the shoulder H is set to be busy. The destination register of the header is R2', and the state block. Statel.Ojn of the temporary storage R2 is "11". There are records in the other instruction access temporary storage (not in the second gamma (4) trend. The right early loading queue 3< specifies the destination register (for example, the temporary "order" points to the second pointed column (please refer to the silk)咐 The record/refers to the order ^^ will be preloaded ~ "〇〇" (invalid state). Because ^ ^: paste s her Tao (Data Depe Ndency) error. "To avoid data phase ^200949690 jl^w/hw3 27005twf.doc/n In addition, if there is a second instruction (referred to as any instruction) at instruction execution level 340, the data should be written to the data cache or At a certain address of the memory, the processor searches for the preloaded queue 360. If the search result shows that the record/instruction in the Suining column 360 is the same as the memory address to be written by the second instruction, the processor The state of the record/instruction state[1:〇j is not "00" (the table is not invalid) will be loaded early in queue 360. Therefore, a memory Dependency error can be avoided. As described above, the mechanism adopted in this embodiment is divided into two parts: Early Load Policy and invalid means (InvaUdati〇n

Policy). The early loading method is to move the data from the cache memory early to the early loading queue 360. The following is a brief description of the actions of the early loading means: 1. Before the instruction is placed in the instruction queue 320, the instruction is pre-decoded (Pre-decode), if the early loading condition is met (for example: the instruction is LDR, LDRB, etc.) And its addressing mode is

Immediate (pre(post)-indexed) offset), and its base art register (Read state in the Base register status table 38〇, put the instruction into the early loading queue 3 2 Then, the data is loaded into the early loading queue 36〇 via the early loading unit 37G to the cache or the memory. 2 The deduction order reaches the instruction decoding level 33〇, and the pre-loading queue 360 is checked. Whether the information is complete and legal. If yes, then the command ^ ^ H (Destination Register) ^ ^ (Rename) to the corresponding entry (Entry) or address in the hunting column 360. 19 200949690 X AV/V / Λ X wi 27005twf.doc/n There are two situations in which the load instruction can advance to the cache or memory to capture the poor material. There is two cases, one is Data Dependency error. One is memory dependent (Mem〇ry

Dependency) error. The former occurs when the value of the base register is being calculated because of other instructions, so that the instruction of "early manned" may take the old value of the base register and perform memory access. At this time, we will address Grab the wrong information. The latter occurs when the "premature loading" command and another store command access the same memory address, so the data captured by the "know: early loading" command may not be captured. Updated. The Invalidation Policy is used to check if the information is correct. In the case of invalid means we will check for the occurrence of these two situations. If these conditions arise, we will set the corresponding record/instruction loaded into the queue 36〇 early to be invalid/invalid. When the instruction execution level 340 actually executes the instruction, the correct data is retrieved from the cache or the ticker. The following brief invalidation means _: & 0 Case 1: Check whether the base register is legal: when any instruction passes the instruction decode stage 330, the state of its destination register in the register status table 38〇 The field is set to Busy and it is searched for the early loading queue 36 to see if there are instructions to use it as the base register. If so, the status block that is loaded into the corresponding entry (Entry) in the 36 column is set to invalid/illegal. Check if the memory address is legal: When the channel store (St〇re) command generates the memory address at the instruction execution level 34, then the search for the early loader column has the same record. 20 200949690 ▲ 27005twf.doc/n Recall the body address, if any, then load the status bar of the corresponding record in the middle column 36 to be invalid/illegal. In summary, this embodiment designs a mechanism for early loading (EariyL〇ad) to use the ♦ command to wait in the command queue to move data from the cache or memory to one of the processors. Load it early in the queue and come up with an effective way to check if the data you grab is correct. Thus, right, the pipeline 300 successfully preloads the data into the preloaded queue, and the delay caused by the load-use can be effectively reduced. Conversely, if the data loading fails early, it does not affect the original performance of the processor. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing a conventional pipelined processor. FIG. 2 is a flow chart illustrating a preloading method of a processor in accordance with an embodiment of the present invention. 3A is a flow chart illustrating a preloading method of a processor in accordance with another embodiment of the present invention. FIG. 3B illustrates a pipelined processor in accordance with an embodiment of the present invention. [Main component symbol description] 100, 300: pipeline 110, 310: instruction fetch stage 21 27005twf.doc/n 200949690 120, 320: command queue 130, 330: instruction decode stage 140, 340: instruction execution stage 150, 350: Data write back stage 311: extracting unit 312: pre-decoding unit 360: early loading queue 370: early loading unit 371: register reading unit 372: address generating unit 373: data extracting unit 380: register State table S210~S240, S310~S320: steps of processor preloading method

twenty two

Claims (1)

27005twfd〇c/n ❹ 10 200949690 X. Applying for a patented version ·· = The processor's job method includes ·· The result is at the - instruction fetch level 'extract and ride—instruction, read a judgment preload: fruit 'whether early Loading one of the instructions corresponding to the instruction that the finger has been correctly loaded' is based on the preloaded method of the processor as described in the article 如 Patent (4) 帛1, and more The result 'decision shirt puts the instruction into the pre-loading of the ==, before executing the instruction to load the instruction corresponding to the preloaded data into the early loading queue. In this case, the current pre-loading method of the processor mentioned in item 2 of the patent scope is as follows: the status column includes - status field, - program count block, two state information block, one memory address. Block, and position. And the preloaded data column includes, for example, the pre-planting method of the processor described in claim 3, and the decoding of the instruction at the instruction decoding level to obtain a decommissioning result; 23 27005twf.d〇c/n 200949690, according to the decoding result, check - the temporary data contained in the temporary storage is the early manned side +. The method of interrupting the 5th item of the 4th item is determined, and the address block I table includes a state block, and the early load column includes 6: as described in item 4 of the patent scope. The preloading method of the processor is further ❹ 器 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 All records of early warnings; and if the early manned queue contains - the purpose of the record refers to the temporary storage 11, the record is invalid. The designation includes 7: the pre-planting method of the processor described in item 4 of the patent scope, and at the execution level of the instruction, if there is - the second instruction will be - bit ^, then search for the early loader歹, n and ·, ·, - If the memory should be carried early (4) jf has - record and the record is invalid. The same address ' 8 · If the application of the scope of the first paragraph of the patent application determines whether to pre-load the pre-planting method, including: * early carrier private order - pre-wear data step package check - register State table; and 24 27005twf.doc/n 200949690 The result of the judgment indicates that the instruction belongs to a target type, and the status of the register corresponding to the instruction is 〇 the temporary corresponding to the instruction - _ information The manned to premature load will be 9. The step of using the preloaded data as the target data in the pre-cutting of the processor described in claim 1 of the patent application includes: It is prepared and legal in the early loading queue; and if the information is pre-loaded, if the information in the queue is ready and legal, the destination register address specified in the consultation order will be changed. For the early loading of the order, the address of the data is indicated. In addition, 10. If the preloading method of the processor described in claim 1 is not correctly loaded, the target data is extracted according to the instruction at an instruction execution level. 11. A processor, comprising: Φ an instruction fetch stage for extracting an instruction, wherein the instruction fetch stage includes a pre-decoding unit to pre-determine the instruction in the instruction fetch stage to obtain a decision result; An instruction decoding stage is spliced to the instruction fetch stage for decoding the instruction to obtain a decoding result; an instruction execution stage coupled to the instruction decoding stage for executing the instruction according to the decoding result; Loading the queue early, coupled to the pre-decoding unit, according to the determination result, determining whether to preload one of the preloaded data corresponding to the instruction; 25 X * WI 27005twf.doc/n where = preloaded data If the command is not loaded correctly, the instruction execution level extracts a target ancestor according to the instruction. The η 7 track level is loaded earlier, and the right preloaded data is correctly punctured. Preloaded data is used as the target data. • As mentioned in the section 1 of the special fiber section, the early loading queue includes a makeup 扪 & ^ - which is the 祜 匕 拦, blocking position, a program counting block, a temporary storage 5 | information One memory is paid by I-Cheng A * -η σ block and - preloaded data block. Early cut into the coffee U-shaped button ^, which mentions the Μ Μ (4) according to the results of the Jing, whether the mosquito recorded the order. Μ ^ The processor of claim U of the patent scope further includes: a buckle I early loading unit coupled to the early loading queue for use before The instruction is executed early to put the preloaded data corresponding to the instruction into the early loading queue. The processor of claim 14, further comprising: a second register status table, mixed to the instruction decoding stage, for recording the status of the plurality of registers in the processor; ❹ wherein the instruction The decoding stage decodes the instruction, and double checks the register status table according to the decoding result to determine whether the preloaded data is correctly loaded into the early loading queue. . The processor of claim 15, wherein the temporary benefit status table includes a status bar and an early loading of the address field.匕_ 17. The processor of claim 15, wherein if the heart decodes the decoding stage to decode a second instruction, the temporary register in the register state table corresponds to the destination register specified by the second instruction The status is set to busy; the processor 26 200949690 r^υυ, 11 υυ j 27005twf.doc/n searches for the early loading queue - there is a record pointing to the second early loader to set the record to Invalid/k's purpose register, then the reference should be made here, if it is in the Lulu-record and the entry column; if it is loaded early, it is valid. If the heart is the same, the processor sets the record to no early load! The process 11 described in claim 14 of the patent, wherein the hardware is the same. In the early U-command execution level, the manned/storage list is shared by the processor. For example, the processor described in the scope of the patent application, the method includes: the test state table 'secret to the instruction decoding level, the rib record The state of the plurality of scratchpads in the processing state; wherein if the judgment result indicates that the instruction belongs to a target type, and the temporary register state table towel commander, the temporary storage! If the I state is in the ready state, one of the preloaded data corresponding to the instruction is loaded into the early loading queue. 21. The processor as claimed in claim n, wherein the fingerprint is depleted, and the inspection of the poor material in the early loading queue is ready and legal; Ready and legal', change the destination register address of the command to the address of the preloaded data in the queue. ' 27