TW200933377A - Method and system for enhancing read performance in serial peripheral interface - Google Patents

Abstract

A method for reading data in an integrated circuit includes receiving a read command, which is associated with an enhanced data read, and receiving a first address from a plurality of input/output pins. The method includes receiving a first performance indicator and determining whether an enhanced read operation is to be performed based on at least information associated with the first performance enhancement indicator. The method includes waiting n clock cycles, where n is an integer, then outputting data from a memory array in the integrated circuit using the plurality of input/output pins concurrently. The method also includes performing an enhanced read operation, if it is determined that the enhanced read operation is to be performed. In an embodiment of the method, performing an enhanced read operation includes receiving a second address and a second performance enhance indicator without receiving a read command.

Description

200933377 IX. Description of the invention: [Technical field to which the invention pertains] β The present invention relates to an integrated circuit and its operation. In particular, the present invention provides a method and system for enhancing data read performance in integrated circuits. One of the examples is that the present invention can be applied to a sequence memory element that matches a sequence peripheral interface to achieve a fast material transfer rate. However, it must be understood that the present invention has a relatively ❹ 15 Lu 20 25 thought:, the scope of application. For example, the present invention can be applied to other single-input memory elements such as dynamic random access memory, static access memory, parallel flash memory or other non-volatile inventions. The invention can also be applied to the sequence peripheral interface. Used to trace the communication between electronic components. [Prior Art] Medium. The application used in many scorpions is taken from this "cell; two more: input and output pins to place the storage line requirements, sequence flash code (four) in 3 in response to the increased space and your purpose, 诵当]疋 was developed to provide a smaller number of pins that can be supplied. This sequence of flash memory and stored image sounds are used for program downloads, with address bits, so (4) read data or 5 200933377 15 ❹ 20 As the above requires the peripheral interface. To be able to provide a variety of improved techniques for the sequence [invention content] · (d) t Ming is related to the integrated circuit and its operation. Especially in the invention can be applied =; with -? Ertong 2: ,, the invention has a relatively broad scope = Fan catch: used in other separate or embedded notes "flash memory or other non-volatile memory can be used for the interface to carry out the electronic component The present invention provides a method in a self-integrated circuit. The method includes: receiving a read command, the read= is related to: enhancing data reading, and the plurality of input/output pins itfΪf method includes receiving-first performance enhancement indication, = according to >, - And the first-performance enhancement indication_information determines whether the upcoming-enhanced-take operation is performed. The method includes waiting for n clocks = 'where η is - an integer' and simultaneously using a plurality of input/output pins from the -memory array output (4) in the integrated circuit, the data and the first read address Related. The method includes performing an up-and-take operation to determine whether an enhanced read operation is about to be performed based on information related to the performance enhancement indication. In a specific embodiment, performing the enhanced read operation includes receiving a second address from the plurality of corresponding input/output pins, receiving a second performance enhancement indication, and enhancing according to the at least one and the second performance Indication phase 6 25 200933377 Ϊ: Input =?, the first reading address of Si β is related from the integrated body. In the case of only η·, d=!, the present invention also includes determining whether or not to proceed according to at least the second performance. The second enhancement includes: 2 - 4 Γ ΐ 即将 即将 即将 — — — — 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强One effect is to enhance a first bit in the indication with a =. ^-Special, in the embodiment, 'this integrated circuit contains—sequence of the foot of the foot, the order of the interface, the interface pin (four) configuration package is the chip selection (CS#), the second pin is the data output (_ ^ foot Shirt protection (Er / SI 〇 2), fourth 贱 ( (G, fifth pin is the data input (Cong. 〇), the sixth pin is the order) 15 (SCLK), the seventh pin is Retaining (HOLD#/SI〇3) and the eighth pedal supply voltage (VCQ. In the embodiment, this first address is received in a cycle. In a particular embodiment, this first performance enhancement guard 1 The four indicator bits P4, P5, I>6 and P7 are received at the first enhancement indication period and the other four indicator bits P〇, PI, P2 and P3 are at the _th. Strong indication clock period reception Each first enhancement indicates a clock cycle; = one of the four received indication bits is compared with one of the four indicated indication bits at the second enhanced indication clock = in ^ It is decided that an enhanced read operation is about to be performed if the following bars are set: (P7泮3) and (P6#P2) and (P5#P1) and (P4#p〇). ', 午成 according to another embodiment' The invention provides a self-contained body A method for fetching data, the method comprising: receiving a read command associated with reading data on the same page. The method includes receiving a first address from the corresponding plurality of/output pins, and receiving a first performance Reluctantly indicating 'and according to at least one of the first indication of the first performance enhancement indication related to the gas index finger 7 25 200933377 to decide whether to proceed - enhanced read operation. Cai 5 * t , , Qf ^ ^ 5

The 20/output pin outputs data from a dk array, which is related to the poem address. The method also includes performing - enhancing the page reading, the second enhancing the indication related information, determining whether the enhancement is about to be performed, and the enhancing page reading operation comprises selecting a plurality of corresponding input/rounding pins to receive a second a second performance enhancement indication, and based on at least one information related to the second performance indication, determining whether to proceed - the second enhanced reading and waiting for n clock cycles, and then using the plurality of clocks simultaneously The input/output pin outputs data from the integrated circuit, and the f material is associated with the second read address. In the embodiment, the integrated circuit includes a sequence of peripheral interface pin arrangement configurations. The sequence peripheral interface pin arrangement includes a chip selection (cs#) and the second pin is a data output (s〇/ The SI〇 pin is write protection (WP#/SI02), the fourth pin is grounded (G [= is the flute input input 0〇), and the sixth pin is the sequence clock LΪ (the foot is reserved) (__) and the eighth pin are according to an alternative embodiment, the present invention provides an enhanced data reading system: the system includes one or more components 'configured to receive a read command 7, which is associated with a Enhanced data read correlation. The system includes one or more components configured to receive a first address from a plurality of input/output pins. The system includes one or more components configured to receive a first performance Enhanced Finger = 2 This system also contains one or more components, configured to determine whether or not to proceed with a barely populating operation based on at least one of the information related to the enhanced indication. This system contains one or Multiple components, configured to wait for n clock cycles 'the towel η is an integer, Simultaneously using a plurality of 8 25 933377 input / wheel-out pins from the integrated body of the data and the first bit ^ = - memory array output data, the piece 'configured to perform the enhanced read = for this system contains i Or a plurality of meta-strong read operations. Becker _, if it is decided that the increase is "package == ί; two rides the enhanced read ι_ from the plurality of input/output pins to receive a second: address, · e 15 20 2·receive-second performance enhancement indication; and 3. waiting for n clock cycles, wherein a plurality of input/output pins are from the output data, the data and the second integrated reading body are taken according to the second The one or more components are included in at least the particular embodiment, the integrated body, and the state includes the first pin is the wafer selection (cst, output, 101), and the third pin is the write protection (Qing 疋The four-pin grounding (GND) and the fifth connection are data input (SI/S, the sixth pin is the sequence clock (SCLK), the seventh pin is the protection (H0LD#/SI03), and the eighth pin. Is the supply voltage (vcc) ^ In an embodiment, the first plurality of address segments are received in six clock cycles. In some embodiments The first performance enhancement indication includes four indicator bits P4, P5, P6, and P7 received at the first-enhanced indication clock cycle, and the other four indicator bits P0, P, P2, and P3 are at the second enhanced indication. Pulse cycle reception, in which it is determined that an enhanced read operation is to be performed, if the following conditions are true: (P7泮3) and (P6#P2) and (P5 rating 1) and (P4 sealing > 〇). 9 25 200933377 ❹10 15

According to another alternative embodiment, the present invention provides a method of reading data from an integrated circuit. The method includes receiving a first read command associated with an enhanced data read and processing information related to the first read command. The method includes receiving a first plurality of address segments, each of the plurality of address segments being simultaneously received from a plurality of input/output pins of the same. The method includes generating a first read address based on at least information associated with the first plurality of address segments. The method also includes receiving a first performance enhancement indication and determining whether an enhanced read operation is about to be performed based on information associated with the first performance enhancement indication. The method includes simultaneously outputting data related to the first read address from a memory array in the integrated circuit using a plurality of input/output pins. The method includes performing an enhanced read operation, and determining, according to the information related to the enhancement indication, whether the enhanced read operation is about to be performed. In an embodiment of the method, the enhanced data reading method includes: connecting a second plurality The address segment, each of the second plurality of address segments, is correspondingly received by a plurality of corresponding input/output pins. The method is based on the fact that the second plurality of health segments are included in the second plurality of health segments, and the second performance enhancement indication is included, and the plurality of input/output pins are used from the "wheel" in the integrated circuit. Data related to the second read address. In the method, the method also includes at least according to the second performance, :,, the shirt (four) - the second bare reading; in an embodiment, determining whether to enhance the read operation /, compare the first - A first bit and a second bit of the performance enhancement indication: In an embodiment of the method, the integrated circuit includes a (two-sided pin: row configuration, which includes the first pin is a crystal selection: (the second pin is a data output (_〇) 1), the third pin is ^ 25 200933377 protection (WP#/SI02), the fourth pin is ground (GND), the fifth pin is data input (si/sioo), and the sixth pin is sequence clock (SCLK), the seventh pin is reserved (H0LD#/SI03) and the eighth pin is the supply voltage (VCC). In a particular embodiment, the first read command includes a read command. In the example, the first plurality of address segments are received in six clock cycles. In the embodiment, the first performance enhancement indication includes four indicator bits P4, P5, P6, and p7 in the first (fourth) indication. The clock cycle is received, and the other four indicator bits p〇, n, p2*p 〇ίο 15 ❹ 20 two enhancements indicate clock cycle reception. The indicator bits received in each____ clock cycle will be In the second clock cycle, the (four) indicator bit corresponds to - for comparison. In the particular embodiment, it will be decided that the second enhanced read operation will be 'if the following conditions are true and (P5 Khan) 1) and (P4#P0). V Ψ Z) According to another embodiment, the present invention provides a method of 2 data. The method includes: receiving a middle data plus the heart two: reading the address and the integrated body The first page of the memory array in the circuit is related. The method includes receiving and not performing the enhanced read operation associated with the first-performance enhancement indication. This method also includes = deciding that this barely read is about to be performed. To take the operation, 曰 to = a number of address paragraphs; the method includes receiving the second plurality of parents and a number of address paragraphs from their corresponding complex 11 25 200933377 several input / output pins simultaneously received. At least according to The information related to one or several address segments 'generates a second read address. The packet receives the second performance enhancement indication, and simultaneously outputs the plurality of dry/output pins from the integrated circuit (4), The data *" reads the address correlation. In the embodiment, the second read address 'product; the first page of the memory array in the circuit is associated. This method also contains the data; = 5 = indicates the relevant data, Decide whether or not to proceed 10 15 _ 20 in one of the methods In a specific embodiment, the integrated circuit includes a column of peripheral interface pin arrangement configurations, wherein the first pin is a crystal (cs#), the second pin is a data output (SO/SI01), and the third pin is耷 protection (WP#/SI02), the fourth pin is ground (GND), the fifth input (S 〇〇 〇〇), the sixth pin is the sequence clock (sc ^ two)

The pin is reserved (H0LD#/SI03) and the eighth pin is the supply J (VCC). In an embodiment, the first read command includes a read-read command. In a particular embodiment, the pages in this memory array contain n bytes (e.g., n = 256). In an embodiment: the first plurality of address segments are received during m clock cycles (for example: m = 2). According to another alternative embodiment, the present invention provides a system for enhancing data reading. The system includes one or more components configured to: 1. receive a read-read command associated with an enhanced data read; 2. process information related to the first read command; 3. receive a first complex number Each address segment, each first-plural address segment is received simultaneously from its corresponding plurality of input/output pins; 12 25 200933377 ❹ 15 ❹ 20 1st her __ message, yielding 5. Receive - - Performance enhancement indication, and root: Lake information determines whether it is about to be performed. 6. Simultaneous use of multiple input/output pins to recall the output of the array in relation to the first read address. Determining that the enhanced read operation is about to be performed, the enhanced-read operation is performed in an embodiment in which the system includes - a small number and a second performance increase H to be based on the one or more components To perform the following functions: The component performs the following functions: For example, the 1. receive-second multiple address segments, each falling from its corresponding multiple input/output contacts, 2, multiple bits Information related to the address paragraph, resulting in the third, the second-effect The enhanced indicator determines whether or not the operation is to be performed according to the information related to the second performance enhancement indication; and whether the second enhancement read is to be performed. 4. The plurality of input/output pins are simultaneously used. Data, the data is related to the second read address. 7. 13 200933377 In a specific embodiment, the system includes an integrated circuit including a sequence, the interface configuration of the interface, the configuration of the pin arrangement The first connection is included, the next day chip selection (CS#), the second pin is the data output (so/sioi), the second pin is the write protection (WP#/SI02), and the fourth pin is the ground ( GND), the foot is the data input (SI fine), the sixth pin is the sequence clock ^: the seventh pin is reserved (H〇LD#/SI〇3) and the eighth pin is; i, ii ( Vcc). In the implementation of the shot, this first - plural address paragraph /, solid clock cycle received. In an embodiment, this 〇 10 15 20

= with r indicating that bits p4, p5, p6 and p7 are received in the first-enhanced = clock cycle, while the other four indicating bits P0, PI, P2 and P3 are received in the first enhanced indication clock cycle, and It is decided that an enhanced read operation is to be performed if the following conditions are true: (P7#P3) and (P private p S and (P4#P0).) Many advantages can be achieved by the present invention compared to the conventional method. By way of example, the present invention can be applied to conventional serial peripheral interface pin arrangements to provide an easy to use method. In some embodiments of the invention, the data and address transfer speeds can be increased. In the present invention, the present invention can provide high speed and random read operations. In a specific embodiment, the present invention provides a page reading method that does not allow for the recording of the data. The one or more features of the present invention can be (10) The book towel (4) is specifically described in the following description, particularly in the following description. Other features, objects, and advantages of the present invention will be fully understood by the following drawings, the detailed description of the invention, and the scope of the patent application. 25 200933377 [Embodiment]

15

20 The present invention relates to an integrated circuit and its operation. In particular, a method and system for integrating a peripheral interface of a read performance for an integrated circuit tape comprising a sigma TG component. Wherein, the _ example is the invention can be applied to the sequence memory of the phase-to-edge interface agreement to achieve a fast negative transfer rate. However, it must be understood that this has a wide range of applications. For example, the present invention can be implemented in other separate or embedded memory elements such as dynamic random access memory, static random access memory, parallel flash memory or other non-volatile memory. The invention can also be applied to a sequence of peripheral surfaces for communication between electronic components. Depending on the embodiment, the invention encompasses many features that can be used. These features include the following: 1

* Use the traditional sequence peripheral interface pin arrangement to achieve a higher data transfer rate. W * allows multiple random reads with a single read command. And the guarantee * can use multiple read commands and partial address information to perform multiple random read operations on the same page. As described above, the features described above can be applied to one or more embodiments. These features are for illustrative purposes only and are not intended to limit the scope of the invention. Various variations, modifications, and combinations can be readily achieved by those skilled in the art. 1 is a schematic diagram of a simple pin arrangement configuration with a sequence peripheral interface 15 200933377 according to an embodiment of the present invention. Patented dry circumference. Variations, modifications, and combinations for those skilled in the art. As shown in the figure, according to this example, the integrated circuit 7L includes the following signals: the first selection (CS#), the second pin is the data output (SQ) protection 〇m), and the fourth pin is grounded (GND). ), the first input (DI), the sixth pin is the sequence clock (SCLK), , = 〇ίο 15 20 (Η〇_ and the eighth pin is the supply voltage (vcc). In the middle, the second pin is Arranged as S0/SI01, the third pin is secured == 102, the fifth pin is arranged as _〇〇, ^ the women's volleyball is 臓 103. In the following description, these loses =

A method of using a "receiving address and J" according to a different embodiment is a simple block diagram of a circuit having a memory element according to one embodiment of the present invention. This illustration is for example only and is not used. To limit the scope of the claimed invention, various variations, modifications, and combinations can be readily made by those skilled in the art. As shown, the integrated circuit component 200 includes a plurality of input blocks coupled to their respective Input and output pins. In a particular embodiment, the integrated circuit component includes input and output pins that conform to a sequence of peripheral interface pins. For example, component 200 can include intervening with the following input/output circuits. Input/output pin: SI/SIOO pin is coupled to SI/SIOO block 211; S0/SI01 pin is connected to SO/SIOI block 212; WP#/SI02 pin is coupled to WP#/ACC block 213; 16 25 200933377 H0LD#/SI03 pin is coupled to HOLD# block 214; CS# pin is coupled to CS# block 215; SCLK_ pin is coupled to SCLK block 216. As shown in Figure 2 The component 200 also includes the following circuit blocks associated with the memory array 230 5 . 230, ❿X decoder 231, page buffer 232, Y decoder 233, 1 〇 sense amplifier 234, and output buffer 236. Element 200 also includes the following control and support circuit blocks. Address generator 221, ❹ data Register 222, 15 SRAM buffer 223, mode logic 224, clock generator 225, state mechanism 226, and high voltage generator 227. 20 is for illustrative purposes only, and is specific to the present invention. The embodiment discusses some of the operations of component 200. The system clock signal 17 200933377 5 ❹ 10 ❹ 20 SCLK at terminal 216 is coupled to clock generator 225, which in turn is interfaced with the mode logic. Mode logic 224 is operationally The meeting is connected to receive the wafer selection signal at the (IV) input terminal. The command or instruction can be input via the input SI/fI block 211 and then passed to the data register 222, mode logic. Mode logic 224 The state mechanism 226 is used in conjunction with decoding and executing the command, such as reading, erasing, or stylizing operations. In a practical example, the mode logic 224 is also received from the wp#/SI〇2 block 2n. To perform a write protection function, and self-discipline (7), block 214 receives a signal to prevent the clock signal from entering the state mechanism. According to a particular embodiment, the data may be via the SI/SI block 211, S0. The /SI01 block 212, the WP#/SI〇2 block 213, and the !1〇1^#3 3 block 214 are input, which are coupled to the #料存器 222. The data register 222 is coupled to the SRAM buffer 223 for temporary storage. The data may be output via SI/SI block 2U, S0/SI01 block 212, WP#/SI〇2 block 213, and h〇ld#/si〇3 block 214, which are coupled to output buffer 236. Pick up. A location corresponding to one of the memory arrays 230 can be provided from the data register 222 to the address generator 221. This address is then decoded by the χ decoder 23° 解码 decoder 233. Page buffer 232 is lightly coupled 230 to provide temporary storage of memory operations. * - Read #_ is passed from the memory array 230 via the sense amplifier 234 to the second 236. In a write operation, the data is transferred from the page buffer 232 to the memory array 23 from the data buffer. For a write operation, such as a write operation, the high voltage generator 227 is activated. </ RTI> Although, in the above description, the integrated circuit components are constructed using the components of the group, but of course, various other variations and modifications may be made. For example, you can add other parts. Can be expanded or combined.排也# is exchanged or _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ It is not used to limit the local variation of various kinds of fish, and the skill of the fish is 2. For those skilled in the art, the method of reading can be easily summarized as shown in the figure below. [Step 31〇) Receiving a _read command; 2. (shoulder 32G) processing the information related to the first read command; 3. (step 330) receiving - the first plurality of address segments; m 15 ❹ 20 25 No upcoming - Added as a first-performance enhancement indicator, and the decision is a number, after 6: hour = period, where n is a memory array in the entire integrated circuit circuit; and 7 is added: enhanced-read Taking the operation, if it is decided that the data is an enhanced plurality of pins according to an embodiment of the present invention: pass = = = " and the use of the generation method can also be provided, which is added to its 200933377 ί: Ϊΐ Ϊΐ for a process - or Multiple sequences have been modified' without deviating from the foot of this issue. The details of this method 2 can be found in the description 'and more specifically refer to the following remedies. 15 ❹ 20 4A* 4B ® based Method for reading data in integrated circuit in one embodiment of the present invention Simple timing diagram. This illustration is only an example. It is not a limitation on the scope of this hair. For those who are skilled in the art, various variations, modifications and combinations can be easily achieved. The simple flow chart of Figure 3 and the use of the four input output pins for the enhanced slave reading method are used in the case of the -specific sample towel. A 75 MHz clock is used. In other implementations, the clock rate can be adjusted for different applications. As shown, the wafer selection ((10)) signal is set to a low level. At step 310 an 8-bit instruction is designed to be 32 ( 16-bit) is transmitted using the si/sioo pin. In step 32, the method includes processing information related to the first read command. Referring to Figure 2, the command is transmitted to the mode logic 224 and decoded. State mechanism 226 is activated to prepare further material associated with this enhanced read command. At step 330, a 24-bit address A0, ,, A23, using SI/SIOO, SO/SICM, WP#/SI02, and H0LD# /SI03 pin to receive. Each pin A series of received address bits, which address is assigned to a paragraph.

In a particular embodiment, the 24-bit address is received during the ✓ clock cycle of the clock signal SCLK. The timing of this address transfer is shown in Table 1 below. 20 25 200933377 Table 1 Address Clock Cycle I/O Pin _ 1 2 3 4 5 6 SI/SIOO A20 A16 A12 A8 A4 A0 SO/SIO1 A21 A17 A13 A9 A5 Al WP#/SI02 A22 A18 A14 A10 A6 A2 H0LD#/SI03 A23 A19 A15 All A7 A3 ❹ For example, in the first address clock cycle, SI/SIO receives the address bit A20, S0/SI01 receives the address bit A21, WP#/SI02 receives The 5 address bit A22, HOLD#/SI〇3 receives the address bit A23. In sequence, the address bits A16, A17, A18, and A19 are simultaneously received in the second address clock cycle, and the address bits A12, A13, A14, and A15 are simultaneously received in the third address clock cycle. The fourth address clock cycle simultaneously receives the address bits A8, A9, A10, and All. When the fifth address clock cycle is the same as 10, the address bits A4, A5, A6, and A7 are received, and in the sixth bit. The address clock cycle simultaneously receives the address bits AO, A1, A2, and A3. Referring to FIG. 2, in an embodiment, the address bits A20, A16, A12, A8, A4, and A0 of the first paragraph are received using the SI/SIOO pin and transmitted from the SI/SIOO block 211 to the data. The memory 222. The address bits A21, A17, A13, A9, A5&quot; and A1 of the _15th paragraph enable the ^200933377 S0/SI01 pin to be received and transferred from the S0/SI01 block 212 to the data register 222. The address bits A22, A18, A14, A10, A6 and A2 of the third paragraph are received using the WP#/SI02 pin and transmitted from the WP# block 213 to the data register 222. The address bits A23, A19, A15, All, A7 and A3 of the fourth paragraph are received using the HOLD#/SI03 pin and are transferred from the HOLD# block 214 to the data register 222. In step 340, the address segment is passed to address generator block 221, where the address bits of the address segment are assembled into a read address 'e.g., A24, A23, A1, A0.

15 ❹ 20, Print New See Figure 4A. In the next two clock cycles of the clock signal SCLK, this method receives the -first performance indication (step 35〇). In the second embodiment, the first performance enhancement indication includes 8 bits, up to 1 Η: it is received using four input/output pins. For example, 'four indicator bits (4)... call center first, pulse period reception' and the other four indicator bits p〇, ...; then receive the clock cycle reception. In step %, the strong indication is performed according to at least the performance indicator of the performance indicator, which corresponds to the four indicator bits received in the second &gt; = shot: compared to the received upcoming-increment _ take operation, false, will decide and (4) Ρ 2) and (Ρ柳) and 0 gt; 4 sword). ^ (Ρ7· XOR or modification. Tian..., there may be other changes in an embodiment, this method contains η is - the number of the shop to see the appropriate, the clock cycle, in the example, this material Sigh 8 days = in - specific real J. In step 360, 22 25 200933377 This method contains access to the record column to refer to the first-read address phase data of the wealthy. This method also comes from the product. The memory array in the body circuit rotates this = take the Bay # as shown in Figure 4A, the one-tuple's capital =, week = the skin transmission 'for example' in the first - data clock on the second, in the data The clock cycle transmits data: ί performs a H-fetch operation or outputs a special number of bytes according to the needs of the application. For example, in a read operation 10 15

The number of bytes transmitted in 20 can be one-tuple, two-tuple 戋θ, four-bit, and the like. - 疋 In step 370, if an enhanced read operation is to be performed based on the data associated with the performance enhancement indication, an enhanced read operation is performed. In an embodiment of enhanced read, a data read can be performed without a new read command. Here, the address of the second read address is received, and a second read address is formed to select a second memory location. In a particular embodiment, the bare data reading method comprises the steps of: / 1. (step 510) receiving a second address; 2. (step 520) receiving a second performance enhancement indication; 3. (step 530) Waiting for n clock cycles, where η is an integer 'after simultaneously using a plurality of input/output pins to output data from the memory array in the integrated circuit; 4. (Step 540) based at least on the second performance Enhance the indication related information 'Deciding whether a second enhanced read operation is about to be performed. In step 510, a second address is received from a corresponding plurality of input/output pins. For example, four input/output pins are used simultaneously to receive the bit address A23-A0 23 25 200933377. This second address consists of A23-A0, so its department is independent of the address of the brother. This first address and the second address can be located on different pages. 15 ❹ 20 f. Step 520, receiving a second performance enhancement indication. As shown in Fig. 4B, four input/output pins are used simultaneously to receive the performance enhancement indicator bit' as previously described. h In step 53, the method includes waiting for n clock cycles, where n integers, followed by a plurality of input/output pins simultaneously outputting data from the memory array in the circuit. This data is off with the second read address. As shown in Fig. 4B, the data bit D7_D〇 is simultaneously output using four input/output pins in two pulse cycles. Step 540, the method includes determining whether to be performed according to at least the information of the second performance enhancement II. The second enhanced reader is similar to the previously described performance enhancement indicator bit P7-P. And the mosquito is about to proceed - enhance the reading operation, if the following (P#P3) and (P research 2) and (P5泮D and (P4 Qing). Hold Hit:: 'If the performance is enhanced, the thin setting' This enhanced reading is based on the fact that the actual complement of the "additional" method will continue in accordance with the demand of strong and private. Therefore, a single multiple random data reading operation. Conversely, the traditional technology Π traditional technology Each data reading operation must be decoded, and σ is decoded, resulting in more system operation management time. Memory arrays are arranged as pages &amp; some integrated circuits j 丨24 25 200933377 In one example, a page includes 256 bytes. In other examples, a page can include 512, 1K, or 4K bytes, etc. In some applications, it may be desirable to have the same page in a memory array. Multiple read operations at different memory locations. In another embodiment of the invention, a method for performing multiple read operations at different memory locations on the same page of a memory array without the need to repeat the read command or the repeated copy of the address information is provided. The details will be described below. Sections 6A and 6B are simplified timing diagrams of an enhanced data reading method in an integrated circuit according to an embodiment of the present invention. This illustration is only for the example 10 and is not intended to limit the present. The scope of the patent application of the invention is readily achievable by those skilled in the art to various variations, modifications, and combinations. The enhanced page reading method includes multiple data reading operations on the same page of a memory array. The method includes the following steps: 1. Receiving a first read command;

20 25 2. processing the information related to the first read command; 3. receiving a first plurality of address segments; 4. generating the first read address based on at least information related to the address segment; 5. receiving a first performance enhancement indication and determining whether an enhanced read operation is to be performed; 6. waiting for n clock cycles, where n is an integer, and then outputting data from a memory array in the integrated circuit; and 7. An enhanced read operation is performed if it is decided that an enhanced read operation is to be performed. As described above, this enhanced page reading method is similar to the previously described enhanced reading method of 200933377. However, the difference in the memory location is that the method of reading the memory/face in the thumb/Fig. 3 is described in the following section. Enter multiple data read operations. In this case, a picture 2::: is about to be performed - an enhanced read operation is formed to select - a second memory ^ - a second read address A7-A0 Ο 10 15

The same is true for the 20th-first memory address = it is specified in a different face than the first-read address A23-A8. In this embodiment, the different bits in the same page of bits are located, and the bit Α7·Α() is specified as the page reading method. The method includes the following steps. In a specific embodiment, the enhancement 1 receives a second. The address is in the first page; 2. Receive - the second performance enhancement indication; 3. Two clock cycles, where - an integer is followed by "the memory of the integrated circuit (4) output data; and 4. ^ according to The information related to the second performance enhancement indication determines whether the next enhanced read operation is to be performed. / In the sixth diagram, 'receives the second plurality of address segments. Each of the first and plural address segments simultaneously Each of the corresponding multiple input/output pins is received. For example, in the sixth diagram, the address bits Α7_Α〇, using four names SI/SIOO, SO/SIOI, WP#/SI02, and H0LD The input/output pins of #/SI03 are received. In a particular embodiment, a page includes 256 bytes, which can be addressed by an 8-bit address in this page. Thus, as shown in Figure 6B This address bit A7_A is divided into four address segments each containing 2 bits. , A4 and AO, A5 and Al, A6 and A2 and A7 and A3. 26 25 200933377 ❹ 10 15 ❹ 20 Generated based at least on information relating to the second plurality of address paragraphs and the first plurality of page address paragraph tables _ second read address. For example, 'in FIG. 6B' uses address bits TO A23-A8 from the first plurality of page address segments and address bits from the second plurality of address segments A7]A0' generates a second read address. According to an embodiment of the invention, since the second read address points to a memory location in the same page as the first unique address, only the second read needs to be transmitted. Take a bit of the address of the address towel. A read command and repeat position bit A23_A8 can reduce the system operation management time. Finder... Receive a second performance enhancement indication. As shown in Figure 6B, At the same time, the input/output pin is used to receive the performance enhancement indicator bit P7_p〇 in two clocks respectively, as described above. This method includes waiting for n clock cycles, and then using a plurality of clocks simultaneously. The output of the output of the W output from the integrated circuit The number η of these ^ clock cycles can be selected according to the needs of the application. In the embodiment of = = and 5 ' in the special case, η 彳 is shaped as eight waiting clock cycles. Corresponding to the second read address. The data bits D7-D0 shown in the dip picture are output simultaneously using four input/output pins in two clock cycles. The method includes whether a second enhanced read operation is to be performed according to at least the second performance enhancement indication associated with the second performance enhancement indication. The bit Ρ7·Ρ〇 is processed and 'enhanced-enhanced read

θ The following conditions are true: (Ρ7#Ρ3) and (Ρ6#Ρ2) and (Ρ5 and U二二i. In the embodiment - as long as the performance enhancement indication is set, this enhancement continues continuously. In an alternative embodiment, the present invention provides an enhanced data reading 27 25 200933377 system: an example of this system can be found in Figure 2_6. For example - this system contains one or more components, configured as: Off; L receive-page read command, which processes information related to the page read command with an enhanced data read phase; λ* receives the first plurality of address segments, each first plurality of addresses And the corresponding input/output pin of the Luomu is received at the same time; Ο 15 ❹ 20 壬$ at least according to the information related to the first-plural address segment to generate the first page read address; 5. Receive a first performance Enhanced indication; who depends on the information related to the performance enhancement indication, decides whether it is going to be difficult to read the operation; using the 7th second Hn clock cycle, where η is an integer, and then the array output d out the pin simultaneously Memory from the integrated circuit The first page reads the address correlation; and the read operation advances the read operation 'if the decision is about to be performed - the enhancement will at least hold the gamma =, the system of the present invention contains one or more components that are about to perform 2nd performance enhancement Indication side (four), decide whether to read the operation carefully: enhance the read operation. In a specific embodiment of this enhancement for pregnancy 'this system contains one or more components, paragraphs from every number of address paragraphs 'Every-second number of addresses should be received at the same time as the input/output pin; 28 200933377 2. To the second read address according to the second plural address; Λ ^ $ - &lt; At 4 欵迠 enhanced indication, and according to at least one with the "3 的 information, whether the mosquito is about to carry out a second rumor 4 with a clock cycle 'where η is an integer' after the same person / turn out the pin The memory array output data in the integrated circuit is associated with the second read address. Ο 15 20 In the embodiment of the ancient skin, the system includes an integrated circuit having a side input Roll out pin arrangement, this pin arrangement Including the first (; 〇 = 一 一 1 select _, the second pin is data output β), the second pin is write protection (WP# / SI02), the fourth pin 'i (GND), the fifth connection The foot is data input (SI/SI〇〇), sixth pin=column clock (SCLK), seventh pin is reserved (H〇LD#/SI〇3), and connection= is supply voltage (vcc). In an embodiment, the first plurality of address segments are received in six clock cycles. In a particular embodiment of the system, the first enhancement indicator includes four indicator bits P4, P5, P6 P7 at The first enhancement indicates a clock cycle reception, and the second enhancement indication packet is received by the other four indication bits ρ〇, ρι, p2, and p3 on the second enhancement indication date and the pulse period. And it will be decided that an enhanced read operation will be performed if the following conditions are true: (P#; P3) and (P6#P2) and (P5 counts 1) and (P4 evaluates 0). Although the above system shows a sequence and a series of timings of a selected group used in the sequence peripheral interface method for memory: according to an embodiment of the present invention, there may be other various modifications and modifications. Combine. For example, some pin arrangements and f can be exchanged or modified. Depending on the embodiment, the time series of women's volleyball can also be changed. For another example, using the clock cycle of 29 25 200933377 rising edge can be exchanged or ===^^, repair memory, static random access:: dynamic random memory is other non-volatile memory material Millennium flash memory or 而 ί i == preferred embodiment and example 10 15

20 :, use is not used to limit the hair;;, = 5 = 3⁄4: two, easy to achieve a variety of modifications and combinations, : iti; i ^ = in the spirit of the invention and the following patent scope [Description of Schematic] FIG. 5 is a schematic diagram of a simple pin arrangement configuration with a sequence peripheral interface and a round-out hoarding circuit according to an embodiment of the present invention. Fig. 2 is a simplified block diagram showing an integrated circuit having a memory element according to an embodiment of the present invention. Figure 3 is a simplified flow diagram of an enhanced data reading method in accordance with an embodiment of the present invention. The fourth and fourth graphs are simplified timing charts of the bare data reading method in the integrated circuit according to an embodiment of the present invention. Figure 5 is a simplified flow chart of an enhanced page data reading method in accordance with an embodiment of the present invention. 30 200933377 FIGS. 6A and 6B are simplified timing diagrams of an enhanced page reading method in an integrated circuit according to an embodiment of the present invention. [Main component symbol description] 5 200 Integrated circuit component 221 Address generator 222 Data register 223 Static random access memory buffer 224 Mode logic 10 225 Clock generator 226 State mechanism 227 Voltage generation 230 Memory Array 231 X Decoder 15 232 Page Buffer 233 Y Decoder 234Sense Amplifier 236 Output Buffer 31

Claims (1)

200933377 X. Patent application scope: 5 15 20 — The method of reading #料 in the integrated circuit, the method package receives a read command; receives a first address; receives a first performance enhancement _ can enhance the indication related The information is not, and according to at least one of the first effect operations; and whether a first enhanced read is to be performed, according to the first performance___ the first enhanced read operation, #denotation related information It is decided to perform, and the first enhanced read operation is performed. The method of claim 1, wherein the receiving the related information to determine that at least one is after the first performance enhancement finger comprises: waiting for the first enhanced read operation step η clock cycles, the -memory array in the circuit turns out an integer, and then the material is discharged from the integrated machine, and the data is related to the first address. 3. If the patent application scope is 1st jg &amp; + self-complex number of corresponding rounds ^f, the method described in 1 item, further includes: receiving - second effect rape strong 3 out of the pin receiving 1 two address; can be enhanced Indicating phase _f 9 and operating according to at least one and the second effect; determining whether the second enhanced read is about to wait for n clock cycles, β the plurality of input/output ^ integers, and then simultaneously Use and the second address (four); - from the _ Weilu towel output data, the data of the second Χ enhancement ' ^ 操 = enhanced indication phase _ information, decide whether to carry out: species 32 25 200933377 4 · such as the scope of patent application The method of claim 1, wherein the circuit comprises a sequence of peripheral interface pin configurations, and the sequence peripheral interface (s〇/si〇rr^ (S0/SI01) 帛 two pins is write protection (WP#) /SI02), the ith = LK) The fifth connection: the input is the I input (s_), the sixth chat is Ϊ 15 10 15 5 · The method described in the fourth paragraph of the patent application, JL 兮# bit The address is in the six veins. In the force 2〃, the first-display bit P4, P5, the received bit P0, !&gt;, the p2 and the decayed:: strong finger f clock cycle show the clock cycle The phase of the received phase/in the first enhancement indicator indicates that the Γ 曰 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 ( ( ( ( Fiber 2) and (P5#P1)a (P^p〇). Column condition is established··(P7#P3) 25 Contains: 8. A method of reading data from an integrated circuit, the method packet receiving a page read command; receiving a first address; 33 200933377 receiving a first A performance enhancement can enhance the indication related information, 曰, 不^ according to at least one with the first effect read operation; and &quot; decide whether to perform a first enhanced page at the enhanced page read according to the first performance It is decided to perform the operation of the enhanced page read operation when the operation is not related to the information. 9, as claimed in the patent scope flute δ s φ 10 15 ❹ 20 the first performance enhancement indication, and the method of claim 8, wherein the receiving the relevant information is determined according to at least one and the first performance The step of enhancing the step further comprises: waiting for the first enhanced page read operation to wait for n clock cycles, the plurality of input/output pins from "," an integer, and then using the first address correlation. - money array output data, the data and the method described in the plurality of items 8 further include: receiving - the second performance 増 == information 'determination is about to proceed - second"; face: f to two The clock cycle, where n is an integer, and then uses the method described in item 8 of the application of μn ^, wherein the integrated body is configured with a peripheral interface pin, and the peripheral interface pin group of the sequence is first匕3 first connection = wafer selection (cs#), second pin is data output (S0/SI01), second pin is write protection (wp job phantom fourth chat is ground (GND) The fifth pin is the data input (SI/SI〇〇), the sixth pin is the sequence 34 25 200933377 column clock (SCLK), the seventh pin is reserved (HOLD#/SI〇3), and the eighth connection The foot is a supply voltage (VCC). The method as described in claim n, wherein the second performance enhancement is included in the P-P5, PM° P7 received by the -first-enhanced indication clock cycle, And in the second enhanced indication clock period j, the indication bits p〇, n, p2, and p3 are received, each of which is connected to the first 10 15 Q 20 d The receiving indicator bit will be compared with the corresponding one of the indicator bits received in the first: the acknowledgment period. 曰-bit 3 is the branch of the item, where the first one or the money' The system includes: receiving a read command; receiving a first address; performing the first enhanced read operation associated with the first performance enhancement indication; performing the first enhanced read operation, Or the system of claim 14, wherein the receiving a second address; receiving a second performance enhancement indication; and 35 25 200933377 transmission periods 'where η is an integer, and then using the plurality of data With the memory array in the circuit, the data is transmitted, and the mosquito (4) picks up the first: incrementally related ❿10 15 ❹ 20 body power patent scope 帛 14 items, wherein the product configuration includes; The foot pin configuration 'the sequence of the peripheral interface pin (SO / sion ^ ^ irD), the first = = to. The pin is reserved for a 10 and the eighth connection - two in such as: two special: period enclosure Receiving the system described in item 1. 4, wherein the first-effect (four) 14 is summarized as a new In the first P4:P; ^ ;^f period, the indication bits p〇, P2, and P3 are received = the first-enhanced read operation, and the following is the secret to be entered (P5 and (P4_) The following conditions are true: (P7 (four) and (P6) 36 25