200901597 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種送電控制裝置、送電裝置、電子機器 及無接點電力傳送系統等。 【先前技術】 近年來，利用電磁感應，即使無金屬部分之接點，仍可 傳达電力之無接點電力傳送（非接觸電力傳送）受到矚目， °亥無接點電力傳送之適用例，提出有行動電話及家庭用機 裔（如電話機之子機）的充電等。 /，、接點電力傳送之先前技術如專利文獻】。該專利文獻1 係藉由所謂負載調制而實現從受電裝置（二次側）向送電裝 =-次側）傳送資料。而後，送電裝置藉由比較器等㈣ 人線圈之感應電壓’以判斷來自受雷梦詈夕# 「0」或Γι」。 附自又電裝置之傳送資料係 "战寻利文獻1之先前技術，用於檢測電 的：限值電®亦因電源電塵及線圈電感等之元件常數參： 不齊而參差不齊。因而有檢測電壓之判定用的/ 術條件嚴格的問題。 〃解ι之技 [專利文獻1]日本特開20〇6_6〇9〇9號公報 【發明内容】 [發明所欲解決之問題] 糟由本發明之數個態樣，元件有參差不齊 現適當之檢測處理的送電控、，亦可實 及無接點電力傳送系統。 電裝置、電子機器 128612.doc 200901597 [解決問題之技術手段] 本發明係關於-種送電控龍置，其設於使_次線圈鱼 二次線圈電磁性結合，從送„置對受電裝置傳送電力， 、十引述又電裝置之負載供給電力之無接點電力傳送系统 的前述送電裝置，且包含：振幅檢測電路，其檢測前述一 次線圈之感應電壓訊號的振幅資訊；趟轉換電路，其進 订檢測出之前述振幅資訊的A/D轉換；及控制電路，並控 制前述送電裝置；前述a/d轉換 測電壓之A/D轉換，长出路在轉換％點’進行檢 “ 纟出基準臨限值電麼之數位資料，嗜 前述振幅檢測電路檢測之電㈣過暫行規定 時點，經過賦予之期間者，前述控制電路使用前述 調制而傳送之資料的檢測：質::述"裝置藉由負載 個。 j雜質檢測及裝卸檢測之至少i 本發明係檢測振幅資訊，_200901597 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a power transmission control device, a power transmission device, an electronic device, a contactless power transmission system, and the like. [Prior Art] In recent years, using electromagnetic induction, even without the contact of the metal part, the contactless power transmission (contactless power transmission) that can transmit power is attracting attention, and the application example of the contactless power transmission of °H, It is proposed to charge mobile phones and households (such as telephone handsets). /,, prior art of contact power transmission, such as patent literature]. Patent Document 1 realizes transmission of data from a power receiving device (secondary side) to a power transmitting device = the secondary side by so-called load modulation. Then, the power transmitting device judges from the sneak peek # "0" or Γι by the comparator (4) the induced voltage of the human coil. The transmission technology attached to the electrical device is the prior art of the Warfare Document 1. It is used to detect electricity: the limit voltage is also due to the component constants such as the power supply dust and the coil inductance. . Therefore, there is a problem that the detection voltage is judged to be strict.专利解之技 [Patent Document 1] Japanese Patent Laid-Open No. Hei 20〇6_6〇9〇9 [Invention] [Problems to be Solved by the Invention] It is a matter of several aspects of the present invention that the components are uneven The power transmission control of the detection process can also be realized with a contactless power transmission system. Electric device, electronic device 128612.doc 200901597 [Technical means for solving the problem] The present invention relates to a type of power transmission control device, which is arranged to electromagnetically combine the secondary coil of the secondary coil fish, and transmit it from the pair of power receiving devices The power transmission device of the contactless power transmission system that supplies power to the load of the electric device, and includes: an amplitude detecting circuit that detects amplitude information of the induced voltage signal of the primary coil; and a conversion circuit that advances Determining the A/D conversion of the amplitude information detected; and controlling the circuit, and controlling the power transmitting device; the A/D conversion of the a/d conversion voltage, and the long wayout at the conversion % point 'checking' The digital data of the limit voltage is detected by the amplitude detection circuit (4). When the period is given, the control circuit transmits the data transmitted by using the modulation. Quality:: " Load one. j impurity detection and handling detection at least i The invention detects amplitude information, _
轉換。此種情況下，在從卜、列雷丁厂欢測出之振幅資訊的A / D 點經過賦予之期門的_暫行規定電壓之時 w巩卞之期間的轉換時點， 臨限值電壓之數位資料， 、，求出基準 之負載變動。藉此，元件有；差出：數，資料檢測二次側 值電壓亦因應其變動 ：h等時，因為基準臨限 理。此外，求出所以可實現適當之檢測處 Ν ίβ卷羊g品限信 測電壓超過暫行規定電壓=用之A/D轉換’係在從檢 行。因此，可防止檢，“ 及過賦予之期間的時點進 而可實現穩定之檢:::錯誤之基準臨限值-的情形， 128612.doc 200901597 此外本發明亦可别述 定電壓之時點，使料數 、電U過暫行規 計數写之计數信… 處理，以在依據前述 之方式，於nw 轉換守點進仃别述A/D轉換 ^控制刖述A/D轉換電路。 藉此，因為可依據計數哭 之日丰點賊、盘 时數位地正確計測進行A/D轉換 之時點，所以可實現更穩定之檢測動作。 此外’本發明亦可前述暫 有之倉㈣心一 K了規疋«係别述受電裝置具Conversion. In this case, the A/D point of the amplitude information that is measured at the time from the Buhler and the Redding factory is passed through the period of the stipulated voltage of the given gate. , ,, Find the load variation of the reference. Therefore, the component has; the difference: the number, the secondary side voltage of the data detection also responds to the change: h, etc., because the reference is limited. In addition, it is found that the appropriate detection can be achieved. 测 β 卷 g g g 品 品 超过 超过 超过 超过 超过 = = = = = = = = = = = = = = = = = = = = = Therefore, it is possible to prevent the detection, and the situation in which the period of the period of the period of the grant is further stabilized:: the reference threshold of the error - 128612.doc 200901597 In addition, the present invention may also specify the timing of the voltage so that Counting number, electric U over the temporary counting, writing the counting signal... Processing, in accordance with the above-mentioned way, in the nw conversion homing point, the A/D conversion is controlled to control the A/D conversion circuit. Because it can accurately measure the time of A/D conversion according to the number of thieves in the counting and crying, it can realize a more stable detection action. In addition, the present invention can also be used in the aforementioned temporary position (four).规疋
有之負載調制部的負载為I ^ ^ ^ & …負载&之檢測電壓，與前述負 載調制敎負載為有負载時之檢測電屢間的電壓。 本發明亦可前述控制電路依據藉由對前述基準臨 用:減去或加上資料檢測用、雜質檢測用或農卸檢測 之妻丈電塵’而獲得之資料檢測用、雜質檢測用或裝卸 檢測用的臨限值電壓，進行資料檢測、雜質檢測及裝卸檢 測之至少〗個。 ^ 可藉由改變參數電壓之設定，個別地設定資料檢 、,J用雜貝檢測用或裝卸檢測用之臨限值電壓，而獲得最 佳之g品限值電壓。而後’可因應依元件參差不齊等而變化 ；D限值電壓，自動修正資料檢測用、雜質檢測用或 裝卸檢測用之臨限值電壓。 本發明亦可前述振幅檢測電路藉由將前述一次線 圈之感應電壓訊號的峰值電壓保持於保持節點，而檢測前 ^ ^ t之峰值電壓；前述控制電路在重設時點，進行 將前述保掊銘科β + P 2之黾荷放電於低電位側電源的重設控制， 〜t °又日夺·點係在從峰值電壓超過前述暫行規定電壓之時 128612.doc 200901597 點:經過第-期間者；前述A/D轉換電路在從前述重設時 點經過第二期間之轉換時點，進行峰值電屡之A/D轉換， 求出4述基準臨限值電壓之數位資料。 藉此ϋ為重设保持節點之電麼，可於峰值電壓穩定後 進仃A/D轉換，所以可提高基準臨限值電壓之檢測精度。 且此：’：發明亦可前述送電裝置包含電壓檢測電路，其 又於引述_人線圈之一端節點與低電位側電源之間的 電壓分割電路，#腺& .+、 义+. 將則述一次線圈之感應電壓訊號輸出至 m分割電路的電麼分割節點；前述控制電路以在資 枓檢測時，與雜質檢測、裝卸檢測時，將來自不同之電壓 分割節點的感應電壓訊號輸入前述振幅檢 進行切換控制。 & ’ 藉此’於資料檢測時之感應電麼訊號的振幅， 測、裝卸檢測時之咸庫雷懕1Μ μ α 离檢 •η级應電屋訊唬的振幅大小不同時， 使用相同之振幅檢測電路進行適當之振幅檢測。 此外：本發明亦可前述控制電路藉由進行將來自第 壓分割節點之感應電壓訊號輸入前述振幅檢測電路的切換 控制，而檢測出過載情、、"•电峪的切換 清况下，進行將來自與前述第-電壓 分割節點不同之第二雷臌八士，μ 电& 刀。即點的感應電壓訊號輸入前 述振幅檢測電路的切拖抽在丨 引 測。 的刀換控制’來進行雜質檢測、裝·… 藉此’可依是否檢測出過載而區分情況，進 測、裝卸檢測’可實現有效之判斷處理。 此外’本發明亦可包合 3脈寬檢測電路’其檢測前述一次 128612.doc 200901597 線圈之感應電壓訊號的脈寬資訊；前述控制電路依據以前 述脈寬檢測電路檢測出之前述脈寬資訊，進行資料檢測， 並使用前述基準臨限值電壓之數位資料進行裝卸檢測。 如此，可藉由分開使用檢測古士 、 、 ^文用微利方式，而提高負載變動之檢 測精度及效率。 此外’本發明係關於-種送電控制裝置，其設於使一次 線圈與二次線圈電磁性結合，從送電裝置對受電裝置傳送 電力，而對前述受電裝置之負載供給電力之無接點電力傳 达系統的前述送電裝置，且包含：脈寬檢測電路，其檢測 前述-次線圈之感應電壓訊號的脈寬資訊；振幅檢測電 路，其檢測前述一次線圈之感應電屋訊號的振幅資訊；及 ㈣電路，其控制前述送電裝置；前述控制電路依據以前 述脈寬檢測電路檢测出之前述脈寬資訊，進行前述受電裝 f错由負載調制而傳送之資料的檢測，並依據以前述振幅 才欢測電路檢測出之前述振幅資訊進行裝卸檢測。 本依據脈寬檢測電路獲得之脈寬資訊進行資料檢 2並㈣振幅檢測電路獲得之振幅資料行裝卸檢測。 由如以就資料檢測，係藉由對資料檢測之靈敏度 行…來進仃，就裝卸檢測，係藉由振幅檢測來進 度及2。’分開使用檢測方式，可提高負載變動之檢測精 定=’ Π明亦可包含:驅動時脈產生電路，其產生規 述-次線圈之驅動頻率的驅動時 ，、依據别述驅動時脈產生驅動器控制訊號，而對驅動 128612.doc •10- 200901597 I述一次線圈之送電驅動器輪出；及波形整形電路，其將 刖述一次線圈之感雍 、 整形訊號；々、fV 訊號予以波形整形，而輪出波形 、，，刖’L &寬檢測電路接收前述波形整形訊號盥前 述驅動時脈，而檢測前述波形整形訊號之脈寬資訊 精此，即使不採用個別地檢測電壓、電流， 嫩…，藉由將電塵波形予以簡單之類比波形： t仍可精由數位電路處理穩定地檢測二次側之負載變 動因此，可以間化之結構適當地檢測二次側之負載變 動。 、外文 此外’本發明亦可前述脈寬檢測電路藉由計測脈寬期 間，而檢測脈寬資訊，該脈寬期間係從前述驅動時脈 主動之電壓位準變成主動之電壓位準的第一點，至前 形整形訊號從主動之電壓位準變成非主動之電廢位第 二點之期間者。 矛 藉此’僅藉由計測第一、筮_机 第 弟—點之間的脈寬期間，即可 檢測脈寬資訊，可以飭彳卜少έ士基 J以間化之結構檢測二次側之負载變動。 此外，本發明係關於-種送電裝置，其包含：上述 -項：送電控制農置；及送電部，其產生交_，而供 給至前述一次線圈。 ” 此外’本發明係關Ρ種電子機器，其包含上述之送雷 裝置。 电 、此外，本發明係關於―種無接點電力傳送系統，其包人 送電裝置與受電裝置，使一次線圈與二次線圈電磁性二 合，從前述送電裝置對前述受電裝置傳送電力，而對前迷： 128612.doc -11 200901597 受電裝置之負載供給電力；且前述受電裝置包含 邛，其將則述二次線圈之感應電麼轉換成直流電塵 載調制部，其從前述受電裝置傳送資料至前述送電裝置 時’因應傳送資料而使負載可變地變化；前述送電裝置包 3 ·振幅檢測電路，其檢測前述—次線圈之感應電壓訊發 的振幅資訊；A/D轉換電路，其進行檢測出之前述振幅 訊的A/D轉換；及控制電路，其控制前述送電裝置；前述 A/D轉換電路在轉換時點’進行檢測電壓之A/D轉換，求 出基準臨限值電壓之數位資料’該轉換時點係從前述振幅 檢測電路檢測之電壓超過暫行規定電壓的時點，經過賦予 之期間者’前述控制電路使用前述基準臨限值電壓之數位 資料，進行前述受電裝置藉由負載調制而傳送之資料的檢 測、雜質檢測及裝卸檢測之至少丨個。 …此外’本發明係關於_種無接點電力傳送系統，其包含 :電裝置與受電裝置，使一次線圈與二次線圈電磁性結 2 ’從前述送電裝置對前述受電裝置傳送電力，而對前述 又電裝置之負載供給電力；且前述受電裝置包含：受電 部，其將前述二次線圈之感應電壓轉換成直流電壓；及負 :調制部，其從前述受電裝置傳送資料至前述送電裝置 =，因應傳送資料而使負載可變地變化；前述送電裝置包 寬檢測電路，其檢測前述一次線圈之感應電麼訊號 ^寬身訊；振幅檢測電路，其檢測前述—次線圈之感應 :壓訊號的振幅資訊；及控制電路，其控制前述送電裝 置’前述控制電路依據前述脈寬檢測電路檢測出之前述脈 1286I2.doc -12- 200901597 寬資訊，進行前述受電裝置藉由負載調制而傳送之資料的 檢測，並依據前述振幅檢測電路檢測出之前述#幅資 進行裝卸檢測。 田、° 此外’本發明係關於一種送電控制裝置，其設於使一次 線圈與二次線圈電磁性結合，從送電裝置對受電裝置傳送 電力，而對前述受電裝置之負载供給電力之無接點電力$ :系統的前述送電裝置，且包含：振幅檢測電路，其檢測 前述一次線圈之感應電壓訊號的振幅資訊；A/D轉換電 路，其進行前述振幅資訊之A/D轉換；及控制電路，其控 制前述送電裝置；前述A/D轉換電路於前述振幅檢測電路 之檢測電壓超過賦予之電壓的時點後，進行前述檢測電壓 之A/D轉換，求出進行前述受電裝置傳送之資料的檢測、 雜質檢測或前述送電裝置與前述受電裝置之裝卸檢測用的 :準限值電壓，刖述控制電路依據前述基準臨限值電 愿i進行前述受電裝置傳送之資料的檢測、前述雜質檢測 及前述送電裝置與前述受電U之裝卸的Μ之至少1 個。 此外’本發明係、關於—種送電裝置，其包含：上述之送 電控制裝置；&送電部，其產生交流電壓，而供給至前述 一次線圈。 此外’本發明係關於一種電子機器，其包含上述之 裝置。 、此外’本發明係關於一種無接點電力傳送系统，其包含 送電裝置與爻電裝置’使一次線圈與二次線圈電磁性結 128612.doc -13- 200901597 合，從送電裝置對受電裝置傳送電力，而對前述受電裝置 之負載供給電力，且前述送電裝置係上述之送電裝置。 【實施方式】 以下’詳細說明本發明適合之實施形態。另外，以下說 明之本實施形悲並非不當地限定記載於申請專利範圍的本 發明之内容者，本實施形態說明之全部結構作為本發明之 解決手段，不限定為必須者。 1.電子機器 圖1 (A)顯示適用本實施形態之無接點電力傳送方法的電 子機器之例。1個電子機器之充電器5〇〇(托架（cradle))包含 送電裝置10。此外，1個電子機器之行動電話51〇包含受電 裝置40。此外，行動電話510包含：lcd等之顯示部512、 以按鈕等構成之操作部514、麥克風516(聲音輸入部）、喇 °八51 8(聲音輸出部）及天線520。 充電器500中經由AC轉接器502供給電力，該電力藉由 無接點電力傳送’而從送電裝置10送電至受電裝置4〇。藉 此，將行動電話510之電池充電，可使行動電話51〇内之裝 置動作。 另外，適用本實施形態之電子機器不限定於行動電話 510。如可適用於手錶、無繩（c〇rdless)電話機、到鬚刀、 電動牙刷、手腕電腦（wrist computer)、掌上終端機、攜帶 式資訊終端或是電動腳踏車等各種電子機器。 如模式地顯示於圖1(B)，自送電裝置1〇向受電裝置4〇之 電力傳送，係藉由使設於送電裝置10側之一次線圈Ll(送 128612.doc -14- 200901597 電線圈）與設於受電裝置40側之二次線圈L2(受電線圈）電磁 δ 开^成電力傳送變壓器（transformer)而實現。藉此 可以非接觸傳送電力。 2·送電裝置、受電裝置 圖2顯不本實施形態之送電裝置10、送電控制裝置2〇、 受電裝置40及受電控制裝置5〇之結構例。圖1(A)之充電器 500等的送電側之電子機器至少包含圖2之送電裝置。此 外，仃動電話510等之受電側的電子機器至少包含受電裝 置40與負載9〇(主要負載）。而後，藉由圖2之結構，實現使 一次線圈L1與二次線圈L2電磁性結合，而自送電裝置⑺對 叉電裝置40傳送電力，並從受電裝置4〇之電壓輸出節點 NB7對負載90供給電力（電壓ν〇υτ)的無接點電力傳送⑽ 接觸電力傳送）系統。 送電裝置10(送電模組、一次模組）可包含··一次線圈 L1、送電部12、電壓檢測電路14 '顯示部16及送電控制裝 置2〇。另夕卜’送電裝置·送電控制裝置2〇不限定於^ 之結構’而可實施省略其構成要素之一部分(如顯示部、 電Μ檢測電路）’或追加其他構成要素’或是變更連接關 係等之各種改良。 送電部12於電力傳送時產生特定頻率之交流㈣，於資 料轉送時，因應資料產生頻率不同之交流電壓，而供給至 -次線圈Li。具體而言，如圖3(Α)所示，如對受電裝置扣 傳送資料「丨」情況下，產生頻率fl之交流電壓，於傳送 資料「〇」情況下’產生頻率f2之交流電壓。該送電㈣ 128612.doc •15· 200901597 可包含驅動一次線圈L1i —端的第一送電驅動器、驅動 次線圈L1之另一端的第二送電驅動器、及與一次線圈以 起構成共振電路之至少1個電容器。 /後，送電部12包含之第一' 第二送電驅動器如分別係 藉由電力MOS電晶體構成之反相電路（緩衝電路），且藉由 送電控制裝置20之驅動器控制電路26控制。 一次線圈L1(送電側線圈）與二次線圈(受電側線圈）電 磁結合，而形成電力傳送用變壓器。如需要傳送電力時， 如圖1(A)、圖1(B)所示，在充電器5〇〇之上放置行動電話 510，形成一次線圈之磁束通過二次線圈L2之狀態。另 外，不需要傳送電力時，物理性分離充電器5〇〇與行動電 話5 10而形成一次線圈L1之磁束不通過二次線圈L2之狀 態0 電壓檢測電路14係檢測一次線圈L1之感應電壓的電路， 如包含：電阻RA1、RA2，及設於RA1與RA2之連接節點 NA3與GND(廣義而言，係低電位側電源）之間的二極體 DA1。 亥電C檢測電路14作為一次線圈L1之線圈端電壓訊號的 半波整流電路之功能。而後，藉由將—次線siLim端 電壓以電阻RA1、RA2分壓而獲得之訊號pHIN(感應電壓 訊號、半波整流訊號）輸入送電控制裝置20之振幅檢測電 路28(波形檢測電路）。亦即，電阻RA1、RA2構成電壓分 割電路（電阻分割電路），而從其電壓分割節點NA3輪出訊 號 PHIN。 128612.doc -16- 200901597 顯示部1 6係使用顏色及 之各種狀態（電力傳送中 LCD等來實現。 影像等顯示無接點電力傳送系統 、ID認證等）者， 如藉由LED及 送電控制裝置2G係進行送電裝置1Q之各種控制的裝置， 可藉由積體電路裝置⑽等來實現。該送電控制裝置20可 包含：控制電路22(送電側)、_路24、驅動器控制電 路26、振幅檢測電路28及人/£)轉換電路。 控制電路22(控制部）係進行送電裝置1〇及送電控制裝置 20之控制者，如可藉由閘極陣列及微電腦等來實現。且體 而言，控制電路22係進行電力傳送、負载檢測、頻率、調 制、雜質檢測或裝卸檢測等時需要的各種程序控制及判定 處理。 振盪電路24如藉由水晶振盪電路而構成，產生一次側之 時脈。驅動器控制電路26依據由振盪電路24產生之時脈及 來自控制電路22之頻率設定訊號等，產生希望頻率之控制 訊號，並輸出至送電部12之第一、第二送電驅動器，以控 制第一、第二送電驅動器。 振幅檢測電路28檢測相當於—次線圈^之一端感應電壓 的感應電壓訊號PHIN之振幅資訊（峰值電壓、振幅電壓、 有效電壓）。藉此，可檢測資料（負載）、檢測雜質（金屬）及 檢測裝卸（取出）等。 如丈電I置40之負載調制部46進行對送電裝置丨〇傳送資 料用之負載調制時，一次線圈L1之感應電壓的訊號波形如 圖3(B)所不地變化。具體而言，為了傳送資料「〇」，而負 128612.doc -17- 200901597 載調制部46降低負載時’訊號波形之振幅(峰值電壓)變 小’為了傳送資料「1」而提高負載時，訊號波形之振幅 (峰值電屢）變化。因此，振幅檢測電路28可藉由進行感應 電壓之訊號波形的峰值保持處理等，判斷峰值電壓是否= 越臨限值電壓，來判斷來自受電裝置4〇之資料為「〇」或 是「1」。 另外，振幅檢測之方法不限定於圖3(A)、圖3(B)之方 法。如亦可使科冑電麼以外的物理量（振幅電麼、有效 電壓）來判斷受電側之負載提高或降低。 A/D轉換電路29在從振幅檢測電路28檢測之電壓（峰值電 壓）超過暫行規定電壓（暫行臨限值電壓）的時點經過賦予之 期間的轉換時點（檢測電塵超過賦予之電麼料點後），進 行檢測電塵之A/D轉換，求出基準臨限值電壓之數位資料 (求出基準臨限值電壓）。㈣，控制電路22制基準臨限 值電壓之數位資料（依據基準臨限值電壓）進行資料檢測、 雜質檢測及裝卸檢測之至少1個。 具體而言，控制電路22從檢測電壓超過暫行規定電壓 (SIGH0)的時.點1始使用計數器之計數處理，趟轉換電 路29在依據該計數器之計數值所設定的轉換時點進行趟 轉換°更具體而言’振幅檢測電路28藉由將一次線圈^之 感應電壓訊號（半波整流訊號）之峰值電壓保持於保持節 點，以檢測振幅資訊之峰值電壓。錢，控制電路22在從 峰值電壓超過暫行規定電壓的時點，經過第一期間之重設 時點（重設期間），進行將保持節點之電荷放電於低電位側 128612.doc •18· 200901597 電源的重設控制。A/D轉換電路29在從重設時點經過第二 期間之轉換時點，進行峰值電壓之A/D轉換，以求出基準 臨限值電壓（SIGHV)之數位資料。 受電裝置40(受電模組、二次模組）可包含：二次線圈 L2、受電部42、負載調制部46、饋電控制部48及受電控制 裝置50。另外，受電裝置40及受電控制裝置50不限定於圖 2之結構，可實施省略其構成要素之一部分，或是追加其 他之構成要素，或是變更連接關係等之各種改良。 受電部42將二次線圈L2之交流的感應電壓轉換成直流電 壓。該轉換藉由受電部42包含之整流電路43來進行。該整 流電路43包含二極體DB1〜DB4。二極體DB1設於二次線圈 L2之一端的節點NB 1與直流電壓VDC的產生節點NB3之 間，DB2設於節點NB3與二次線圈L2之另一端的節點NB2 之間，DB3設於節點NB2與VSS之節點NB4之間，DB4設於 節點NB4與NB1之間。 受電部42之電阻RBI、RB2設於節點NB1與NB4之間。而 後，將節點NB 1、NB4間之電壓藉由電阻RB1、RB2予以分 壓而獲得之訊號CCMPI輸入受電控制裝置50之頻率檢測電 路60。 受電部42之電容器CB1及電阻RB4、RB5設於直流電壓 VDC之節點NB3與VSS的節點NB4之間。而後，將節點 NB3、NB4間之電壓藉由電阻RB4、RB5予以分壓而獲得之 訊號ADIN輸入受電控制裝置50之位置檢測電路56。 負載調制部46進行負載調制處理。具體而言，從受電裝 128612.doc -19- 200901597 置40傳送希望之資料至送電裝置ι〇時，因應傳送資料，使 、載周制46(一次側)之負載可變地變化，如圖3⑻所示 地使-次線圈L1之感應電麼的訊號波形變化。為此，負載 °周制部46包含串聯地設於節點NB3、NB4之間的電阻 RB3及電晶體TB3⑽之CM〇s電晶體）。該電晶體彻 藉由來自文電控制裝置5〇之控制電路52的訊號實施接 通 '斷開控制。而後，接通、斷開控制電晶體τβ3，進行 負載調制時’饋電控制部48之電晶體Τβι、τβ2斷開，而 形成負载90不電性連接於受電裝置4〇之狀態。 如圖3⑻所示，為了傳送資料「Q」，而將二次側形成低 負載（阻抗大）情況下，訊號P3q形成L位準，電晶體加斷 開。藉此，負載調制部46之負載形成大致無限大（益負 載）。另外，為了傳送資料「！」而將二次側形成高負載（阻 抗小）情況下，訊號P3Q形成Η位準，而電晶體ΤΒ3接通。 藉此，負載調制部4 6之負載形成電阻rb 3 (高負载）。 饋電控制部48控制對負載90之電力的饋電。調整器49調 整以整流電路43轉換而獲得之直流電壓VDC的電壓位準， 產生電源電壓VD5(如5 V)。受電控制裝置5〇如供給該電源 電壓VD5而動作。 ’、 電晶體TB2 (P型之CMOS電晶體）藉由來自受電控制裝置 50之控制電路52的訊號P1Q而控制。具體，， ' 5 ，電晶體 TB2於m認證完成（確立），進行通常之電力傳送情況下接 通，而於負載調制時等斷開。 電晶體Tm (P型之CMOS電晶體）藉由來自輸出保證電路 128612.doc • 20- 200901597 54的訊號P4Q而控制。具體而言，於戰'證完成，進行通 常之電力傳送情況下接通。另外，檢測ac轉接器之連 接，於電源電屋VD5比受電控制裳置5〇(控制電路52)之動 作下限電壓小時等斷開。 受電控制裝置观進行受電裝置4Q之各種控制的裝置， 可藉由積體電路裝置（IC)等來實現。該受電控制裝置对 藉由從二次線圈L2之感應電麼產生的電源電屢彻而動 作。此外，受電控制裝置5〇可包含：控制電㈣（受電 ⑷、輸出保證電路54、位置檢測電路56、㈣電㈣、 頻率檢/則電路60及滿充電檢測電路。 控制電路52(控制部）係進行受電裝置扣及受電控制裝置 5〇之控制者，如可藉由閘極陣列及微電腦等來實現。且體 而言’控制電路52係進行ID認證、位置檢測、頻率檢測、 負载調制或滿充電檢測等時需要的各種程序控制及判定處 輸出保證電路54係保證低電堡時（〇v時）之受電裝置扣的 輸出之電路，且防止電流自電壓輸出節點NB7向受電裝置 40側逆流。 位置檢測電路56監視相合於_ Am 冲*於—一人線圈L2之感應電壓波形 的訊號ADIN之波形，判斷一 ^ -人線圈L1與二次線圈L2之位 置關係是否適當。具體而言，係將訊號細N以比較器轉 =二值或A/D轉換，以判定位準’來判斷位置 否 適當。 振蘯電路58如藉由CR振盪雷技而嫌 依盈逼路而構成，並產生二次側 128612.doc 200901597 之時脈。頻率檢測電路60檢測訊號CCMPI之頻率（fl、 f2) ’如圖3(A)所示地判斷來自送電裝置1〇之傳送資料為 「1」或「0」。 滿充電檢測電路62(充電檢測電路）係檢測負載9〇之電池 94(二次電池）是否達到滿充電狀態（充電狀態）的電路。 負載90包含進行電池94之充電控制等的充電控制裝置 92。該充電控制裝置92(充電控制IC)可藉由積體電路裝置 等來實現。另外，亦可如智慧型電池，使電池94本身具備 充電控制裝置92之功能。 其次，就送電側與受電側之動作的概要，使用圖4之流 程圖作說明。送電側於投入電源而電力接通時（步驟， 進行位置檢測用之暫時性電力傳送（步驟S2)。藉由該電力 傳送，受電側之電源電壓上昇，解除受電控制裝置5〇之重 設（步驟sii)。如此’受電側將訊號piQ設定成h位準並 將訊號P4Q設定成高阻抗狀態（步驟S12)。藉此，電晶體 TB2、TB1均斷開，而遮斷與負載9〇間之電性連接。 其次，受電側使用位置檢測電路56判斷一次線圈u與二 次線圈L2之位置關係是否適當(步驟S13)。而後，於位置 關係適當情況下’受電側開㈣之認證處理，並將認證訊 框傳送至送電側（步驟S14)。具體而言，係藉㈣3(b)中說 明之負載調制，來傳送認證訊框之資料。 送電側接收認證訊框時 進行ID是否一致等之判斷處理The load of the load modulation unit is the detection voltage of I ^ ^ ^ & load & and the voltage of the detected load when the load is modulated by the load. According to the present invention, the control circuit can also be used for data detection, impurity detection or loading and unloading by subtracting or adding data detection, impurity detection or agricultural inspection. The threshold voltage for detection is performed, and at least one of data detection, impurity detection, and loading and unloading detection is performed. ^ By setting the parameter voltage setting, you can individually set the data detection, J to detect the threshold voltage for miscellaneous detection or loading and unloading, and obtain the best g-product limit voltage. Then, it can vary depending on the components, and the D limit voltage automatically corrects the threshold voltage for data detection, impurity detection, or loading and unloading detection. In the present invention, the amplitude detecting circuit may detect the peak voltage of the front voltage by holding the peak voltage of the induced voltage signal of the primary coil at the holding node; and the control circuit performs the above-mentioned protection when the reset circuit is reset. The charge of the β 2 + P 2 discharge is controlled by the reset of the low-potential side power supply, and the point is at the time when the peak voltage exceeds the aforementioned provisional voltage. 128612.doc 200901597 points: after the period-period The A/D conversion circuit performs peak-to-peak A/D conversion at the point of transition from the reset time to the second period, and obtains digital data of the reference threshold voltage. By this means that the power of the holding node is reset, the A/D conversion can be performed after the peak voltage is stabilized, so that the detection accuracy of the reference threshold voltage can be improved. And this: ': Inventively, the power transmitting device may include a voltage detecting circuit, which in turn refers to a voltage dividing circuit between one end node of the human coil and the low potential side power source, #腺&+, meaning+. The induced voltage signal of the primary coil is output to the electrical dividing node of the m-dividing circuit; the control circuit inputs the induced voltage signal from different voltage dividing nodes into the amplitude during the detection of the resource, and the detection of the impurity and the loading and unloading detection. Check for switching control. & 'Through this', the amplitude of the inductive signal during the data detection, the salt and thunder of the test, the loading and unloading detection, 1Μ μ α, the detection, the η level, the difference in the amplitude of the electric house, the same The amplitude detection circuit performs appropriate amplitude detection. In addition, in the present invention, the control circuit may perform switching control of inputting the induced voltage signal from the voltage division node to the amplitude detecting circuit to detect an overload condition and a switching condition of the power supply. The second Thunder Bastars, μ Electric & Knife, which is different from the aforementioned first-voltage split node. The point-inductive voltage signal is input to the amplitude detection circuit and the cut-and-pull is measured. The knife change control is used to perform impurity detection, loading, and the like. By this, it is possible to distinguish the situation depending on whether or not an overload is detected, and the detection and handling detection can achieve an effective judgment process. In addition, the present invention may also include a 3-pulse width detecting circuit for detecting the pulse width information of the induced voltage signal of the coil of the previous 128612.doc 200901597; the foregoing control circuit is based on the pulse width information detected by the pulse width detecting circuit. Data detection is performed, and the digital data of the aforementioned reference threshold voltage is used for loading and unloading detection. In this way, the detection accuracy and efficiency of the load variation can be improved by separately detecting the Gus, and the text. Further, the present invention relates to a power transmission control device which is provided in a non-contact power transmission in which a primary coil and a secondary coil are electromagnetically coupled, and power is transmitted from a power transmitting device to a power receiving device, and power is supplied to a load of the power receiving device. The power transmitting device of the system includes: a pulse width detecting circuit that detects pulse width information of the induced voltage signal of the second coil; and an amplitude detecting circuit that detects amplitude information of the induced electric house signal of the primary coil; and (4) a circuit for controlling the power transmitting device; the control circuit performs detection of the data transmitted by the load modulation based on the pulse width information detected by the pulse width detecting circuit, and is based on the amplitude The amplitude information detected by the measuring circuit is used for loading and unloading detection. According to the pulse width information obtained by the pulse width detecting circuit, the data is checked 2 and (4) the amplitude data obtained by the amplitude detecting circuit is loaded and unloaded. In the case of data detection, the sensitivity is detected by the data detection, and the loading and unloading detection is performed by amplitude detection. 'Separate use detection method, which can improve the detection of load fluctuations. ' Π 亦可 亦可 亦可 ' 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动The driver controls the signal, and the driver 128962.doc •10-2009015971 describes the power transmission driver of the coil; and the waveform shaping circuit, which will describe the inductance and shaping signals of the primary coil; the waveform of the V and fV signals is shaped. And the round-out waveform, the 刖'L & wide detection circuit receives the aforementioned waveform shaping signal 盥 the aforementioned driving clock, and detects the pulse width information of the waveform shaping signal, even if the voltage and current are not individually detected, ..., by simply analogizing the waveform of the electric dust waveform: t can still be stably processed by the digital circuit to stably detect the load fluctuation on the secondary side. Therefore, the load variation on the secondary side can be appropriately detected by the structure that can be alternated. Further, in the present invention, the pulse width detecting circuit may detect the pulse width information by measuring the pulse width period, and the pulse width period is the first from the voltage level of the driving clock active to the active voltage level. Point, the period from the active voltage level to the second point of the inactive electric waste. The spear can be used to detect the pulse width information only by measuring the pulse width between the first and the first machine, and can detect the secondary side of the structure. The load changes. Further, the present invention relates to a power transmission device comprising: the above-mentioned item: power transmission control; and a power transmission unit that generates an intersection and supplies the same to the primary coil. In addition, the present invention relates to an electronic device including the above-described lightning protection device. In addition, the present invention relates to a kind of contactless power transmission system, which comprises a power transmission device and a power receiving device, so that the primary coil and the The secondary coil is electromagnetically coupled, and power is transmitted from the power transmitting device to the power receiving device, and power is supplied to the load of the power receiving device: 128612.doc -11 200901597; and the power receiving device includes 邛, which will be described twice The induction current of the coil is converted into a DC dust load modulation unit, and when the data is transmitted from the power receiving device to the power transmission device, the load is variably changed in response to the transmission of the data; the power transmission device package 3 • the amplitude detection circuit detects the foregoing - amplitude information of the induced voltage signal of the secondary coil; an A/D conversion circuit that performs A/D conversion of the amplitude signal detected; and a control circuit that controls the power transmitting device; the A/D conversion circuit is converting At the time point 'A/D conversion of the detection voltage is performed, and the digital data of the reference threshold voltage is obtained. 'The conversion point is detected from the amplitude detection circuit described above. When the voltage exceeds the provisional predetermined voltage, the period in which the voltage is supplied by the control circuit using the reference threshold voltage is used to perform detection, impurity detection, and detachment detection of the data transmitted by the power receiving device by load modulation. In addition, the present invention relates to a type of contactless power transmission system including: an electric device and a power receiving device, and an electromagnetic connection between the primary coil and the secondary coil 2' is transmitted from the power transmitting device to the power receiving device Power is supplied to the load of the electric device; and the power receiving device includes: a power receiving unit that converts an induced voltage of the secondary coil into a DC voltage; and a negative: a modulation unit that transmits data from the power receiving device to The power transmitting device=the load is variably changed according to the data to be transmitted; the power transmitting device includes a width detecting circuit for detecting the inductive power of the primary coil, and the amplitude detecting circuit detects the aforesaid-secondary coil Induction: amplitude information of the pressure signal; and control circuit that controls the aforementioned power transmitting device' The circuit is configured to detect the data transmitted by the power receiving device by load modulation according to the pulse 1286I2.doc -12-200901597 wide information detected by the pulse width detecting circuit, and detect the aforementioned # amplitude according to the amplitude detecting circuit. In addition, the present invention relates to a power transmission control device that is provided to electromagnetically combine a primary coil and a secondary coil, and to transmit power from the power transmitting device to the power receiving device, and to supply a load to the power receiving device. Powerless contact power $: The aforementioned power transmitting device of the system, and comprising: an amplitude detecting circuit for detecting amplitude information of the induced voltage signal of the primary coil; and an A/D converting circuit for performing A/D conversion of the amplitude information And a control circuit that controls the power transmitting device; the A/D conversion circuit performs A/D conversion of the detection voltage after the detection voltage of the amplitude detection circuit exceeds a voltage to be applied, and obtains the transmission of the power receiving device Detection of data, detection of impurities, or use of the power transmitting device and the above-described power receiving device for loading and unloading detection The quasi-limit voltage, the paraphrase control circuit performs at least one of the detection of the data transmitted by the power receiving device, the detection of the impurity, and the pick-up of the power transmitting device and the power receiving U, based on the reference threshold value. Further, the present invention relates to a power transmission device comprising: the above-described power transmission control device; & a power transmission unit that generates an alternating current voltage and supplies the same to the primary coil. Further, the present invention relates to an electronic apparatus comprising the above-described apparatus. Furthermore, the present invention relates to a contactless power transmission system including a power transmitting device and a power generating device, which combines a primary coil with a secondary coil electromagnetic junction 128612.doc -13 - 200901597, and transmits the power transmitting device to the power receiving device. Electric power is supplied to the load of the power receiving device, and the power transmitting device is the power transmitting device described above. [Embodiment] Hereinafter, embodiments suitable for the present invention will be described in detail. In addition, the present invention is not limited to the scope of the present invention described in the claims, and all the configurations described in the present embodiment are not limited thereto as a means for solving the present invention. 1. Electronic Apparatus Fig. 1 (A) shows an example of an electronic apparatus to which the contactless power transmission method of the present embodiment is applied. A charger 5 cradle (cradle) of an electronic device includes a power transmitting device 10. Further, the mobile phone 51A of one electronic device includes the power receiving device 40. Further, the mobile phone 510 includes a display unit 512 such as LCD or the like, an operation unit 514 composed of a button or the like, a microphone 516 (sound input unit), a microphone 518 (sound output unit), and an antenna 520. The charger 500 supplies electric power via the AC adapter 502, and the electric power is transmitted from the power transmitting device 10 to the power receiving device 4 by the contactless power transmission. By this, the battery of the mobile phone 510 is charged, and the device in the mobile phone 51 can be operated. Further, the electronic device to which the present embodiment is applied is not limited to the mobile phone 510. For example, it can be applied to watches, cordless (c〇rdless) telephones, to knives, electric toothbrushes, wrist computers, handheld terminals, portable information terminals or electric bicycles. As shown in FIG. 1(B), the power transmission from the power transmitting device 1 to the power receiving device 4 is performed by the primary coil L1 provided on the power transmitting device 10 side (sending 128612.doc -14-200901597 electric coil) The electromagnetic coil δ of the secondary coil L2 (receiving coil) provided on the power receiving device 40 side is electromagnetically turned into a power transmission transformer. This allows non-contact transmission of power. 2. Power transmitting device and power receiving device Fig. 2 shows a configuration example of the power transmitting device 10, the power transmitting control device 2, the power receiving device 40, and the power receiving control device 5 of the present embodiment. The electronic device on the power transmitting side of the charger 500 or the like of Fig. 1(A) includes at least the power transmitting device of Fig. 2. Further, the electronic device on the power receiving side of the squeezing telephone 510 or the like includes at least the power receiving device 40 and the load 9 〇 (main load). Then, by the structure of FIG. 2, the primary coil L1 and the secondary coil L2 are electromagnetically coupled, and the self-power transmitting device (7) transmits power to the fork electric device 40, and the voltage output node NB7 from the power receiving device 4 is connected to the load 90. Contactless power transfer (10) contact power transfer system for supplying power (voltage ν 〇υ τ). The power transmission device 10 (power transmission module, primary module) may include a primary coil L1, a power transmission unit 12, a voltage detection circuit 14', a display unit 16, and a power transmission control device 2A. In addition, the power transmission device and the power transmission control device 2 are not limited to the structure ', and one of the components (such as the display unit and the power detection circuit) may be omitted, or another component may be added, or the connection relationship may be changed. Various improvements. The power transmission unit 12 generates an alternating current (four) of a specific frequency during power transmission, and supplies the secondary coil Li to the secondary coil Li when the data is transferred in response to the data. Specifically, as shown in Fig. 3 (Α), when the data is transmitted to the power receiving device, the AC voltage of the frequency fl is generated, and when the data "传送" is transmitted, the AC voltage of the frequency f2 is generated. The power transmission (4) 128612.doc •15·200901597 may include a first power transmission driver that drives the primary coil L1i, a second power transmission driver that drives the other end of the secondary coil L1, and at least one capacitor that forms a resonant circuit with the primary coil. . After that, the first 'second power transmission driver included in the power transmission unit 12 is an inverter circuit (snubber circuit) constituted by a power MOS transistor, respectively, and is controlled by a driver control circuit 26 of the power transmission control device 20. The primary coil L1 (power transmitting side coil) and the secondary coil (power receiving side coil) are electromagnetically coupled to each other to form a power transmission transformer. When it is necessary to transmit electric power, as shown in Fig. 1(A) and Fig. 1(B), the mobile phone 510 is placed above the charger 5A to form a state in which the magnetic flux of the primary coil passes through the secondary coil L2. Further, when it is not necessary to transmit power, the magnetic separation of the charger 5 〇〇 and the mobile phone 5 10 to form the magnetic flux of the primary coil L1 does not pass through the secondary coil L2. The voltage detecting circuit 14 detects the induced voltage of the primary coil L1. The circuit includes, for example, resistors RA1, RA2, and a diode DA1 provided between the connection nodes NA3 and GND of RA1 and RA2 (in a broad sense, the low-potential side power supply). The galvanic C detecting circuit 14 functions as a half-wave rectifying circuit for the coil terminal voltage signal of the primary coil L1. Then, the signal pHIN (induced voltage signal, half-wave rectified signal) obtained by dividing the voltage of the secondary line siLim terminal by the resistors RA1, RA2 is input to the amplitude detecting circuit 28 (waveform detecting circuit) of the power transmission control device 20. That is, the resistors RA1, RA2 constitute a voltage dividing circuit (resistor dividing circuit), and the signal PHIN is rotated from the voltage dividing node NA3. 128612.doc -16- 200901597 Display unit 1 6 uses color and various states (implemented by LCD, etc. during power transmission. Display of contactless power transmission system, ID authentication, etc.), such as LED and power transmission control The device 2G is a device that performs various controls of the power transmitting device 1Q, and can be realized by an integrated circuit device (10) or the like. The power transmission control device 20 may include a control circuit 22 (power transmission side), a path 24, a driver control circuit 26, an amplitude detecting circuit 28, and a person/£ conversion circuit. The control circuit 22 (control unit) is a controller of the power transmitting device 1 and the power transmission control device 20, and can be realized by a gate array, a microcomputer, or the like. In addition, the control circuit 22 performs various program control and determination processes required for power transmission, load detection, frequency, modulation, impurity detection, or detachment detection. The oscillation circuit 24 is constituted by a crystal oscillation circuit, and generates a clock on the primary side. The driver control circuit 26 generates a control signal of a desired frequency according to a clock generated by the oscillation circuit 24 and a frequency setting signal from the control circuit 22, and outputs the control signal to the first and second power transmission drivers of the power transmission unit 12 to control the first , the second power transmission driver. The amplitude detecting circuit 28 detects amplitude information (peak voltage, amplitude voltage, effective voltage) of the induced voltage signal PHIN corresponding to the induced voltage at one end of the secondary coil. By this, it is possible to detect data (load), detect impurities (metal), and detect loading (unloading). When the load modulation unit 46 of the power supply unit 40 performs load modulation for the power transmission device 丨〇 transmission, the signal waveform of the induced voltage of the primary coil L1 does not change as shown in Fig. 3(B). Specifically, in order to transmit the data "〇", the negative 128812.doc -17- 200901597 when the modulation unit 46 reduces the load, the amplitude (peak voltage) of the signal waveform becomes smaller. When the load is increased by transmitting the data "1", The amplitude (peak power) of the signal waveform changes. Therefore, the amplitude detecting circuit 28 can determine whether the data from the power receiving device 4 is "〇" or "1" by performing peak hold processing of the signal waveform of the induced voltage or the like to determine whether the peak voltage = the threshold voltage. . Further, the method of amplitude detection is not limited to the method of Figs. 3(A) and 3(B). It is also possible to judge whether the load on the power receiving side is increased or decreased by the physical quantity (amplitude power, effective voltage) other than the power supply. When the voltage (peak voltage) detected by the amplitude detecting circuit 28 exceeds the provisional predetermined voltage (temporary threshold voltage), the A/D conversion circuit 29 passes the period of the transition period (the detected electric dust exceeds the given electric material point). After that, the A/D conversion of the electric dust is detected, and the digital data of the reference threshold voltage is obtained (the reference threshold voltage is obtained). (4) The control circuit 22 performs at least one of data detection, impurity detection, and loading and unloading detection based on the digital data of the reference threshold voltage (according to the reference threshold voltage). Specifically, the control circuit 22 uses the counter counting process from the time point 1 when the detected voltage exceeds the provisional predetermined voltage (SIGH0), and the 趟 conversion circuit 29 performs the 趟 conversion at the conversion time point set according to the counter value of the counter. Specifically, the amplitude detecting circuit 28 detects the peak voltage of the amplitude information by holding the peak voltage of the induced voltage signal (half-wave rectified signal) of the primary coil at the holding node. The control circuit 22 discharges the charge of the holding node to the low potential side 128812.doc •18·200901597 when the peak voltage exceeds the provisional predetermined voltage and the reset period of the first period (reset period) Reset control. The A/D conversion circuit 29 performs A/D conversion of the peak voltage at the point of transition from the reset period to the second period to obtain digital data of the reference threshold voltage (SIGHV). The power receiving device 40 (power receiving module, secondary module) may include a secondary coil L2, a power receiving unit 42, a load modulation unit 46, a power feeding control unit 48, and a power receiving control device 50. Further, the power receiving device 40 and the power receiving control device 50 are not limited to the configuration of Fig. 2, and various modifications may be made to omit one of the constituent elements, or to add other constituent elements, or to change the connection relationship. The power receiving unit 42 converts the induced voltage of the alternating current of the secondary coil L2 into a direct current voltage. This conversion is performed by the rectifier circuit 43 included in the power receiving unit 42. The rectifying circuit 43 includes diodes DB1 to DB4. The diode DB1 is disposed between the node NB 1 at one end of the secondary coil L2 and the generating node NB3 of the DC voltage VDC, and DB2 is disposed between the node NB3 and the node NB2 at the other end of the secondary coil L2, and the DB3 is set at the node Between NB2 and VSS node NB4, DB4 is located between nodes NB4 and NB1. The resistors RBI and RB2 of the power receiving unit 42 are provided between the nodes NB1 and NB4. Then, the signal CCMPI obtained by dividing the voltage between the nodes NB 1 and NB4 by the resistors RB1 and RB2 is input to the frequency detecting circuit 60 of the power receiving control device 50. The capacitor CB1 and the resistors RB4 and RB5 of the power receiving unit 42 are provided between the node NB3 of the DC voltage VDC and the node NB4 of the VSS. Then, the signal ADIN obtained by dividing the voltage between the nodes NB3 and NB4 by the resistors RB4 and RB5 is input to the position detecting circuit 56 of the power receiving control device 50. The load modulation unit 46 performs load modulation processing. Specifically, when the desired data is transmitted from the power receiving device 128612.doc -19- 200901597 40 to the power transmitting device, the load of the load carrying 46 (primary side) is variably changed according to the data transmitted, as shown in the figure. The signal waveform of the induced current of the secondary coil L1 is changed as shown in 3 (8). To this end, the load peripheral portion 46 includes a resistor RB3 provided in series between the nodes NB3 and NB4 and a CM〇s transistor of the transistor TB3 (10). The transistor is turned "on" by the signal from the control circuit 52 of the electronic control unit 5. Then, when the control transistor τβ3 is turned on and off, and the load modulation is performed, the transistors Τβι and τβ2 of the feed control unit 48 are turned off, and the load 90 is not electrically connected to the power receiving device 4A. As shown in Fig. 3 (8), in order to transmit the data "Q" and form a low load (high impedance) on the secondary side, the signal P3q forms an L level, and the transistor is turned off. Thereby, the load of the load modulation unit 46 is formed to be substantially infinite (benefit). Further, in the case where the secondary side is formed with a high load (small impedance) in order to transmit the data "!", the signal P3Q forms a Η level, and the transistor ΤΒ3 is turned on. Thereby, the load of the load modulation unit 46 forms a resistor rb 3 (high load). The feed control unit 48 controls the feeding of the electric power to the load 90. The regulator 49 adjusts the voltage level of the DC voltage VDC obtained by the conversion circuit 43 to generate a power supply voltage VD5 (e.g., 5 V). The power receiving control device 5 operates by supplying the power supply voltage VD5. The transistor TB2 (P-type CMOS transistor) is controlled by the signal P1Q from the control circuit 52 of the power receiving control device 50. Specifically, '5, the transistor TB2 is completed (established) in m, and is turned on in the case of normal power transmission, and is turned off during load modulation. The transistor Tm (P-type CMOS transistor) is controlled by the signal P4Q from the output guarantee circuit 128612.doc • 20-200901597 54. Specifically, it is turned on when the battle is completed and normal power transmission is performed. In addition, the connection of the ac adapter is detected, and the power supply house VD5 is disconnected from the lower limit voltage of the power supply control panel 5 〇 (control circuit 52). The device that performs various control of the power receiving device 4Q by the power receiving control device can be realized by an integrated circuit device (IC) or the like. The power receiving control device operates repeatedly by the power source generated by the induction of electricity from the secondary coil L2. Further, the power receiving control device 5A may include: control power (4) (power receiving (4), output ensuring circuit 54, position detecting circuit 56, (four) power (four), frequency detecting circuit circuit 60, and full charge detecting circuit. Control circuit 52 (control unit) The controller of the power receiving device buckle and the power receiving control device 5 can be realized by a gate array, a microcomputer, etc., and the control circuit 52 performs ID authentication, position detection, frequency detection, load modulation, or Various program control and determination unit output guarantee circuits 54 required for full charge detection and the like are circuits for securing the output of the power receiving device buckle when the battery is low (when 〇v), and prevent current from the voltage output node NB7 to the power receiving device 40 side. The position detecting circuit 56 monitors the waveform of the signal ADIN corresponding to the induced voltage waveform of the one-person coil L2, and determines whether the positional relationship between the human-coil L1 and the secondary coil L2 is appropriate. Specifically, The signal is fine N is converted to a binary value or A/D conversion to determine the position to determine whether the position is appropriate. The vibrating circuit 58 is forced to rely on the CR to oscillate the lightning. The frequency of the signal CCMPI (fl, f2) is detected by the frequency detecting circuit 60 as shown in FIG. 3(A). 1" or "0". The full charge detecting circuit 62 (charge detecting circuit) is a circuit for detecting whether or not the battery 94 (secondary battery) of the load 9 is in a fully charged state (charging state). The load 90 includes charging the battery 94. The charge control device 92 is controlled, etc. The charge control device 92 (charge control IC) can be realized by an integrated circuit device or the like. Alternatively, the battery 94 itself can be provided with the function of the charge control device 92, such as a smart battery. Next, an outline of the operation of the power transmitting side and the power receiving side will be described using a flowchart of Fig. 4. When the power transmitting side is powered on and the power is turned on (step, temporary power transmission for position detection is performed (step S2). When the power is transmitted, the power supply voltage on the power receiving side rises, and the power receiving control device 5 is reset (step sii). Thus, the power receiving side sets the signal piQ to the h level and the signal P4Q to the high level. In the impedance state (step S12), the transistors TB2 and TB1 are both turned off, and the electrical connection between the transistor and the load 9 is interrupted. Next, the power receiving side uses the position detecting circuit 56 to determine the primary coil u and the secondary coil L2. Whether or not the positional relationship is appropriate (step S13). Then, in the case where the positional relationship is appropriate, the authentication process of the power-receiving side is turned on (4), and the authentication frame is transmitted to the power transmitting side (step S14). Specifically, the (4) 3 (b) The load modulation described in the above is used to transmit the information of the authentication frame. The judgment of the ID is the same when the power transmission side receives the authentication frame.
送至受電側（步驟S4)。具體而言， m況下，將允許訊框傳 係藉由圖3(A)中說明之 128612.doc •22- 200901597 頻率調制來傳送資料。 受電側接收允許訊框，其内容為〇K情況下，將開始無 接點電力傳送用之開始訊框傳送至送電側（步驟s丨5、 S16)。另外，送電側接收開始訊框，於其内容為〇κ情況 下，開始通常之電力傳送（步驟S5、S6)。而後，受電側將 訊號P1Q、P4Q設定成l位準（步驟S17)。藉此，因為電晶 體TB2、TB 1均接通，所以可對負載9〇傳送電力，而開始 對負載供給電力（VOUT之輸出）（步驟S18)。 3 ·振幅檢測 圖5顯示本實施形態之送電控制裝置2〇的具體結構例。 圖5中，振幅檢測電路28檢測感應電壓訊號pHIN之振幅資 Λ此日寸’一次線圈L1之電感及構成共振電路之電容器的 電容值參差不齊，或電源電壓等變動時，振幅檢測電路28 之檢測電壓（峰值電壓、振幅電壓、有效電壓）亦變動。因 此資料檢測、雜質檢測、裝卸檢測之判定用的基準臨限 值電壓（判定電壓）係固定值時，可能無法實現正確之檢 測。 因此本實施形嘘係採用如圖5所示地設置a/D轉換電路 29，在從暫行規定電壓（規格電壓）經過賦予之期間的時點 進行Α/t)轉換，以自動修正檢測判定用之基準臨限值電壓 的方法。 具體而言，設定圖6所示之暫行規定電壓SIGH〇。該暫 行規定電壓SIGH〇係圖2之受電裝置4〇的負載調制部“之 負載係無負載（TB3斷開）時的峰值電壓（廣義而t，為檢測 128612.doc -23- 200901597 電壓）’與係有負載（TB3接通）時之峰值電壓間的電壓，士 係SIGH0=2.5 V。另外，亦可藉由暫存器可變地設定暫行 規定電壓SIGH0。 A/D轉換電路29在從感應電壓訊號PHIN之峰值電壓（1 號PHQ)超過暫行規定電壓SIGH0之時點u經過賦予之期間 TP的轉換時點t2，進行峰值電壓之a/d轉換。而後，长出 基準臨限值電壓SIGHV的數位資料ADQ而輸出。閂鎖電路 30閂鎖該資料ADQ。控制電路22使用閂鎖之資料ADQ進疒 資料檢測、雜質檢測或裝卸檢測。亦即’檢測受電裝置Z 藉由負載調制而傳送之資料的「〇」、「！」，或是檢測放置 於充電器之一次線圈上的雜質（二次線圈以外之金屬），戋 是檢測放置於充電器上$Φ μ I ， 凡电态上之仃動電5舌尊之電子機器的裝 (取出）。 如在圖6之時點t0，受電側之負載調制部粍的電晶體丁扪 接通，或是從無負載（負载不連接）變成有負载（負載連接） 時’感應電壓訊號PHIN的峰值電壓上昇。圖6係設定檢測 此種峰值電壓之上昇用的暫行規定電壓sighq(暫行之臨限 值電壓）。该暫行S定電壓8職〇於受電側為無負載情況 下，係並未超過之電壓，峰值電壓超過sigh〇情況下，可 判斷為受電側確實地連接有負載。因&，在從該時點_ 過充分之期間TP，於峰值電屢之位準穩定的時點t2,進行 A/D轉換’求出基準臨限值電® SIGHV。具體而言， 電路22從超過暫行規定電壓臟〇之時點tl，使料㈣ ㈤開始計數處理（計數值之增量或減量）。而後，以在依: 128612.doc -24· 200901597 計數器1 02之計數值而設定的轉換時點t2進行A/D轉換之方 式，控制A/D轉換電路29，來求出基準臨限值電壓 SIGHV。 而後，控制電路22依據該基準臨限值電壓SIGHV進行資 料檢測、雜質檢測及裝卸檢測。具體而言，藉由對基準臨 限值電壓SIGHV減去或加上資料檢測用、雜質檢測用或裝 卸檢測用之參數電壓’而獲得貢料檢測用、雜質檢測用或 裝卸檢測用之臨限值電壓。而後，依據此等臨限值電壓， 進行資料檢測、雜質檢測及裝卸檢測之至少1個。 圖7顯示求出資料檢測用、過載檢測用、雜質檢測用、 裝卸檢測用之臨限值電壓VSIGH、VOVER、VMETAL、 VLEAVE用的臨限值表1 00之例。控制電路22使用該臨限值 表 100 求出 VSIGH、VOVER、VMETAL 及 VLEAVE。如資 料檢測用之臨限值電壓VSIGH藉由對基準臨限值電壓 SIGHV減去資料檢測用之參數電壓PV1而求出。同樣地， VOVER藉由對SIGHV加上過載檢測用之參數電壓PV2而求 出，VMETAL藉由對SIGHV加上雜質檢測用之參數電壓 PV3而求出，VLEAVE藉由對SIGHV減去裝卸檢測用之參 數電壓PV4而求出。 另外，本實施形態係首先進行過載檢測，於檢測出過載 時，進行電壓檢測電路14之電壓分割節點的切換控制，並 進行雜質檢測、裝卸檢測。此時參數電壓PV1、PV2、 PV3、PV4如可設定成 0·3 V、0.8 V、0.8 V、0.1 V。如 SIGHV=3.0 V情況下，VSIGH=3.0-0.3=2.7 V，資料檢測用 128612.doc -25- 200901597 之臨限值電壓VSIGH形成基準臨限值電壓SIGHV (3.0 V)與 暫行規定電壓SIGH0 (2.5 V)間之電壓。 藉由以上之本實施形態的方法，於線圈之電感及電容器 之電容值及電源電壓變動時，因應其變動，基準臨限值電 壓SIGHV亦變化，藉由SIGHV而求出之資料檢測用、雜質 檢測用、裝卸檢測用的臨限值電壓VSIGH、VMETAL、 VL£ AV£亦變化。亦即，因應依元件參差不齊等而變化之 基準臨限值電壓SIGHV，來自動修正臨限值電壓VSIGH、 VMETAL、VLEAVE。藉此，可自動地吸收元件參差不 齊，而可實現穩定之檢測動作。此外，基準臨限值電壓 SIGHV之A/D轉換，係在使用SIGH0確實地檢測出受電側 之負載從無負載變成有負載的時點tl，經過充分之期間TP 的時點t2進行。因此，可防止檢測出錯誤之基準臨限值電 壓SIGHV的情形，而可實現無錯誤檢測之穩定的檢測動 作。 另外，在二次線圈L2靠近一次線圈L1之過程及設有雜質 情況下，有時峰值電壓超過暫行規定電壓SIGH0。但是， 此種情況下，因為其以後之負載調制的程序與預先規定之 程序不一致，所以成為ID認證錯誤，因為須再起動，所以 不致發生問題。 此外，圖6係顯示振幅檢測電路2 8之檢測電壓係峰值電 壓的情況例，不過，振幅資訊不限定於峰值電壓，只須為 表示感應電壓訊號之振幅大小的物理量即可。如振幅資訊 亦可為表示感應電壓訊號之電力的有效電壓，亦可為感應 128612.doc -26- 200901597 電壓訊號之振幅電壓本身。 4.詳細之結構例 圖8顯示振幅檢測電路28、A/D轉換電路29之詳細結構 例。圖8中，振幅檢測電路28包含：運算放大器OPA1、 OPA2、保持電容器CA1及重設用之N型的電晶體TA1。運 算放大器OPA1在其非反轉輸入端子上輸入訊號PHIN，在 其反轉輸入端子上連接運算放大器OPA2之輸出節點NA5。 保持電容器CA1及重設用電晶體TA1設於運算放大器OPA1 之輸出節點的峰值電壓之保持節點NA4與GND(低電位側 電源）之間。運算放大器OPA2在其非反轉輸入端子上連接 保持節點NA4，在其反轉輸入端子上連接OPA2的輸出節點 NA5，而構成電壓輸出器連接的運算放大器。另外，亦可 在運算放大器OPA2之後段進一步設置電壓輸出器連接的 運算放大器。 藉由圖8之運算放大器OPA1、OPA2、保持電容器CA1及 重設用電晶體TA1而構成峰值保持電路（峰值檢測電路）。 亦即，來自電壓檢測電路1 4之檢測訊號PHIN的峰值電壓 保持於保持節點NA4，該保持之峰值電壓的訊號藉由電壓 輸出器連接之運算放大器OPA2實施阻抗轉換，並輸出至 節點NA5。 重設用電晶體ΤΑ 1在重設期間接通，將保持節點NA4之 電荷放電於GND側。亦即，運算放大器OPA1僅係在保持 電容器CA1中貯存電荷，而無法將電荷放電於GND側之類 型的運算放大器。因而，雖可追隨訊號PHIN之峰值電壓 128612.doc -27- 200901597 的亡昇，但是無法追隨峰值電壓的下降。此外，因為設於 運算放大器OPA1之輸出部的電荷貯存用之p型的電晶體中 存在漏電流，所以該P型電晶體斷開情況下，於經過長時 間後’保持節點NA4之電壓亦上昇。目而，需要定期地重 設保持節點NA4之電壓。基於以上之理由，圖8中在保持 節點NA4上設有重設用之電晶體TA1。 如本實施形態係受電側從送電側之交流電壓檢測（抽出） 時脈，並與該時脈同步進行負載調制。因此，受電側之負 載調制與送電側之時脈同步地進行，所以送電側可唯一地 瞭解受電側之負載調制的時點。因此，控制電路2 2特定受 電側之負載調制之負載的切換時點，在包含特定之切換時 點之重設期間，進行將保持節點NA4之電荷放電於gnd侧 的重設控制。藉此，採用無法追隨峰值電壓之下降類型的 運算放大器OPA1情況下，亦可實現適當之峰值保持動 作。此外，在等待峰值電壓超過暫行規定電壓81(}}1〇的待 機模式時，藉由定期地重設保持節點NA4之電壓，可防止 因運算放大器OPA1之P型電晶體之漏電流造成保持電壓之 上昇。 圖9顯示說明振幅檢測電路28之動作用的訊號波形例。 如圖9所示，訊號PHIN為藉由半波整流電路之電壓檢測電 路14而半波整流的訊號。運算放大器〇pA1之輸出訊號〇pQ 在訊號PHIN之脈衝發生期間，其電壓上昇，在脈衝不發 生期間，其電麼被保持電容器CAI保持而維持。而後，運 算放大器OPA2之輸出訊號PHQ平滑地追隨訊號pmN之峰 128612.doc •28- 200901597 值。 A/D轉換電路29包含：抽樣保持電路110 '比較器 CPA1、逐次比較暫存器ii2、d/a轉換電路114。抽樣保持 電路110抽樣訊號PHQ而保持。比較器cpai比較來自d/a 轉換電路114之D/A轉換後的類比訊號DAq與來自抽樣保持 電路no之抽樣保持訊號SHQ。逐次比較暫存器ιΐ2(逐次比 較控制電路）储存比較器CPA1之輸出訊號CQl0ijf料。d/a 轉換電路114將來自逐次比較暫存器112之如8位元的數位 貝料SAQ予以d/A轉換後，輸出類比訊號DAQ。 該逐次比較型之A/D轉換電路29由比較器cpAi比較僅 MSB(最上階位元）為時之〇/Α轉換後的訊號daq與輸 入訊號SHQ (PHQ)。而後只要訊號SHQ之電壓大時，msb 仍為1」’小柃則MSB為「〇」。而後，八/1}轉換電路29就 以後之下階位it亦同樣地逐次進行比較處理。而後，將最 後獲得之數位資料ADQ輸出至閃鎖電路3〇。另外，a/d轉 換電路29不限定於圖8之結構，如亦可為不同電路結構之 逐次比較型A/D轉換轉’亦可為追隨比較型、並列比較 型、雙重積分型等之A/D轉換電路。 圖1〇顯示說明圖8之電路動作用的訊號波形例。在時點 tU ’重設訊號RST形成L位準（非主動），解除重設時，峰 值電壓之訊號PHQ稱微上昇。在其後之時點U2,受電側 (二次側）從無負載變成有負載時，峰值電壓進一步上昇， 在時點U3,超過暫行規定電麗SlGH〇_，計數器ι〇2開始 計數動作。而後，在經過期間τρι(如1〇4clk)的重設時點 128612.doc -29- 200901597 tl4，訊號RST形成Η位準（主動），電晶體TA1接通，保持節 點NA4之電荷放電於GND側。藉此，峰值電壓暫時下降。 而後，經過重設期間TP2(如32CLK)，而到達時點tl5時， 因為受電側仍然有負載，所以峰值電壓再度上昇。其後， 在經過期間TP3(如32CLK)的轉換時點tl6，A/D轉換電路 29開始A/D轉換，求出基準臨限值電壓SIGHV之數位資 料。而後，在經過期間TP4(如64CLK)的時點tl7，閂鎖訊 號LAT形成Η位準（主動），基準臨限值電壓SIGHV之數位資 料被閂鎖電路30閂鎖。 如此，圖1 0係在從峰值電壓（PHQ)超過暫行規定電壓 SIGH0的時點，經過第一期間ΤΡ1之重設時點U4，進行將 保持節點NA4之電荷放電於低電位側電源的重設控制。而 後，在從重設時點tl4經過第二期間（TP2 + TP3)的轉換時點 tl6，進行峰值電壓之A/D轉換，而求出基準臨限值電壓 SIGHV之數位資料。 亦即，從超過暫行規定電壓SIGH0起，經過期間TP1 後，設置重設期間TP2，暫時重設保持節點NA4之電壓。 而後，於期間TP3中等待振幅檢測電路28(峰值保持電路） 之輸出穩定，其後，起動A/D轉換電路29，進行A/D轉 換。藉此，因為重設保持節點NA4之電壓，可於峰值電壓 穩定後進行A/D轉換，所以可提高基準臨限值電壓SIGHV 之檢測精度。 5.第一種改良例 圖11顯示本實施形態之第一種改良例。與圖8不同之處 128612.doc •30- 200901597 為：電壓檢測電路14之結構與增設開關電路SWl、SW2。 圖11之電壓檢測電路14設於一次線圈L1之一端的節點 NA2與GND(低電位側電源）之間，且包含串聯連接之電阻 RA1、RA2、RA3。藉由此等電阻rai、RA2、RA3而構成 電壓分割電路。而後’將一次線圈L1之感應電壓訊號 PHIN1、PHIN2(半波整流訊號）輸出至電壓分割電路之電 壓分割節點NA3 1、NA32。而後，控制電路22在資料檢測 時，及雜質檢測、裝卸檢測時，以將來自不同之電壓分割 節點的感應電壓訊號輸入振幅檢測電路28之方式，進行切 換控制。 具體而言’於資料檢測情況下，開關電路Swi接通（導 通狀悲）’來自第一電壓分割節點NA3 1之訊號PHIN1，作 為訊號PHIN而輸入振幅檢測電路28，來檢測峰值電壓（振 幅資訊）。另外，在雜質檢測及裝卸檢測等之過載檢測情 況下，開關電路SW2接通，來自第二電壓分割節點NA32 之afl號PHIN2作為sfL號PHIN而輸入振幅檢測電路28，來檢 測峰值電壓（振幅資訊）。 另外，開關電路SW1、SW2如可藉由共通連接p型電晶 體與N型電晶體之汲極及源極的轉移閘（transfer gate)等而 構成。此外，開關電路SW1 ' SW2之接通、斷開藉由來自 控制電路22之開關讯號SC 1、SC2而控制。亦即，係藉由 開關訊號SCI、SC2來控制構成開關電路SW1、SW2之電晶 體的接通、斷開。 圖12顯示說明第-種改良例之動作用的流程圖。圖^之 128612.doc -31 - 200901597 處理係在通常之資料檢測模式的狀態下經常進行之處理。 首先，接通開關電路SW1，並斷開開關電路S W2(步驟 S21)。此等之接通、斷開控制藉由來自控制電路22之開關 訊號SC 1、SC2而進行。藉此，來自電壓分割節點NA3 1之 訊號PHIN1作為訊號PHIN，而輸入振幅檢測電路28，可檢 測來自受電側之傳送資料。 其次，判斷峰值電壓訊號PHQ是否超過圖7中說明之過 載檢測用之臨限值電壓VOVER(步驟S22)。而後，如連續3 次（廣義而言為數次）判斷為超過情況下，判斷為過載狀 態，而斷開開關電路SW1，並接通開關電路SW2(步驟 S23)。藉此，將來自電壓分割節點NA32之訊號PHIN2作為 訊號PHIN，而輸入振幅檢測電路28，可進行雜質檢測及 裝卸檢測等之過載狀態的檢測。 其次，判斷峰值電壓訊號PHQ是否超過圖7中說明之雜 質檢測用的臨限值電壓VMETAL(步驟S24)。而後，如連續 3次（數次）判斷為超過情況下，判斷為存在雜質，進行使警 告雜質存在之紅色LED點亮的控制（步驟S25)。而後，回到 ID認證前之初始狀態模式（如圖4之步驟S2)。 另外，峰值電壓訊號PHQ未超過VMETAL之情況下，判 斷PHQ是否超過裝卸檢測用之臨限值電壓VLEAVE(步驟 S26)，未超過情況下回到步驟S2 1。藉此，開關電路S W1 接通，開關電路SW2斷開，而回到通常之資料檢測模式。 另外，於PHQ超過VLEAVE情況下，判斷為進行了電子機 器之裝卸（取出）（步驟S27)。而後，回到ID認證前之初始狀 128612.doc -32- 200901597 態模式。 如此，第一種改良例首先係進行切換控制，將來自第一 電壓分割節點NA31的感應電壓訊號醜犯輸入振幅檢測電 路28(步驟21)。而後，以該狀態檢測出過載之情況下（步驟 . S22)，料㈣控制，將來自與第—電壓分割節點na3i 不同之第二電塵分割節點NA32的感應電壓訊號p麵2輸入 振幅檢測電路28(步驟S23)，進行雜質檢測、裝卸檢測（步 驟 S24〜S27) 〇 亦即，過載狀態時之峰值電壓遠比資料檢測時大。因 此，不變更電壓分割節點，而欲使用運算放大器咖、 OPA2檢測過載狀態之峰值電壓時，運算放大器〇pAi、 OPA2之動作範圍的設計困難。 就切·一點，圖11、圖12係在判定為過載狀態情況下，以 來自比貝料檢測之電壓分割節點Na3 i更低電位側的電壓 分割節點NA32的訊號PHIN2檢測峰值電壓。如此，變更電 壓分割節點時，即使線圈端電壓高時，輸入振幅檢測電路 28之甙號的峰值降低。因此，可使用共用之運算放大器 OPA1、OPA2實現過載狀態之雜質檢測及裝卸檢測，而可 輕易地設計運算放大器之動作範圍。 6.第二種改良例 圖13顯示本實施形態之第二種改良例。該第二種改良例 除了感應電壓訊號之振幅檢測之外，亦進行脈寬檢测。圖 13與圖8不同之處為：增設波形整形電路％、脈寬檢測電 路33閂鎖電路34等。另外，亦可實施組合圖丨丨之第一種 128612.doc •33- 200901597 改良例與圖13之第一種改良例的改良。此外’第二種改良 例之結構不限定於圖13，如亦可省略A/D轉換電路29及波 $整形電路32等之構成要素，如亦可取代換電路 29,而設置比較峰值電壓與臨限值電塵之數個比較器。 波形正形電路32將一次線圈u之感應電壓訊號]?1^以（線 圈端電壓）予以波形整形，而輸出波形整形訊號wfq。具 體而έ，如訊號PHIN超過賦予之臨限值電壓時，輸出形 成主動（如Η位準）之方形波（矩形波）的波形整形訊號wfq。 驅動時脈產生電路25產生規定一次線圈L1之驅動頻率的 驅動時脈DRCK。具體而言，將振盪電路24所產生之基準 時脈CLK予以分頻，而產生驅動時脈DRCK。一次線圈 中供給該驅動時脈DRCK之驅動頻率的交流電壓。 驅動器控制電路26依據驅動時脈DRCK產生驅動器控制 訊號，並輸出至驅動一次線圈L1之送電部12的送電驅動器 (第一、第二送電驅動器）。此時，係以貫穿電流不流入構 成送電驅動器之反相電路之方式，並以輸入反相電路之p 型電晶體的閘極之訊號與輸入N型電晶體的閘極之訊號彼 此形成不重疊之訊號的方式，產生驅動器控制訊號。 脈寬檢測電路33檢測一次線圈L1之感應電壓訊號PHIN 的脈寬資訊。具體而言，係接收來自波形整形電路32之波 形整形訊號WFQ與來自驅動時脈產生電路25之驅動時脈 DRCK ’藉由檢測波形整形訊號WFq之脈寬資訊，而檢測 感應電壓訊號PHIN之脈寬資訊。 更具體而言，脈寬檢測電路33藉由計測驅動時脈 128612.doc -34- 200901597 DRCK(驅動控制訊號）從非主動之電壓位準（如L位準）變成 主動之電壓位準(如职立準)的第—點(如上昇邊緣。開始驅 動點），至波形整形訊號WFQ從主動之電壓位準（如h位準） 變成非主動之電壓位準（如L位準）的第二點（如下降邊緣。 波形整形汛號之結束點)之期間的脈寬期『曰，’來檢測脈寬 資訊。如計測藉由驅動時脈DRCK之電壓變化而感應的電 壓訊號PHIN為賤予之臨限值電壓以上的脈寬期間。而 =，計測波形整形訊號WFQ(感應電壓訊號）之脈寬對驅動 %脈DRCK之脈寬的大小。此時之脈寬期間的計測如使用 土準％脈CLK進行。而後，脈寬檢測電路3 3計測結果之資 料PWQ閂鎖於閂鎖電路34。具體而言，脈寬檢測電路^藉 由基準時脈CLK ,使用進行計數值之增量（或減量）的計數 。。°十測脈寬期間，並將其計測結果之資料pWQ閂鎖於閂 鎖電路3 4。 控制電路22依據脈寬檢測電路33檢測出之脈寬資訊，檢 測二次側（受電裝置40側）之負載變動（負載之高低）。具體 而。，控制電路22係依據脈寬檢測電路33檢測出之脈寬資 訊，進行受電裝置40藉由負載調制而傳送之資料的檢測， 並依據振幅檢測電路2 8檢測出之振幅資訊，進行裝卸檢 測。 更具體而έ，控制電路22依據以脈寬檢測電路3 3檢測， 而門鎖於閂鎖電路34之脈寬期間的資料PWq(脈寬資訊）， 進仃貧料檢測。此外’使用藉由振幅檢測電路28、八/：〇轉 換電路29求出，而閂鎖於閂鎖電路3〇之基準臨限值電壓的 128612.doc -35- 200901597 數位貧料進行裝卸檢測。如求出圖7中說明之裝卸檢測用 的臨限值電壓，來進行裝卸檢測。 另外，圖13中，振幅檢測用之第一問鎖電路3〇藉由问鎖 訊號la丁】問鎖來自A/D轉換電㈣之資料娜（如基準臨 限值電屋之㈣）。此外，脈寬朗用之第q鎖電路34 精由問鎖訊號LAT2問鎖來自脈寬檢測電路3 3之 PWQ(脈寬期間之f料）。此時第二_電路μ在與第一閃 鎖電路30之問鎖時點同步的時點，問鎖來自脈寬檢測電路 =資料。具體而言’第一、第二閃鎖電路Μ藉由相 同k點之⑽訊號LAT1、LAT2^鎖資料。 如此’可在相同時點問鎖藉由脈寬檢測而獲得之資料與 藉由振幅檢測而獲得之資料，並輸入控制電路22。藉此:、 可保持脈寬檢測與振幅檢測間之電路互換性，並可簡化控 制電路22之程序處理及判斷處理。 工 θ ()圖14⑻顯7^次線®L1之線圈端波形的 圖⑷圖“(B)分別係受電側之負載電流為 15〇mA、3〇〇mA時的電屢波形。負載 載），線圈端電壓為賭； ^露疋问負 為R予之設定電壓VR以上的脈寬期間 TPW愈短。因此，藉由計測該脈寬期間 裝置40之負載調制部 1斷丈電 之傳送資料係「。二的負減’並可判斷來自受電侧 負載時传「〇 / 」。如圖3(B)所示，規定為低 負載時係〇」’向負栽時係Γ1」。此種情況 TPW比賦予之基乘晰眢w 肌見期間 Α「Λ r办 _間長時’為低負載’所以可判斷 為 〇」’脈寬期間短拉*丄 辦 時為鬲負載’所以可判斷為「1 128612.doc -36 - 200901597 顯示驅動時脈DRCK(驅動控制訊號）與線圈端 之關係。驅動時脈聰K在時點位準（主 動）士，在時點t2#L位準（非主動）。另外，線圈端電屋在驅 動％脈DRCK為H位準的時點⑵急遽地上昇，其後下降。 而後’如圖15所示，受電側之負載愈低，線圈端電壓之下 降愈緩慢。因,，受電側之負載愈低，線圈端電壓（感應 電壓汛唬)為賦予之設定電壓以上的脈寬期間愈長。因 此’藉由計測該脈寬期間，可判斷受電側之負載係低負 載、中負載、高負載或過載之哪一個。 如亦有以負載之相位特性判斷受電側之負載變動的方 法。此處，所謂負載之相位特性，係指電屢、電流相位差 者’不過，該方法有電路結構複雜，_高成本 題。 對於此’本實施形態之脈寬檢測方法，因為係利用電壓 波开/可Μ早之波形整形電路與計數電路（計數器）作為 數位，料來處理’所以具有可簡化電路結構之優點。此 外，還具有容易實現與使用電塵波形檢測負載變動之振幅 檢測方法組合的優點。 另外，計測脈寬期間用之設定電-VR(如〇 ¥以上之電 壓。N型電晶體之臨限值電壓以上的電壓），只須適切選擇 負載變動之檢測精度為最佳的電壓來設定即可。 圖16顯示第二種改良例之具體結構例。圖16係波形整形 電路32包含：串聯連接於卿（高電位側電源）與gnd間之 電阻RC1及N型電晶體TC1、與反相電路INVC。在電晶體 128612.doc •37· 200901597 TC1之閘極中輸入來自電壓檢測電路14之訊號。而 後，甙唬PHIN比電晶體Tc丨之臨限值電壓高時，因為TC i 接通節點NC1之電壓形成L位準，所以波形整形訊號 WFQ形成η位準。另外，訊號pHiN比臨限值電壓低時，波 形整形訊號WFQ形成L位準。 另外，波形整形電路32不限定於圖16之結構。如亦可藉 由在其非反轉輸入端子（第一端子）上輸入訊號pHIN，在其 反轉輸入端子（第二端子）上輸入設定電壓VR的比較器而構 成波形整形電路32。因為使用此種比較器時，可任意地調 整设定電壓VR，所以可提高負載變動之檢測精度。 脈寬檢測電路33包含計數器122。該計數器122在脈寬期 間進行计數值之增量（或減量），並依據獲得之計數值計測 脈寬期間之長度。此時，計數器122如依據基準時脈cLK 進行計數值之計數處理。 更具體而言，脈寬檢測電路33包含賦能訊號產生電路 12〇。忒賦能汛唬產生電路i20接收波形整形訊號WFq與驅 動時脈DRCK，在脈寬期間產生成為主動之賦能訊號 ENQ。而後，計數器122於賦能訊號ENQ係主動（如H位準） 時’進行計數值之增量（或減量）。 該賦能訊號產生電路120可藉由在其時脈端子上輸入驅 動時脈DRCK，在其資料端子上輸入VDD(廣義而言，為高 電位側電源）的電壓，於波形整形訊號WFQ係非主動（匕位 準）時重設之正反器電路FFC1而構成。藉由該正反器電路 FFC1，於波形整形訊號WFQ形成主動（H位準）後，驅動時 128612.doc -38^ 200901597 脈DRCK形成主動（H位準盆It is sent to the power receiving side (step S4). Specifically, in the case of m, the frame transmission is allowed to transmit data by the frequency modulation of 128612.doc •22-200901597 illustrated in Fig. 3(A). When the power receiving side receives the permission frame and the content is 〇K, the start frame for starting the contactless power transmission is transmitted to the power transmitting side (steps s5, S16). Further, the power transmission side receives the start frame, and when the content is 〇 κ, the normal power transmission is started (steps S5 and S6). Then, the power receiving side sets the signals P1Q and P4Q to the l level (step S17). Thereby, since both of the electric crystals TB2 and TB1 are turned on, power can be transmitted to the load 9〇, and power supply (output of VOUT) is started to be supplied to the load (step S18). 3. Amplitude Detection Fig. 5 shows a specific configuration example of the power transmission control device 2A of the present embodiment. In FIG. 5, the amplitude detecting circuit 28 detects the amplitude of the induced voltage signal pHIN, and the amplitude detecting circuit 28 when the inductance of the primary coil L1 and the capacitance of the capacitor constituting the resonant circuit are uneven or the power supply voltage or the like fluctuates. The detection voltage (peak voltage, amplitude voltage, effective voltage) also varies. Therefore, when the reference threshold voltage (judgment voltage) used for data detection, impurity detection, and loading and unloading detection is a fixed value, correct detection may not be possible. Therefore, in the present embodiment, the a/D conversion circuit 29 is provided as shown in FIG. 5, and the Α/t) conversion is performed at the time when the temporary predetermined voltage (specification voltage) is supplied, to automatically correct the detection and determination. The method of benchmarking the threshold voltage. Specifically, the provisional predetermined voltage SIGH 所示 shown in FIG. 6 is set. The provisional predetermined voltage SIGH〇 is the peak voltage at the time of no load (TB3 disconnection) of the load modulation unit of the power receiving device 4A of FIG. 2 (generalized t, for detecting 128612.doc -23-200901597 voltage) The voltage between the peak voltages when the load (TB3 is turned on) is set to SIGH0 = 2.5 V. Alternatively, the temporary regulation voltage SIGH0 can be variably set by the register. The A/D conversion circuit 29 is in the slave. When the peak voltage of the induced voltage signal PHIN (PHQ No. 1) exceeds the temporary regulation voltage SIGH0, the peak voltage a/d conversion is performed after the transition time t2 of the period TP is applied. Then, the reference threshold voltage SIGHV is generated. The digital data is outputted by the ADQ. The latch circuit 30 latches the data ADQ. The control circuit 22 uses the data of the latch ADQ to perform data detection, impurity detection or loading and unloading detection, that is, 'detecting the power receiving device Z to be transmitted by load modulation. "〇", "!" of the data, or the impurity placed on the primary coil of the charger (metal other than the secondary coil), and the detection is placed on the charger for $Φ μ I , where it is electrically仃动电5舌The electronic device mounted (removed). At time t0 in Fig. 6, the transistor of the load modulation unit 受 on the power receiving side is turned on, or the peak voltage of the induced voltage signal PHIN rises when there is no load (load is not connected) and there is load (load connection). . Fig. 6 is a tentative predetermined voltage sighq (temporary threshold voltage) for detecting the rise of such a peak voltage. In the case where the power receiving side is no-load, the voltage is not exceeded, and if the peak voltage exceeds sigh, it can be judged that the load is reliably connected to the power receiving side. When &, during the period _ from the time point _ is sufficient, the A/D conversion is performed at the time point t2 at which the peak electric power level is stable, and the reference threshold electric power SIGHV is obtained. Specifically, the circuit 22 starts the counting process (increment or decrement of the count value) from the time t1 when the temporary prescribed voltage is exceeded, and the material (4) (f) is started. Then, the A/D conversion circuit 29 is controlled to obtain the reference threshold voltage SIGHV by performing A/D conversion at the conversion time t2 set by the counter value of the counter value of 128612.doc -24· 200901597. . Then, the control circuit 22 performs data detection, impurity detection, and detachment detection based on the reference threshold voltage SIGHV. Specifically, by subtracting or adding the parameter voltage 'for data detection, impurity detection, or detachment detection to the reference threshold voltage SIGHV, the threshold for the detection of the fascia, the detection of the impurity, or the detection of the detachment is obtained. Value voltage. Then, based on the threshold voltages, at least one of data detection, impurity detection, and loading and unloading detection is performed. Fig. 7 shows an example of the threshold value table 100 for determining the threshold voltages VSIGH, VOVER, VMETAL, and VLEAVE for data detection, overload detection, impurity detection, and detachment detection. The control circuit 22 uses the threshold table 100 to find VSIGH, VOVER, VMETAL, and VLEAVE. The threshold voltage VSIGH for the material detection is obtained by subtracting the parameter voltage PV1 for data detection from the reference threshold voltage SIGHV. Similarly, VOVER is obtained by adding the parameter voltage PV2 for overload detection to SIGHV, and VMETAL is obtained by adding parameter voltage PV3 for impurity detection to SIGHV, and VLEAVE is used for SIGHV minus loading and unloading detection. The parameter voltage PV4 is obtained. Further, in the present embodiment, the overload detection is first performed, and when the overload is detected, the switching control of the voltage division node of the voltage detecting circuit 14 is performed, and the impurity detection and the detachment detection are performed. At this time, the parameter voltages PV1, PV2, PV3, and PV4 can be set to 0·3 V, 0.8 V, 0.8 V, and 0.1 V. For example, when SIGHV=3.0 V, VSIGH=3.0-0.3=2.7 V, the threshold voltage VSIGH for data detection 128612.doc -25- 200901597 forms the reference threshold voltage SIGHV (3.0 V) and the interim regulated voltage SIGH0 ( Voltage between 2.5 V). According to the method of the present embodiment, when the inductance of the coil and the capacitance value of the capacitor and the power supply voltage fluctuate, the reference threshold voltage SIGHV also changes, and the data detection and impurity obtained by SIGHV are obtained. The threshold voltages VSIGH, VMETAL, and VL £ AV £ for detection and handling detection also change. That is, the threshold voltages VSIGH, VMETAL, and VLEAVE are automatically corrected in accordance with the reference threshold voltage SIGHV which varies depending on the components. Thereby, the components can be automatically absorbed and the stable detection operation can be realized. In addition, the A/D conversion of the reference threshold voltage SIGHV is performed by using SIGH0 to reliably detect the time t1 at which the load on the power receiving side changes from no load to load, and the time t2 when the sufficient period TP is passed. Therefore, it is possible to prevent the detection of the erroneous reference threshold voltage SIGHV, and it is possible to realize a stable detection operation without error detection. Further, in the case where the secondary coil L2 is close to the primary coil L1 and the presence of impurities, the peak voltage may exceed the provisional predetermined voltage SIGH0. However, in this case, since the program of the load modulation in the future does not coincide with the program specified in advance, it becomes an ID authentication error, and since it is necessary to restart, there is no problem. Further, Fig. 6 shows an example of the case where the detection voltage is the peak voltage of the amplitude detecting circuit 28. However, the amplitude information is not limited to the peak voltage, and it is only necessary to be a physical quantity indicating the magnitude of the amplitude of the induced voltage signal. For example, the amplitude information can also be the effective voltage of the power indicating the induced voltage signal, or the amplitude voltage itself of the voltage signal. 4. Detailed Configuration Example Fig. 8 shows a detailed configuration example of the amplitude detecting circuit 28 and the A/D converting circuit 29. In FIG. 8, the amplitude detecting circuit 28 includes operational amplifiers OPA1, OPA2, a holding capacitor CA1, and an N-type transistor TA1 for resetting. The operational amplifier OPA1 inputs the signal PHIN at its non-inverting input terminal and the output node NA5 of the operational amplifier OPA2 at its inverted input terminal. The holding capacitor CA1 and the reset transistor TA1 are provided between the holding node NA4 of the output node of the operational amplifier OPA1 and the GND (low potential side power supply). The operational amplifier OPA2 is connected to the non-inverting input terminal to hold the node NA4, and its inverting input terminal is connected to the output node NA5 of the OPA2 to form an operational amplifier to which the voltage output is connected. Alternatively, an operational amplifier to which the voltage output device is connected may be further provided in the subsequent stage of the operational amplifier OPA2. The peak hold circuit (peak detection circuit) is constituted by the operational amplifiers OPA1, OPA2, the holding capacitor CA1, and the reset transistor TA1 of Fig. 8. That is, the peak voltage of the detection signal PHIN from the voltage detecting circuit 14 is held at the holding node NA4, and the signal of the held peak voltage is impedance-converted by the operational amplifier OPA2 connected to the voltage output, and output to the node NA5. The reset transistor ΤΑ 1 is turned on during the reset period, and discharges the charge of the holding node NA4 to the GND side. That is, the operational amplifier OPA1 is only an operational amplifier of a type in which the charge is stored in the holding capacitor CA1 and the electric charge cannot be discharged to the GND side. Therefore, although the peak voltage of the signal PHIN 128612.doc -27- 200901597 can be followed, it cannot follow the drop of the peak voltage. In addition, since there is a leakage current in the p-type transistor for storing the charge in the output portion of the operational amplifier OPA1, the voltage of the node NA4 is also increased after a long period of time after the P-type transistor is turned off. . Therefore, it is necessary to periodically reset the voltage of the holding node NA4. For the above reasons, the reset transistor TA1 is provided on the holding node NA4 in Fig. 8 . In the present embodiment, the power receiving side detects (extracts) the clock from the AC voltage on the power transmitting side, and performs load modulation in synchronization with the clock. Therefore, since the load modulation on the power receiving side is synchronized with the clock on the power transmitting side, the power transmitting side can uniquely know the timing of the load modulation on the power receiving side. Therefore, the control circuit 22 specifies the switching timing of the load modulation load on the power receiving side, and resets the charge of the holding node NA4 to the gnd side during the reset period including the specific switching timing. Therefore, in the case of the operational amplifier OPA1 which cannot follow the type of the falling of the peak voltage, an appropriate peak hold operation can be realized. In addition, while waiting for the standby mode in which the peak voltage exceeds the temporary predetermined voltage 81 (}} 1 ,, by periodically resetting the voltage of the holding node NA4, the holding voltage due to the leakage current of the P-type transistor of the operational amplifier OPA1 can be prevented. Fig. 9 shows an example of a signal waveform for explaining the operation of the amplitude detecting circuit 28. As shown in Fig. 9, the signal PHIN is a half-wave rectified signal by the voltage detecting circuit 14 of the half-wave rectifying circuit. Operational amplifier 〇pA1 The output signal 〇pQ rises during the pulse of the signal PHIN, and is maintained by the holding capacitor CAI while the pulse is not occurring. Then, the output signal PHQ of the operational amplifier OPA2 smoothly follows the peak of the signal pmN. 128612.doc • 28- 200901597 The A/D conversion circuit 29 includes a sample and hold circuit 110' comparator CPA1, a successive comparison register ii2, and a d/a conversion circuit 114. The sample and hold circuit 110 samples the signal PHQ and holds it. The comparator cpai compares the D/A converted analog signal DAq from the d/a conversion circuit 114 with the sample hold signal SHQ from the sample and hold circuit no. The successive comparison is temporarily stored. The ιΐ2 (sequential comparison control circuit) stores the output signal CQ1Ojf of the comparator CPA1. The d/a conversion circuit 114 d/A converts the digital bit material SAQ of the 8-bit element from the successive comparison register 112, and outputs Analog-to-digital signal DAQ. The successive comparison type A/D conversion circuit 29 compares only the MSB (the highest order bit) of the MSB (the highest order bit) with the converted signal daq and the input signal SHQ (PHQ). Then the signal is as follows. When the voltage of SHQ is large, msb is still 1"', and MSB is "〇". Then, the eighth/1} conversion circuit 29 compares the next order it is also performed successively. Then, it will be finally obtained. The digital data ADQ is output to the flash lock circuit 3. In addition, the a/d conversion circuit 29 is not limited to the structure of FIG. 8, and may be a successive comparison type A/D conversion turn for different circuit structures. An A/D conversion circuit of a parallel type, a double integral type, etc. Fig. 1A shows an example of a signal waveform for explaining the operation of the circuit of Fig. 8. At time tU 'reset the signal RST to form an L level (inactive), When the reset is released, the signal PHQ of the peak voltage is slightly increased. At the subsequent point U2, when the power receiving side (secondary side) changes from no load to load, the peak voltage further rises, and at time point U3, the temporary predetermined electric current S1GH〇_ is exceeded, and the counter ι〇2 starts counting operation. During the reset period τρι (such as 1〇4clk), 128612.doc -29- 200901597 tl4, the signal RST forms a Η level (active), the transistor TA1 is turned on, and the charge of the node NA4 is discharged on the GND side. Thereby, the peak voltage temporarily drops. Then, after the reset period TP2 (such as 32CLK) and the arrival time point t15, since the power receiving side still has a load, the peak voltage rises again. Thereafter, at the time t15 when the transition of the period TP3 (e.g., 32CLK) elapses, the A/D conversion circuit 29 starts A/D conversion, and the digital data of the reference threshold voltage SIGHV is obtained. Then, at time t17 of the period TP4 (e.g., 64CLK), the latch signal LAT forms a Η level (active), and the digital data of the reference threshold voltage SIGHV is latched by the latch circuit 30. As described above, Fig. 10 is a reset control for discharging the electric charge of the holding node NA4 to the low-potential side power supply at the time point U4 when the peak voltage (PHQ) exceeds the provisional predetermined voltage SIGH0 and the reset period of the first period ΤΡ1. Then, the A/D conversion of the peak voltage is performed at the transition time t15 from the reset time point t14 through the second period (TP2 + TP3), and the digital data of the reference threshold voltage SIGHV is obtained. That is, the reset period TP2 is set after the period TP1 elapses from the temporary regulation voltage SIGH0, and the voltage of the holding node NA4 is temporarily reset. Then, the output of the amplitude detecting circuit 28 (peak holding circuit) is stabilized in the period TP3, and thereafter, the A/D converting circuit 29 is activated to perform A/D conversion. Thereby, since the voltage of the holding node NA4 is reset, the A/D conversion can be performed after the peak voltage is stabilized, so that the detection accuracy of the reference threshold voltage SIGHV can be improved. 5. First Modification FIG. 11 shows a first modification of the embodiment. The difference from FIG. 8 is 128612.doc • 30- 200901597: the structure of the voltage detecting circuit 14 and the additional switching circuits SW1 and SW2. The voltage detecting circuit 14 of Fig. 11 is provided between the node NA2 at one end of the primary coil L1 and the GND (low potential side power supply), and includes resistors RA1, RA2, RA3 connected in series. The voltage division circuit is constructed by the equal resistances rai, RA2, and RA3. Then, the induced voltage signals PHIN1, PHIN2 (half-wave rectified signals) of the primary coil L1 are output to the voltage dividing nodes NA3 1 and NA32 of the voltage dividing circuit. Then, the control circuit 22 performs switching control such that the induced voltage signals from the different voltage division nodes are input to the amplitude detecting circuit 28 during data detection, impurity detection, and detachment detection. Specifically, in the case of data detection, the switch circuit Swi is turned on (conducted), the signal PHIN1 from the first voltage dividing node NA3 1 is input to the amplitude detecting circuit 28 as the signal PHIN to detect the peak voltage (amplitude information). ). Further, in the case of overload detection such as impurity detection and handling detection, the switch circuit SW2 is turned on, and the afl number PHIN2 from the second voltage division node NA32 is input as the sfL number PHIN to the amplitude detecting circuit 28 to detect the peak voltage (amplitude information). ). Further, the switch circuits SW1 and SW2 can be configured by commonly connecting a p-type electric crystal and a transfer gate of a source and a source of the N-type transistor. Further, the switching circuit SW1'SW2 is turned on and off by the switching signals SC1, SC2 from the control circuit 22. That is, the switching of the electric crystals constituting the switching circuits SW1 and SW2 is controlled by the switching signals SCI and SC2. Fig. 12 is a flow chart showing the operation of the first modified example. Figure ^128612.doc -31 - 200901597 Processing is often performed in the normal state of data detection mode. First, the switch circuit SW1 is turned on, and the switch circuit S W2 is turned off (step S21). These on/off control is performed by the switching signals SC 1 and SC2 from the control circuit 22. Thereby, the signal PHIN1 from the voltage division node NA3 1 is used as the signal PHIN, and the amplitude detecting circuit 28 is input to detect the transmission data from the power receiving side. Next, it is judged whether or not the peak voltage signal PHQ exceeds the threshold voltage VOVER for overload detection explained in Fig. 7 (step S22). Then, if it is judged to be overloaded three times (in a broad sense, several times in a broad sense), the switch circuit SW1 is turned off, and the switch circuit SW2 is turned on (step S23). Thereby, the signal PHIN2 from the voltage division node NA32 is used as the signal PHIN, and is input to the amplitude detecting circuit 28, thereby detecting the overload state such as impurity detection and detachment detection. Next, it is judged whether or not the peak voltage signal PHQ exceeds the threshold voltage VMETAL for impurity detection described in Fig. 7 (step S24). Then, if it is judged to be excessive if it is judged to be excessive for three times (several times), control for lighting the red LED in which the warning impurity is present is performed (step S25). Then, return to the initial state mode before ID authentication (step S2 of Figure 4). When the peak voltage signal PHQ does not exceed VMETAL, it is determined whether or not the PHQ exceeds the threshold voltage VLEAVE for the detachment detection (step S26). If not, the process returns to step S2 1. Thereby, the switch circuit S W1 is turned on, and the switch circuit SW2 is turned off, and returns to the normal data detection mode. When the PHQ exceeds VLEAVE, it is determined that the electronic machine has been loaded (unloaded) (step S27). Then, return to the initial state before the ID authentication 128612.doc -32- 200901597 state mode. Thus, the first modified example first performs switching control to input the induced voltage signal from the first voltage dividing node NA31 into the amplitude detecting circuit 28 (step 21). Then, in the case where the overload is detected in this state (step S22), the material (4) is controlled, and the induced voltage signal p-plane 2 from the second electric dust dividing node NA32 different from the first voltage dividing node na3i is input to the amplitude detecting circuit. 28 (Step S23), impurity detection and detachment detection are performed (steps S24 to S27). That is, the peak voltage at the time of the overload state is much larger than that at the time of data detection. Therefore, when the voltage division node is not changed and the peak voltage of the overload state is detected using the operational amplifier and OPA2, the operation range of the operational amplifiers 〇pAi and OPA2 is difficult to design. In the case of the determination of the overload state, in Fig. 11 and Fig. 12, the peak voltage is detected by the signal PHIN2 from the voltage division node NA32 on the lower potential side of the voltage division node Na3 i than the bar-feed detection. As described above, when the voltage division node is changed, the peak value of the apostrophe of the input amplitude detecting circuit 28 is lowered even when the coil terminal voltage is high. Therefore, the shared operational amplifiers OPA1 and OPA2 can be used to detect and detect the overload in the overload state, and the operating range of the operational amplifier can be easily designed. 6. Second Modification Example Fig. 13 shows a second modification of the embodiment. In the second modification, in addition to the amplitude detection of the induced voltage signal, pulse width detection is also performed. 13 differs from FIG. 8 in that a waveform shaping circuit %, a pulse width detecting circuit 33 latch circuit 34, and the like are added. Further, the improvement of the first modification of the combination of the first type 128612.doc • 33-200901597 and the first modification of Fig. 13 can be carried out. Further, the configuration of the second modified example is not limited to FIG. 13, and constituent elements such as the A/D conversion circuit 29 and the wave shaping circuit 32 may be omitted, and the comparison peak voltage may be set instead of the replacement circuit 29. Several comparators for the limit electric dust. The waveform orthomorphic circuit 32 waveform-shapes the induced voltage signal of the primary coil u by (the coil terminal voltage), and outputs a waveform shaping signal wfq. Specifically, if the signal PHIN exceeds the threshold voltage given, the output forms a waveform shaping signal wfq of a square wave (rectangular wave) of an active (e.g., Η level). The drive clock generating circuit 25 generates a drive clock DRCK that defines the drive frequency of the primary coil L1. Specifically, the reference clock CLK generated by the oscillation circuit 24 is divided to generate a drive clock DRCK. The AC voltage of the driving frequency of the drive clock DRCK is supplied to the primary coil. The driver control circuit 26 generates a driver control signal in accordance with the drive clock DRCK, and outputs it to the power transmission driver (first and second power transmission drivers) that drive the power transmission portion 12 of the primary coil L1. In this case, the through-current does not flow into the inverter circuit constituting the power transmission driver, and the signal of the gate of the p-type transistor input to the inverter circuit and the signal of the gate of the input N-type transistor do not overlap each other. The signal is generated in a way that generates a drive control signal. The pulse width detecting circuit 33 detects the pulse width information of the induced voltage signal PHIN of the primary coil L1. Specifically, the waveform shaping signal WFQ from the waveform shaping circuit 32 and the driving clock DRCK' from the driving clock generating circuit 25 are detected by detecting the pulse width information of the waveform shaping signal WFq, and detecting the pulse of the induced voltage signal PHIN. Wide information. More specifically, the pulse width detecting circuit 33 changes from an inactive voltage level (such as an L level) to an active voltage level by measuring a driving clock 128612.doc -34 - 200901597 DRCK (drive control signal) (eg, The first point of the job (such as the rising edge. Start driving point), until the waveform shaping signal WFQ changes from the active voltage level (such as h level) to the inactive voltage level (such as the L level) The pulse width period "曰," during the period of two points (such as the falling edge. The end point of the waveform shaping nickname) is used to detect the pulse width information. For example, the voltage signal PHIN induced by the voltage change of the driving clock DRCK is measured as a pulse width period equal to or greater than the threshold voltage. And =, measure the pulse width of the waveform shaping signal WFQ (inductive voltage signal) to drive the pulse width of the % pulse DRCK. The measurement during the pulse width at this time is performed using the soil % pulse CLK. Then, the data PWQ of the measurement result of the pulse width detecting circuit 3 is latched to the latch circuit 34. Specifically, the pulse width detecting circuit ^ uses the count of the increment (or decrement) of the count value by the reference clock CLK. . During the measurement of the pulse width, the data pWQ of the measurement result is latched to the latch circuit 34. The control circuit 22 detects the load fluctuation (the level of the load) on the secondary side (the power receiving device 40 side) based on the pulse width information detected by the pulse width detecting circuit 33. Specifically. The control circuit 22 detects the data transmitted by the power receiving device 40 by load modulation based on the pulse width information detected by the pulse width detecting circuit 33, and performs the loading and unloading detection based on the amplitude information detected by the amplitude detecting circuit 28. More specifically, the control circuit 22 detects the data detected by the pulse width detecting circuit 33 and locks the data PWq (pulse width information) during the pulse width of the latch circuit 34. Further, the use of the amplitude detecting circuit 28 and the VIII/: 〇 switching circuit 29 is performed, and the digital threshold material is latched at the reference threshold voltage of the latch circuit 3 128 128612.doc -35 - 200901597. The threshold voltage for the detachment detection described in Fig. 7 is obtained, and the detachment detection is performed. In addition, in Fig. 13, the first interrogation circuit 3 for amplitude detection is caused by the information of the A/D conversion electric power (4), such as the reference threshold electric house (4). In addition, the q-lock circuit 34 of the pulse width is used to lock the PWQ (the material during the pulse width) from the pulse width detecting circuit 3 3 by the lock signal LAT2. At this time, the second _ circuit μ is synchronized with the time point of the lock of the first flash lock circuit 30, and the lock is from the pulse width detecting circuit = data. Specifically, the first and second flash lock circuits lock data by the (10) signals LAT1, LAT2^ at the same k point. Thus, the data obtained by the pulse width detection and the data obtained by the amplitude detection can be clicked at the same time and input to the control circuit 22. Thereby, the circuit interchangeability between the pulse width detection and the amplitude detection can be maintained, and the program processing and the judgment processing of the control circuit 22 can be simplified. Figure θ () Figure 14 (8) shows the waveform of the coil end of the 7 ^ sub-line ® L1 (4) Figure "(B) is the electric waveform of the load current of the power receiving side is 15 mA, 3 mA, respectively. Load load) The voltage at the coil end is gambling; the shorter the TPW is during the pulse width period of the set voltage VR above R. Therefore, by transmitting the data of the load modulation unit 1 of the device 40 during the measurement of the pulse width period It is "" negative minus" and can be judged to be "〇/" when it comes from the load on the power receiving side. As shown in Fig. 3(B), when the load is low, the system is set to "1" when the load is low. In this case, the TPW is more than the given factor. The muscles are seen during the period of the muscles. Λ Λ 办 办 _ 间 ' ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” It can be judged as "1 128612.doc -36 - 200901597 shows the relationship between the drive clock DRCK (drive control signal) and the coil end. The drive clock is at the time point (active), at the time point t2#L level ( In addition, the coil end electric house rises sharply when the drive %DR DRCK is at the H level (2), and then falls. Then, as shown in Fig. 15, the lower the load on the power receiving side, the lower the voltage at the coil end The slower the load on the power receiving side, the longer the coil end voltage (induced voltage 汛唬) is the pulse width period above the set voltage. Therefore, by measuring the pulse width period, it is possible to determine the power receiving side. The load is one of low load, medium load, high load or overload. For example, there is a method of determining the load variation on the power receiving side based on the phase characteristics of the load. Here, the phase characteristic of the load refers to the current and current phase difference. 'However, the method has a circuit The structure is complicated, _ high cost problem. For the pulse width detection method of the present embodiment, because the voltage wave open/precise waveform shaping circuit and the counting circuit (counter) are used as the digits, the material is processed, so It also has the advantage of simplifying the circuit structure. In addition, it has the advantage of being easy to combine with the amplitude detection method using the electric dust waveform to detect the load variation. In addition, the voltage-VR is set during the measurement of the pulse width (for example, the voltage above 。¥. N type The voltage above the threshold voltage of the transistor can be set only by appropriately selecting the voltage with the highest detection accuracy of the load variation. Fig. 16 shows a specific configuration example of the second modified example. Fig. 16 is a waveform shaping circuit. 32 includes: a resistor RC1 and an N-type transistor TC1 connected to the (high-potential side power supply) and gnd, and an inverter circuit INVC connected in series. The input voltage is input in the gate of the transistor 128612.doc • 37· 200901597 TC1 Detecting the signal of circuit 14. Then, when 甙唬PHIN is higher than the threshold voltage of transistor Tc丨, waveform shaping is performed because TC i turns on the voltage of node NC1 to form the L level. No. WFQ forms an η level. In addition, when the signal pHiN is lower than the threshold voltage, the waveform shaping signal WFQ forms an L level. In addition, the waveform shaping circuit 32 is not limited to the structure of Fig. 16. The input signal pHIN is input to the inverting input terminal (first terminal), and the comparator of the set voltage VR is input to the inverting input terminal (second terminal) to form the waveform shaping circuit 32. Since such a comparator is used, it can be arbitrarily Since the set voltage VR is adjusted, the detection accuracy of the load fluctuation can be improved. The pulse width detecting circuit 33 includes a counter 122. The counter 122 performs an increment (or decrement) of the count value during the pulse width, and measures the count value according to the obtained count value. The length of the pulse width period. At this time, the counter 122 performs the counting process of the count value according to the reference clock cLK. More specifically, the pulse width detecting circuit 33 includes an energization signal generating circuit 12A. The endurance generation circuit i20 receives the waveform shaping signal WFq and the driving clock DRCK, and generates an active energizing signal ENQ during the pulse width. Then, the counter 122 increments (or decrements) the count value when the energizing signal ENQ is active (e.g., H level). The enable signal generating circuit 120 can input a voltage of VDD (broadly speaking, a high-potential side power supply) at its data terminal by inputting a driving clock DRCK at its clock terminal, and the waveform shaping signal WFQ is not The flip-flop circuit FFC1 is reset when the active (positive level) is reset. With the flip-flop circuit FFC1, after the waveform shaping signal WFQ is formed into an active (H level), when driving, 128612.doc -38^200901597 pulse DRCK forms an active (H-level basin)
I + m ’、輙出訊唬之賦能訊號ENQ 〉 位準）。其後，於波形整形訊號w 動（L位準）時重設正反器電路FFCi， ^ ^非主 ^FNO^ ^ 具輸出訊旎之賦能訊 Q成非主動（L位準）。因此，計數itm藉由以基準 時脈cue计數賦能訊號ENQ為主動之期間，可計測脈寬期 間。 另外’亦可藉由在其時脈端子上輸入驅動時脈drck， 在其貧料端子上連接GND(低電位側電源），於波形整形訊 號WFQ係非主動時重設的正反器電路來構成賦能訊號產生 電路.此種情況下，只須將正反器電路之輪出訊號的 反轉W料賦能訊號ENQ而輸人計數器122即可。 計數值保持電路124保持來自計數器122之計數值 CNT(脈寬資訊）。而後，將保狀計數值的資㈣㈣出 至輸出電路126。 輸出電路126(遽波器電路、雜訊除去電路）接收被計數 值保持電路124保持之計數值的f#LTQ2，而輸出資料 PWQ。該輸出電路126如可包含比較此次保持於計數值保 持電路124之計數值與前次保持之計數值，而輸出大的一 方之計數值的比較電路130。藉此，可自輸出電路126保持 最大值之計數值而輸出。如此，可抑制因雜音等造成脈寬 期間之變動’而可實現敎之脈寬檢測。此外，亦可輕易 地與振幅檢測方法組合。 另外，亦可藉由求出保持於計數值保持電路124之數個 計數值的平均值（移動平均）之平均化電路而構成輸出電路 128612.doc •39- 200901597 126。 圖17顯示說明圖16之電路動作用的訊號波形例。在時點 ⑴波形整形訊號WFQ形成此準時，解除正反器電路 FFCM之重設。而後，在時點t32，於驅動時脈drck形成Η 位準時’在其上昇邊緣，VDD之電壓被引進正反器電路 FFCi，藉此，賦能訊號ENQ&L位準變成11位準。結果計 數器122開始計數處理’並使用基準時脈clk計測脈 間丁PW。 其次，在時點t33，波形整形訊號WFQ形成l位準時，重 設正反器電路FFC1，賦能訊號抓…^^位$變成l位準。 藉此，計數器122之計數處理結束。而後，藉由該計數處 理而獲得之計數值成為表示脈寬期間Tpw之計測結果。 同樣地® 17係藉由在時點m，波形整形訊號形 成Η位準，在時點t35，賦能訊號enq形成H位準，而開始 -十數處理其後’藉由在時點t36，波形整形訊號卿q及 賦能訊號ENQ形纽準，而結束計數處理。而彳卜藉由該 δ十數處理而獲得之計數值点主车- Τ数值成為表不脈寬期間tPw之計測結 果。 而後，如圖1 7所示，夸雷彳日丨^^ 々 又電側係低負載情況下，因為脈寬 期間TP W變長，所以計齡佶t傲丄 卞數值亦變大。另外，受電側係高負 載情況下，因為脈寬期喆Tpw嫩 見d間i PW變短，所以計數值亦變小。I + m ’, the signal of the output signal ENQ 〉 level). Thereafter, the flip-flop circuit FFCi is reset when the waveform shaping signal w (L level), ^ ^ non-main ^FNO^ ^ has the output signal Q is inactive (L level). Therefore, the count itm can measure the pulse width period by counting the energization signal ENQ with the reference clock cue as the active period. In addition, by inputting the driving clock drck on its clock terminal, GND (low potential side power supply) is connected to its poor terminal, and the flip-flop circuit is reset when the waveform shaping signal WFQ is inactive. The energizing signal generating circuit is formed. In this case, the counter 122 of the flip-flop signal of the flip-flop circuit is only required to be input to the counter 122. The count value holding circuit 124 holds the count value CNT (pulse width information) from the counter 122. Then, the capital (4) (4) of the guaranteed value is output to the output circuit 126. The output circuit 126 (chopper circuit, noise removing circuit) receives f#LTQ2 which is the count value held by the count value holding circuit 124, and outputs the data PWQ. The output circuit 126 may include a comparison circuit 130 that compares the count value held by the count value holding circuit 124 with the count value held last time, and outputs a larger one. Thereby, the output value can be outputted from the output circuit 126 while maintaining the maximum value. In this way, it is possible to suppress the variation of the pulse width period due to noise or the like, and to realize the pulse width detection of the chirp. In addition, it can be easily combined with the amplitude detection method. Alternatively, the output circuit 128612.doc • 39- 200901597 126 may be constructed by calculating an averaging circuit of the average value (moving average) of the count values held by the count value holding circuit 124. Fig. 17 is a view showing an example of a signal waveform for explaining the operation of the circuit of Fig. 16. At the time point (1) the waveform shaping signal WFQ forms this timing, and the reset of the flip-flop circuit FFCM is released. Then, at time t32, when the driving clock drck forms a Η level, 'at its rising edge, the voltage of VDD is introduced to the flip-flop circuit FFCi, whereby the energizing signal ENQ&L level becomes 11 level. As a result, the counter 122 starts counting processing ' and measures the inter-pulse PW using the reference clock clk. Next, at time t33, when the waveform shaping signal WFQ forms a 1-bit time, the flip-flop circuit FFC1 is reset, and the enable signal captures the ^^ bit to become the l-level. Thereby, the counting process of the counter 122 ends. Then, the count value obtained by the counting process becomes a measurement result indicating the pulse width period Tpw. Similarly, the 17 series is formed by the waveform shaping signal at the time point m, and at the time point t35, the energizing signal enq forms the H level, and the start-ten number processing is followed by the waveform shaping signal at the time point t36. Qing q and the empowerment signal ENQ shape, and end the counting process. The count value of the main vehicle-enthalpy value obtained by the δ-decimal processing becomes the measurement result of the period of the pulse width-free period tPw. Then, as shown in Fig. 17, after the low load of the electric side and the electric side, the TP W becomes longer during the pulse width, so the age of the aging is also increased. In addition, in the case of a high load on the power receiving side, since the pulse width period 喆Tpw is short, i PW becomes shorter, so the count value also becomes smaller.
因此，控制電路22可依壚捧楚也A 攸據此等计數值之大小來判斷受電側 之負載高低。 圖1 8(A)顯不脈寬之變姓沾 支化特性，圖18(B)顯示振幅之變化 128612.doc -40- 200901597 特性。圖18(A)之橫軸係受電側之負載電流量，縱軸為計 數益122之計數值（脈寬期間）。另外，圖J 8(B)之橫軸係受 電側之負載電流量，縱軸為線圈端電壓之振幅（峰值電 壓）。 圖18(A)之脈寬變化特性係如£1所示，負載電流量小， 而為低負載情況下，計數值對負載電流量之變化的變化率 大，靈敏度尚。另外，如E2所示，負載電流量大，而為高 負載情況下，計數值對負載電流量之變化的變化率小，靈 敏度低。其理由係因與正常之線圈結合時，藉由結合度之 限制，隨著負載加重’負栽-相位特性中之相位旋轉飽 和〇 另外，圖1 8(B)之振幅變化特性係如F1所示，於低負載 情况下線圈端電壓對負栽電流量之變化的變化率小，靈 敏度低。另外，如F2所示，於高負載情況下，計數值對負 載電流量之變化的變化率大，靈敏度高。 如此，脈寬檢測在低备發 -員载區域者之檢測靈敏度比高負載 區域高。另外，振幅檢測尤古 ^在同負载區域者之檢測靈敏度比 低負載區域南。因此，右你含也广t 在低負載區域負載變動情況下，須 使用脈寬檢測來判斷負巷 ^ 、 、戰之南低’在高負載區域負載變動 f月況下，須使用振幅檢測來古 、丨斷負載之局低。如此，藉由 在低負載區域與高負 貝戟&域分開使用檢測方 測負載變動。 、』名双概 具體而言’如檢測Μ 士含必 m…「々由負载調制而傳送之資料情況下， 在車父低負载之區域負載蠻 戰甏動。因此’就受電裝置40藉由負 128612.doc •41、 200901597 載調制所傳送之資料的檢測’須依據以脈寬檢測電路”檢 測出之脈寬資訊來進行。另外，裝卸檢測等之過载狀態情 況下，在高負載區域須靈敏度高，f尤裝卸檢測，須依據振 幅檢測電路28檢測出之振幅資訊來進行。藉此，可以高靈 敏度效率佳地實現資料檢測、雜質檢測及裝卸檢測等^ 另外，依狀況亦可依據振幅檢測電路28檢測出之振幅資 訊進行資料檢測，或是依據脈寬檢測電路33檢測出之脈寬 貢訊進行雜質檢測及裝卸檢測等之過載檢測。如資料檢測 時，在高負載區域負載變動情況下，係依據振幅資訊進行 資料檢测，或疋兼用振幅資訊與脈寬資訊進行資料檢測。 另外電源之供給能力低，藉由過載而電源電壓降低之系 統等情況下’係依據脈寬資訊進行雜質檢測及裝卸檢測， 或疋兼用脈寬資訊與振幅資訊進行雜質檢測及裝卸檢測。 如就雜質檢測，如前述，可依據振幅檢測電路28檢測出 之振幅資訊進行，不過’亦可依據脈寬檢測電路33檢測出 之脈寬:貝Dfl進行，或是使用振幅資訊及脈寬資訊來進行。 如圖19顯7^雜質尺寸與脈寬檢測之計數值的關係。G1係 正#負載日守之變化特性。G2係並非雜質之正常負載時，在 —人側（文電裝置）觀察之計數界限值的收斂橫軸線。如G3 之變化特性 二丄 、，計數值為G2之計數界限值以下情況下，可判 斷為雜曾 〇 介 ’、亦即’因為G3係無法藉由振幅檢測而檢測之雜 貝的I化特性，且在與線圈之間進行估計外之結合，藉由 、載（G1)無法獲付之相位旋轉，而觀察小之計數 值，所以可主丨i i ^ J斷為雜質。藉由將該圖19之檢測方法與振幅 J28612.doc -42- 200901597 檢測組合，可進行更具智能之檢測處理。 另外如上述，係就本實施形態詳細作說明，不過熟悉 本技術之業者應可輕易瞭解，從本發明之創新事項及效果 可作許多實體性不脫離的改良。因此，此種改良例均係包 含於本發明之範圍者。如在說明書或圖式中，至少曾與更 廣義或同義之不同用語（低電位側電源、高電位側電源、 檢測電壓、電子機器等）_起記載之用語（gnd、vdd、峰 值電壓、行動電話與充電器等），在說明書或圖式之任何 部位，均可替換成其不同之用語。此外，本實施形態及改 良例之全部組合亦包含於本發明之範圍。此外，送電控制 裝置、送電裝置、受電控制裝置、受電裝置之結構與動 作、振幅檢測方法、脈寬檢測方法亦不限定於本實施形態 中說明者’而可實施各種改良。 【圖式簡單說明】 圖1(A)、圖l(B)係無接點電力傳送之說明圖。 圖2係本實施形態之送電裝置、送電控制裝置、受電裝 置、受電控制裝置的結構例。 、 圖3㈧、圖3(B)係藉由頻率調制、負載調 之說明圖。 疋貝竹 用之流程 圖4係就送電側與受電側之動作概要作說明 圖0 圖5係本實施形態之送電控制裝置的結構例。 圖6係說明本實施形態之動作用的訊號波形例。 圖7係fe限值表之例。 128612.doc -43- 200901597 圖8係振幅檢測電路、A/D轉換電路之具體的結構例。 圖9係說明振幅檢測電路之動作用的訊號波形例。 圖10係说明本實施形態之動作用的訊號波形例。 圖11係本實施形態之第—種改良例的結構例。 圖12係說明第一種改良例之動作用的流程圖。 圖13係本實施形態之第二種改良例的結構例。 圖14(A)、圖14(B)係顯示線圈端電壓波形之測定結果之 〇 圖15係顯示驅動時脈與線圈端電壓波形之關係的模式 〇 圖16係第二種改良例之具體結構例。 圖17係s兒明第二種改良例之動作用的訊號波形例。 圖18(A)、圖18(B)係脈寬變化、振幅變化之特性圖。 圖19係顯不雜質尺寸與脈寬檢測之計數值的關係之特性 【主要元件符號說明】 L1 一次線圈 L2 二次線圈 10 送電裝置 12 送電部 14 電壓檢測電路 16 顯示部 20 送電控制裝置 22 控制電路（送電側） 128612.doc -44^ 200901597 24 振盪電路 25 驅動時脈產生電路 26 驅動器控制電路 28 振幅檢測電路 29 A/D轉換電路 30 閂鎖電路 32 波形整形電路 33 脈寬檢測電路 34 閂鎖電路 40 受電裝置 42 受電部 43 整流電路 46 負載調制部 48 饋電控制部 50 受電控制裝置 52 控制電路（受電側） 54 輸出保證電路 56 位置檢測電路 58 振盪電路 60 頻率檢測電路 62 滿充電檢測電路 90 負載 92 充電控制裝置 94 電池 128612.doc -45- 200901597 100 臨限值表 102 計數器 110 抽樣保持電路 112 逐次比較暫存器 114 D/A轉換電路 120 賦能訊號產生電路 122 計數器 124 計數值保持電路 126 輸出電路 130 比較電路 J28612.doc -46-Therefore, the control circuit 22 can determine the level of the load on the power receiving side based on the magnitude of the count value. Fig. 1 (A) shows the change of the surname of the pulse width, and the variation of the amplitude is shown in Fig. 18(B). 128612.doc -40- 200901597 Characteristics. The horizontal axis of Fig. 18(A) is the load current amount on the power receiving side, and the vertical axis is the count value (pulse width period) of the count benefit 122. Further, the horizontal axis of Fig. J 8 (B) is the amount of load current on the power receiving side, and the vertical axis is the amplitude (peak voltage) of the coil terminal voltage. The pulse width variation characteristic of Fig. 18(A) is as shown in Fig. 1, and the amount of load current is small. When the load is low, the rate of change of the count value to the amount of load current is large, and the sensitivity is still high. In addition, as shown in E2, the amount of load current is large, and in the case of high load, the rate of change of the count value to the change of the amount of load current is small, and the sensitivity is low. The reason for this is that, when combined with a normal coil, the phase rotation saturation in the 'negative-phase characteristic' is increased as the load is increased by the degree of bonding. In addition, the amplitude variation characteristic of Fig. 18(B) is such as F1. It shows that the change rate of the coil terminal voltage to the change of the load current is small and the sensitivity is low under low load conditions. In addition, as shown by F2, under high load conditions, the rate of change of the count value to the amount of load current is large and the sensitivity is high. Thus, the pulse width detection is higher in the detection performance of the low standby-envelope area than in the high load area. In addition, the amplitude detection is especially high in the load region compared to the low load region. Therefore, if you have a wide load in the low load region, you should use pulse width detection to judge the negative lane and the south of the war. In the case of high load load fluctuations, you must use amplitude detection. The ancient and broken load is low. Thus, the detection of the load variation is detected by using the detection in a low load region separately from the high negative 戟 戟 & In the case of the data transmitted by the load modulation, the load is swayed in the area where the load is low load. Therefore, the power receiving device 40 is used. Negative 128612.doc •41, 200901597 The detection of the data transmitted by the modulation is subject to the pulse width information detected by the pulse width detection circuit. In addition, in the case of an overload condition such as loading and unloading detection, high sensitivity is required in the high load region, and f is particularly detachable and detected, and is performed based on the amplitude information detected by the amplitude detecting circuit 28. Thereby, data detection, impurity detection, loading and unloading detection, etc. can be realized with high sensitivity and efficiency. In addition, depending on the situation, the amplitude information detected by the amplitude detecting circuit 28 can be used for data detection, or can be detected according to the pulse width detecting circuit 33. The pulse width tribute is used for overload detection such as impurity detection and loading and unloading detection. For example, when the data is detected, the data is detected based on the amplitude information in the case of load fluctuation in the high load region, or the amplitude information and the pulse width information are used for data detection. In addition, when the power supply capacity is low, the system is reduced in power supply voltage due to overload, etc., and the impurity detection and loading and unloading detection are performed based on the pulse width information, or the pulse width information and the amplitude information are used for impurity detection and loading and unloading detection. For example, the impurity detection may be performed according to the amplitude information detected by the amplitude detecting circuit 28, but may be based on the pulse width detected by the pulse width detecting circuit 33: BDF, or amplitude information and pulse width information. Come on. As shown in Fig. 19, the relationship between the impurity size and the count value of the pulse width detection. G1 is the change characteristic of the load day. When G2 is not a normal load of impurities, the convergence horizontal axis of the count limit value observed on the human side (text device). For example, if the variation characteristic of G3 is 2, and the count value is below the count limit value of G2, it can be judged that the miscellaneous shells of the G3 system cannot be detected by the amplitude detection. And the combination of the estimation with the coil, by the phase rotation that can not be paid by (G1), and observing the small count value, so the main 丨 ii ^ J is broken into impurities. By combining the detection method of Fig. 19 with the amplitude J28612.doc -42- 200901597 detection, a more intelligent detection process can be performed. Further, as described above, the present embodiment will be described in detail, but those skilled in the art should be able to easily understand that many innovations and effects of the present invention can be improved without departing from the scope of the invention. Accordingly, such modifications are intended to be included within the scope of the invention. In the specification or the schema, at least the terms used in the broader or synonymous (low potential side power supply, high potential side power supply, detection voltage, electronic equipment, etc.) _ the terms used (gnd, vdd, peak voltage, action) Telephones, chargers, etc., can be replaced with different terms in any part of the manual or the drawings. Further, all combinations of the embodiment and the modified examples are also included in the scope of the invention. Further, the configuration and operation of the power transmission control device, the power transmission device, the power receiving control device, and the power receiving device, the amplitude detecting method, and the pulse width detecting method are not limited to those described in the present embodiment, and various improvements can be made. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1(A) and Fig. 1(B) are explanatory diagrams of contactless power transmission. Fig. 2 shows an example of the configuration of a power transmitting device, a power transmission control device, a power receiving device, and a power receiving control device according to the present embodiment. Fig. 3 (8) and Fig. 3 (B) are explanatory diagrams of frequency modulation and load modulation. Fig. 4 is a schematic view showing the operation of the power transmitting side and the power receiving side. Fig. 0 Fig. 5 is a configuration example of the power transmission control device of the embodiment. Fig. 6 is a view showing an example of a signal waveform for the operation of the embodiment. Fig. 7 is an example of a fe limit table. 128612.doc -43- 200901597 Fig. 8 is a specific configuration example of an amplitude detecting circuit and an A/D converting circuit. Fig. 9 is a view showing an example of a signal waveform for operating the amplitude detecting circuit. Fig. 10 is a view showing an example of a signal waveform for the operation of the embodiment. Fig. 11 is a view showing a configuration example of a first modification of the embodiment. Fig. 12 is a flow chart for explaining the operation of the first modified example. Fig. 13 is a view showing a configuration example of a second modified example of the embodiment. 14(A) and 14(B) show the measurement results of the coil terminal voltage waveform. FIG. 15 is a diagram showing the relationship between the driving clock and the coil terminal voltage waveform. FIG. 16 is a specific structure of the second modified example. example. Fig. 17 is a diagram showing an example of a signal waveform for the operation of the second modified example. 18(A) and 18(B) are characteristic diagrams showing changes in pulse width and amplitude. Fig. 19 shows the relationship between the impurity-free size and the count value of the pulse width detection. [Main component symbol description] L1 primary coil L2 secondary coil 10 power transmitting device 12 power transmitting portion 14 voltage detecting circuit 16 display portion 20 power transmission control device 22 control Circuit (power transmission side) 128612.doc -44^ 200901597 24 Oscillation circuit 25 Drive clock generation circuit 26 Driver control circuit 28 Amplitude detection circuit 29 A/D conversion circuit 30 Latch circuit 32 Wave shaping circuit 33 Pulse width detection circuit 34 Latch Lock circuit 40 Power receiving device 42 Power receiving unit 43 Rectifier circuit 46 Load modulation unit 48 Feed control unit 50 Power receiving control device 52 Control circuit (power receiving side) 54 Output guarantee circuit 56 Position detecting circuit 58 Oscillation circuit 60 Frequency detecting circuit 62 Full charge detection Circuit 90 Load 92 Charge Control Device 94 Battery 128612.doc -45- 200901597 100 Threshold Table 102 Counter 110 Sample Hold Circuit 112 Successive Comparison Register 114 D/A Conversion Circuit 120 Enable Signal Generation Circuit 122 Counter 124 Count Value Hold circuit 126 output circuit 130 comparison circuit J28612.doc -46-