TW200845014A - A bit line structure for a multilevel, dual-sided nonvolatile memory cell array - Google Patents

Abstract

A nonvolatile memory array includes a plurality of dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping nonbolatile memory cess on each column form at least one grouping that is arranged in a NAND seires string of dual-sided charge-trapping nonbolatile memory cells. Each NAND seires string has a top select transistor and a bottom select transistor. A plurality of bit lines is connected in a cross connective columar bit line structure such tha each column of the dual-sided charge-trapping nonbolatile memory cells is connected to an associated pair of bit lines. The first of the associated pair of bit lines is further connected to a first adjacent column of dual-sided charge-trapping nonbolatile memory cells and the second of the associated pair of bit lines is further associated with a second adjacent column of dual-sided charge-trapping nonbolatile memory cells.

Description

200845014 IX. Description of the Invention: [Technical Field] The present invention relates to a non-volatile memory array structure and operation, and more particularly to a double-sided charge trapping type, a bit line structure of a volatile memory cell, and more particularly , involving the multi-level double-sided charge trapping non-volatile memory unit _ bit line structure, turning to program planning, reading, dividing _ catching_load, the turning _ charge Gu double-sided electric · catching forwarding The charge trapping region of the fe early element represents a plurality of bit data bits. [Prior Art] • Non-two-dimensional memory is well known in the art. Different types of non-volatile memory include ·, read-only memory (ROM), electrical programmable read-only memory (epr〇m), electrical erasable programmable = read recorder (EEPRC) M), N () R _ 记 倾, to (4) to investigate the situation. f Currently, for example, personal digital devices, mobile phones, notebook and laptop systems, voice recording key systems, etc. t memory has become more volatile in non-volatile memory. (4) The memory has the advantages of high density, ♦ small area, low cost, and the ability to use a combination of single low-power power supply reprogramming and erasing. Here, the flash memory structure known in the art uses a charge storage mechanism and a charge trap. The charge storage mechanism, for example, in the floating secret forwarding essay, represents digital information = charge bribes on the device 啰 _ pole. The stored charge correction rib determines the critical dust of the floating gate memory unit stored in the digital poor. In the charge trapping structure, as in the case of the stone-oxide-nitride-oxide, SONOS or metal-oxide-nitride-oxide-MONOS type, the charge is trapped in two insulations. The charge trapping layer between the layers. The charge trapping layer centered by NOS/MONOS & has a relatively high dielectric constant (8), such as Shi Ni nitride (SiNx). The charge is reduced to the county, so that two bits of data can be stored in the single-SONOS/M〇N〇s non-volatile memory unit. U.S. Patent Application Serial No. 5,768,192 (Eitan) describes a charge-distribution non-(four) semi-reactive cell using an asymmetric charge trapping mechanism. Programmable Read Memory 200845014 (PROM) inserts a capture dielectric between two layers of germanium dioxide. The trapping dielectric is: yttrium oxide cerium nitride <oxide (〇N〇), and cerium oxide having buried polycrystalline stone islands. A non-conductive dielectric layer acts as an electronic charge trapping medium. The charge trapping layer is interposed between two ruthenium dioxide layers as electrical insulators. A conductive control gate layer is disposed over the upper erbium oxide layer. When the source is grounded, a thermoelectric hole is used to apply the programming voltage to the gate and the drain, as described in (4). The hole is accelerated enough to attract the green ugly _ catching the area of the dielectric layer =. The device is read in the opposite direction in which it was written. When the drain is grounded, the read voltage is applied to the gate and source. For the same gate voltage applied, the reverse read greatly reduces the potential across the charge-trapping region. A shorter planning time is allowed by amplifying the effect of checking the charge in the localized region. U.S. Patent No. 7,187, G3G (Chae et al.), SQNOS Memory Device, and a method for erasing data from the SONOS memory device. The erase pack, the charge carrier of the L symbol is injected into her thin wealth, and the capture film has captured the charge of the first symbol (4). The second sign of the charge carrier is generated by the turtle field. The electric field is formed between one of the first and second electrodes in contact with at least one bit line and a gate electrode in contact with the word line. Between the closed and the general. Senna two characters _ Chu Jian hole 0

A method and apparatus for operating a string of charge trapping memory cells is described in U.S. Patent No. 7,170,785 (Yeh). The _memory unit having a charge trapping structure is read by two pairs of portions of a memory cell of the word line. The portion of the portion of the read body sheet 7L is turned on by the conduction of the (4) __ in the unit (4) unit through the electro-crystal. The selection of the portion of the reservoir is determined by the current on the bit line of the double-sided over-metallization. U.S. Patent Application Serial No. 7,158,411, et al., the disclosure of which is incorporated herein by reference in its entirety in its entirety in its entirety in its entirety in its entirety in its entirety in It is configured to store data for the use of another data. The first and second calendars are formed by the charge according to the charge of the non-counting unit. U.S. Patent Application Serial No. 7,151,293 (Shimiwa et al.) describes a SONOS memory having an inverse bit line. The s〇N〇s memory cell formed in a semiconductor substrate includes a bottom dielectric disposed on the semiconductor material; a charge trapping material disposed on the surface dielectric, and A top dielectric disposed on the charge trapping material. In addition, the s〇n〇s memory unit further includes: a word line brewing structure disposed on the top dielectric fJL; and at least one bit line gate for sensing at least one reverse in the semiconductor substrate To the bit line. No. 7,120,063 (Liu et al.) describes a flash memory cell comprising: a dielectric material formed over a substrate channel region; and a dielectric material formed in the dielectric material a charge trapping material over the bucket; and a control gate formed over the charge trapping material. The unit can be programmed by directing electrons from the control gate to the charge trapping material to raise the threshold voltage of the unit. Electron can be directed from the gate to the charge trapping material by coupling a substrate to a substrate voltage potential and aligning the control to a voltage potential, wherein the gate voltage potential is lower than The substrate voltage potential. The cell is erased by directing electrons from the charge to the threshold voltage of the (4) impurity side, and the substrate is coupled to a substrate voltage potential, and The control gate is coupled to a gate voltage potential, wherein the voltage potential is higher than the substrate voltage potential. The non-volatile memory cells in the prior art are typically configured as NAND cell junctions. U.S. Patent No. 6,614, _ and Class No. 6,163, _ (Hirose et al.) describe a semiconductor non-volatile memory device having a NAND cell structure. A NAND stack of non-volatile memory cell transistors is disposed on a semiconductor substrate 1 . The non-volatile memory cell transistor series has a threshold voltage that varies electrically within the depletion range. When a cell in a particular NAND stack is selected for a read operation, a surrounding circuit drives the selected gate word line to the well potential and drives the words of the other gates in the selected NAND stack The line is up to the potential, and the magnitude of the potential is at least equal to the reference voltage plus the size of the money that the 单 忆 体 单 被 被 被 被 纠 纠 纠 纠 纠 纠 纠.

Hara et al., "A 146-mm2 8-Gb Multi-Level NAND Flash Memory with 70-rnn CMOS Technology" with 70 nm CMOS Technology" ( IEEE's Solid State Circuits (IEeE Journal of Solid-State Circuits, January, 2016, Vol. 41, issue number: 1, pp. 161.169) provides 8Gb with 4 levels of stylized units. Hierarchical NAND flash memory.

Eitan et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell" (IEEE Electronic Device Express (IEEE Electron) Device Letters), November 2000, Vol. 21 'Publication No. 11. 'pp. 543-545) presents a novel flash memory based on local charge trapping in the 'I pen layer'. Store a nominal ~4〇〇 electron on an n+/p junction. Hunting is programmed by the channel hot electron injection program and is erased by the tunnel enhanced thermoelectric hole injection. 5 The buying method is sensitive to the position of the trapped charge above the source. The single device unit has the storage capacity of two physical bits.

Cho et al. "One-mode NAND flash memory: 1Gb multi-level and high-performance 512Mb single-layer mode (a Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes ) '', (IEEE Journal of Solid-State Circuits), November 2001, Vol. 36, issue η, page 17004706), describes 116.7mm2 NAND flash memory It has two modes: 1Gb multi-level programming (MLC) mode and high-performance 512Mb single-level programming unit (SLC) mode. The two-level bit line setting design prevents peak currents below (9) (five) people. Technology avoids program disturb. SLC mode uses 〇·5ν incremental stepping pulse and self-boosting program to overcome the program to achieve high planning performance. MLC mode uses 0.15V incremental stepping pulse and partial self-boosting program to overcome the design, close The distribution of the threshold voltage Vth of the ground control unit. U.S. Patent No. 7,203,092 (Nazarian) provides a memory array having rows and columns of flash memory cells. Configuring a NAND sequence string like a memory cell. Each NAND series string has: a top select transistor, and a bottom select transistor. The top select transistor and the bottom select transistor are connected to the bit line such that in response to The bit line is selected and biased, and the alternating bit line is operated as a source line or a bit line. ^ The structure of the multi-bit programming of the non-volatile § memory unit is written by Atwood et al. 9 200845014 "Intel StrataFlash ΤΜ Memory Technology Overview (Intel StrataFlash TM Memory

Technology Overview)", (Intel Technology J0Umai, Vol. 2, Q4 1997, published on www.intel.com, April 23, 2007) is known in the art. The volatile memory cell includes a single transistor having an isolated floating gate. The flash cell is an analog storage device that stores charge (quantized in a single electron) rather than a memory bit. Technique, but a precise amount of charge can be placed on the floating gate. The charge is accurately set to one of the four charge states (or ranges) describing the two bits. Each of the four charge states has two bits. The data pattern of the element is related. The number of states required is equal to 2N, where N is the desired number of bits. Then the critical value of the flash cell is determined to read the digital data stored in the flash cell. No. 7,113,431 (Hamilton et al.) belongs to the technique for erasing the bits in the dual-bit memory, which is performed in such a manner as to maintain the interference control of the complementary bits of the bit pairs of the memory cells. except, The elements of the dual-bit memory unit can be programmed into multiple levels. A typical method includes: providing a word of the memory unit after the initial erasure, and planning the four-bit bit knowledge to a more detailed level. Program programming one or more levels of the hierarchy. Each of the bit pairs of the word determines an interference level. The combined interference level is then calculated to represent the individual interference level. The drain voltage pattern is then applied to the The word is programmed a number of times until the target pattern is stored in the word of the memory unit according to the combined interference level, and the unprogrammed bits in the bit pair are erased to a single programming level. This compensation exists in the interference between the complementary bit pairs of the words, improving the distribution of the critical (Vt) distribution in the program level of the erased program, and the improvement of the money is planned with the higher program. Accuracy' and reduce errors or incorrect readings of the program's leveling state. SUMMARY OF THE INVENTION The present invention is directed to providing a columnar bit line junction with intersecting connections Structure for multi-level programmable programming of double-sided non-volatile memory cells. The present invention is directed to providing a circuit and method for (4) operating a columnar read structure having intersecting connections. The at least one of the array of double-sided non-volatile memory cells of the program axis, the at least one of the body arrays, the present invention provides - the non-volatile memory Τ 所述 the double-sided electrical capture-type forward memory on each column ΝΛ, Γ in the NAND _ series of double-sided charge-trapping non-volatile memory cells. Cascade-green; t 2 strings have. Top select transistor, and - bottom select transistor. Sighting so that the two sides of the double-sided charge 槪-type 杂 记 记 一 = , , , , , , , , , , , , , , , 源 源 源 源 源 源 源 源 源 源 源 源 源 源 源 源 源The relevant bit ', the younger brother. The first one of the related bit line pairs is further connected to one adjacent column of the double-sided upper memory unit f, and the first ft surface charge trapping of the associated bit line pair A second adjacent column of non-volatile memory cells has a source/drain of a top select transistor connected to the escaped second strip of the associated bit = two, and the second adjacent column The bottom of the bottom select transistor is connected to the first one of the associated bit line pairs. The positive 4SL unit line t is connected to the plurality of bit lines. Shifting the bit line operating voltage to a double-sided electrically-capable non-volatile memory cell, because the charge code used for the capture is secondarily broadcasted, and the captured charge represents the selected one. Double-sided charge-trapping military § 己 体 体 单元 单元 一 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元Selecting ^ and a plurality of bottom selections. Each word line and the complex surface charge trapping memory unit One row is selected. Each top selection line is connected to the double-sided charge trapping type. At least one of the top serial strings of the memory cells is selected from the top of the transistor. L The bottom selection line is connected to the double-sided charge type. The bottom of at least one of the NAND strings of the memory cells selects the secret of the transistor. The word line control (4) is connected to the word line, the top selection line, and the bottom selection line to shift The word line operation read is used to perform selection, programming, reading, and erasing of the captured charge, wherein the captured private charge represents each of the selected double-sided charge trapping non-volatile memory sheets 11 200845014 A plurality of bit data bits in the charge trapping area. The bit line controller has: a first bit threaded planning voltage source, and a second bit threaded planning voltage source. a meta-threaded planning voltage source that passes through the first one of the associated bit line pairs to the source/drain of the top select transistor, and will represent a plurality of portions of the plurality of digital data bits One of the critical adjustment voltages Providing a first drain/source of the selected double-sided charge trapping non-volatile memory cell to set the hot carrier charge representative of a portion of the digital negative negative bit of the charge trapping region a first level of quasi-planning voltage source, providing a second retracement threshold voltage representing another portion of the plurality of digit data bits to: selected double-sided charge trapping non-volatile A first gate/source of the memory cell is at a second level of the hot carrier charge of the portion of the plurality of digital data bits of the charge trapping region by δ. Having a character-threaded programming voltage source that provides a negative medium-sized process j planning voltage and a medium positive source or no-pole voltage for generating a double-sided charge trapping non-volatile memory cell located in the selected Controlling a gate, a voltage field between the gate and source regions of the selected double-sided charge trapping non-volatile memory cell, and implanting from the selected double-sided charge trapping non-volatile memory cell One charge The hot and cold regions in the capture zone produce hot carriers. The word line controller further includes a first selected threaded planning voltage source and a first threaded planning voltage source. The first selected threaded planning voltage source selectively provides a top select transistor for the NAND series string of 70 read _ _ _ double sided charge traps. The second 划 择 ! I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Gu, which generates a plurality of complex elements of a single body unit, selects a plurality of copies;:=r-12 12450450, including - reading secrets to produce n, which produces - 汲 赖 ,, ship voltage level The first and second strips of the edge pair are selectively transferred to the first gate/source and the second secret/source, depending on the trapped charge trapping region The charge level is initiated by the selected double φ charge generalized to the nucleus unit. The 侃 line control succeeds in the first, the ground reference 赖 produces ||produces - picks up the test, the face position Yuan lion rides the first and f two are turned face to the first - and second miscellaneous ...inductive Wei Jing said Chengshan position 兀 line is connected to: the selected double-sided charge 槪 type non-volatile memory unit, with the pair of f = two fresh lines, the side represents the multi-station data bit The programmed state of the charge trapping region. • The pressure is more included—the word is still fine. _ Large eraser The electricity is used in the channel area of the face-to-face turtle-type non-volatile memory unit, and the two are ===峨 峨 除 除 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用 使用Touch line controller: There is a brother-grounding voltage generator m to apply the ground reference voltage to the first and the - no source. /, the example capture type non-volatile memory unit is the secret of the n-channel memory unit. The pattern voltage level is about - 至 大约 , , ν to make the (two) hole injection into the charge trap layer. . The plurality of critical adjustment voltages are the first and second portions of the digital data bits. == til to about +5·ϋν, divided into different numbers

The increase of Sl351 dragon is 4. The ship's pole electrical calibration must be - the voltage level, large enough to overcome the first and second 丼妯 丼妯 从 F from the Xintian two mines flat 疋 double-sided charge trapping non-volatile; Not enough to cause the f to be about +1 to about +20V. The very large erase voltage uses H_Norxiheim f tunneling so that hot electrons are injected from the channel region into the double-sided charge trapping type memory to increase the riding double-sided f-load capture type non-i 13 200845014 The threshold voltage of the memory unit. In the example where the double-sided charge trapping non-volatile memory unit is a ρ·channel memory unit, the very large program is drawn; the j-level is about ν to about, to cause a hot load. Sub-injection is injected into the charge trapping layer for the thermal cavity. The plurality of critical adjustments: the range 攸 about -1.0V to about -6.0V, and the interval is sufficiently large to determine the plurality of, the first and second of the digital data bits section. The plurality of critical side = = electric 扼 扼 从 大约 from about -2.0V to about 娜, and is divided to distinguish the plurality of programs. The singularity of the electric squad is to be counted, and it is large enough to be grammatical, 汲 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Further, in the case where the double-sided charge-transfer memory is a P-channel memory cell, the very large erase current is large, ·, - 5.〇ν to about -20V. The very large erase voltage is flipped with F〇wler N, and the channel region is injected into the double-sided charge-trapping non-volatile memory cell boundary to reduce the double-sided charge trapping VOID MEMORY UNIT [Embodiment] The non-volatile view ship of the present invention is a two-sided charge trapping type non-volatile memory that is disposed on each column by a double-sided charge trapping configuration A double-sided charge-trapping non-volatile memory unit in series with 3 ΐ ΐ is connected in series. Each of the capture-type non-volatile memory cells: a secret and a pole of the lion's transistor connected to the said; =: a source of the bottom-selective transistor is connected to the associated bit = = off bit, the first pair in the pair is more with double-sided charge trapping and the double-charged her-style transfer Wei Jiuyi (i^第-相_赖钱) system The cell ^ neighbor is associated with 'and a second adjacent column of the preceding bit in the associated bit line pair. The top select 200845014 selects a source/drain of the electrification transistor to : the second repair in the related bit line pair, and the second phase _ (four) Φ electric turn-off forwarding (4) single bottom: select a source/drain of the transistor to connect to the Said first 佟 in the associated bit line pair

V

a bit line controller is connected to the plurality of bit lines, and the bit line operation is selected to select a double-sided charge enemy non-volatile memory unit, and the captured charge path is swiped, read, and wiped. In addition, the captured charge represents a plurality of digital data bits in the charge trapping regions of each of the selected double-sided non-volatile memory cells. The control gates of each of the double-sided charge trapping non-volatile memory cells on each column of the non-volatile memory array of the present invention are connected to a word line. The gates of the top select transistors of the NAND series of multiplexed charge trapping volatile memory cells are coupled to the select lines. _ ground, charge her type _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ A word line controller is connected to: the word line, the top selection line, and the bottom selection line, to transfer & yuan operation voltage, Lin will be arrested (four) charge Qing, program _, read And the erased, wherein the captured, charge represents a plurality of digital data bits in the charge trapping regions of each of the selected double-sided charge trapping non-volatile bills & Production of the tea test, the first map and the lb, for discussing the Lashi oxide _ nitride _ Shi Xi (SONOS) or metal-oxide _ nitride _ oxide · 〇 〇 N〇 s double The surface flash flashes the FF body early collision structure, and the 帛 lb off the invention turns the memory memory charge trapping scale relay unit 5 to form in the substrate. - Secret == = Zone 2G is formed in the substrate 1〇. - relatively thin _ extreme oxide oxide oxide % deposition; on the soil plate 10. - A charge trapping layer 35 is then formed over the oxide layer 3A and above the channel region 25 between the poleless = 5 and the source region 20. A second dielectric oxide layer 4 is placed on top of the electron capture layer 35 to separate the charge trap layer 35 from the multi-layer 45. The multi-layer 45 forms a controlled closed-pole of the double-sided charge trapping non-volatile memory unit $. When the control side of the double-sided transfer type read unit 5 is disposed in an array of double-sided charge traps 2, the memory unit 5 is connected to a word line terminal 50. The drain 15 is connected to the -th bit line terminal 55, and the source 2G is connected to the second bit line terminal. 15 200845014 The body sheet is stored as a _ (four) charge in the Ϊ (4) charge and stored in the electric channel charge trapping layer 35. The multi-layer double-sided flash memory unit 5 formed between the pole 15 and the source 20 is disposed. The operations include ··—erase operations, operations, and read operations. At the erase operation t, the word line terminal 50 is set to erased and applied to the control gate 45, thereby injecting electrons from the channel region between the gate 15 and the source 20, being captured. The charge is 65 and 7 wipes. The first and second bit line terminals 55 and 60 and the drain region 15 and the source region 2 are thus set to a ground reference voltage. The program planning operation of the multi-layer double-sided flash memory unit 5 is set by applying a medium program size voltage to the word line terminal % to the control '45. The screaming plan lightning pressure of the shot is opposite to the polarity of the very large erased dust. In order to program the charge trapping region 65 closest to the drain region ls, the first-bit line terminal 55 and the non-polar region ls are sequentially set to the bit line voltage level j and the second bit line terminal 60 and The source region 2〇 is set to the ground reference voltage. In order to be the most detached from the source 2G, the 狮 娜 % % 奴 帛 帛 帛 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四Set to ground reference voltage. Read operation by placing the word line end? % and thus the control gate 45 are determined to start with the read voltage level. To read the charge trapping area & the state, the first bit line terminal 55 and thus the non-polar region 15 are set to the ground reference voltage, and the second bit 7 〇 line terminal 60 and 0 this source Zone 2G is set to check the pole reading level. The threshold voltage (10) adjusted by the charge level of the charge trapping region 65 determines the digital data stored in the charge trapping region 65. To read the program planning state of the charge trap 357, the one bit line terminal 55 and thus the drain region 15 are set to the immersed voltage level, and the second bit line terminal 60 and thus the source region 20 are Set to ground reference. The threshold voltage (Vt) adjusted by the charge level of the charge trapping region % determines the digital data stored in the charge trapping region 7A. The method of operation of the present invention for a SONOS/MONOS double-sided flash memory cell provides a plurality of bits of respective charge trapping regions 65 and 7〇 stored in FIG. In the lc diagram, each of the charge trapping regions may have a level of one of four levels 100, 110, 12, and 13, and thus two binary bits representing digital data. The threshold voltage level 130, which serves as the erase voltage level, also serves as the voltage level for the digital data of the digit η. s〇N〇s/M〇N〇s double 200845014 face flash memory unit -_ is made long enough _ program planning, _ allows the distribution of threshold voltages (Vt) 102, 112, 122 and 132 to allow The word line voltage is set, and thus the array of the array is programmed for voltages WV1 1〇5, WV2 115, and (2). During a master operation, the control gate is set to determine the threshold voltage (Vt) of each voltage, and the critical value represents the two bits of each of the health care resources stored in the charge trapping layer. The non-volatile memory array 200 of the present invention is formed by a double-sided charge trapping non-volatile memory cell unit in the first drawing in a column and row configuration, as shown in Fig. 2a. The sets 210a, 210b, 210N, 210n, 210n of the double-sided charge trapping non-volatile memory cells 205 located on the respective rows of the non-volatile memory array 200 of the present invention are connected to form a double-sided charge trapping type. A NAND series string of volatile memory cells 205. Each of the NAND series strings 21a, 210b, ... 210n-1, 21〇n has a top selection transistor 215a, 215b, ... 215n l, 21, and a bottom selection transistor 220a, 220b, ... 220n-l 220η. Each of the top selection transistors 215a, 215b, ... 215n-1, 215n has a first source/no pole, and is connected to the top of each of the series series strings 210a, 210b, ... 210n-1. The pole of the volatile memory unit 205. Each of the bottom selection transistors 22A, 22B, ... 220n-, 220n has a first source/drain, connected to the bottom of each of the NAND series strings 210a, 210b, ... 210n-: 1, 220n The source of the surface charge trapping non-volatile memory unit 205. The source and drain electrodes of the top selection transistors 215a, 215b, ... 215n], 215n and the bottom selection transistors 220a, 22〇b, ... 22〇11_b 220n are functionally interchangeable, and therefore are clearly stated. Designated as the first and second source/drain. Each of the top selection transistors 215a, 215b, ... is operative to allow the second source/drain to be connected to the relevant ones of the bit lines 225a, 225b, 225c, ... 225n-2, 225n-1, 225n. The first line of the bit line pair. The second source/nopole of the bottom selection transistors 220a, 220b, ... 22〇η-1, 220n is connected to the bit lines 225a, 225b, 225c, ... 225n-2, 225n-1, 225n The second line of the bit line pair. The various rows of the non-volatile memory array 200 of the present invention (in this embodiment, referred to as one of the NAND series strings 210a, 210b, ... 210n-1, 210n) and the bit lines 225a, 225b, 225c, ... 17 200845014 225n- 2. A pair of bit lines of 225n-l and 225η are related. One of the pair of bit lines associated with the bit lines 225a, 225b, 225c, ... 225n_2, 225n-1, 225n is further a first adjacent to the double-sided charge trapping non-volatile memory cell unit The rows 2i 〇 a, 21 〇 b, ... 210 η - 卜 210 η are related, and the second of the pair of bit lines in the bit lines 225a, 225b, 225c, . . . 22511-2, 225H-b 225n The strip is further related to a second adjacent row 21 (^, 21013, ".21〇11-1, 21〇11) of the double-sided charge trapping non-volatile memory cell unit. The first adjacent row 21 (^ a second source/no pole of the top select transistor of 21011, 210, 210n-1, 210n is connected to the bit in the bit line 225a, 225b, 225c, ... 225n_2, 225n·: 1, 225η The second strip of the pair, and a source/drain of the bottom select transistor of the second adjacent row is connected to the bit line 225a, 225b, 225c, ... 225n-2, 225n-1, 225n The first strip of the associated bit line pair. The top select transistor having one row of 2i〇a, 210b'.. 210n4, 210n and 21〇a, 21〇b, ... 210n-l, 210n Bottom selection of an adjacent row The transistor is connected to one of the bit lines 225a, 225b, 225c, ... 225n-2, 225n-b 225n, providing the intersecting columnar bit line structure of the present invention. All bit lines 225a , 225b, 225c, ... 225η-2, 225η-b 225η are all connected to the bit line controller 230. The bit line controller 230 provides the necessary bit to the selected double-sided charge trapping non-volatile memory unit 205. a line operating voltage for programming, reading, and erasing the captured charge, wherein the captured charge represents a charge trapping region of each of the selected double-sided charge trapping non-volatile memory cells a plurality of digital data bits in a row. A control gate of each double-sided charge trapping non-volatile memory unit 205 on each column of the non-volatile memory array 200 of the present invention is connected to word lines 235a, 235b One of 235j-l, 235j, 235j+l, ... 235m], 235m. The gates of the top selection transistors 215a, 215b, ... 215n_1, 215n are connected to the top selection gate lines 240a and 240b. This embodiment of the non-volatile memory array 200 of the present invention In the example, one of the top select transistors 215a, 215b, ... 215n-1, 215n is connected to one of the top gate select lines 240a and 240b, and the other half is in the top gate select lines 240a and 240b The other one is connected. The gates of the bottom selection transistors 220a, 220b, ... 220n-1, 220n are connected to the bottom selection gate line 245. All word lines 235a, 235b, ... 235j], 235j ·, 235j + ...... 235m small 235 melon, top select gate lines 240a and 240b, and bottom select gate line 245 are all connected to one character 18 200845014 line controller 250. The word line controller 250 rotates the operating voltage of the word line for selecting, reading, reading, and erasing the captured charge, wherein the captured charge represents each of the selected double-sided charges Non-volatile memory unit 2〇5 # A multi-station data bit in a charge trapping area. A second embodiment of the non-volatile memory array 200 of the present invention formed by the double-sided charge trapping non-volatile memory cells of Figure la is shown in Figure 2b. Except for the bottom selection transistor 22Ga, 22Gb, ··· 22Gn.:l, recommended _ pole, the structure and function of this (10) are equivalent to the 2a figure. The bottom selection transistors 22A, 220b, ... 220n-1, 220n are alternately connected to one of the two bottom selection gate lines 245a and 245b. Enabling one of the two bottom select gate lines 245a and 245b allows alternate rows of NAND series string sets 21〇a, 21〇b, ... 210η-1, 210n to be connected to bit lines 225a, 225b, 225c, ... 225nJ, 225n ' and NAND series series strings 210a, 21Gb, ..., 210n · 1, 21Gn are alternately isolated, the NAND series string sets the bottom selection transistors 22〇a, 22〇b, ... 22〇11_ Bu 22〇n is connected to the unstarters of the two bottom select gate lines 245a and 245b. A more general structure of the non-volatile memory array 300 of the present invention is formed by the two-sided charge trapping non-volatile memory cell of the ia diagram in a row and row configuration, as illustrated in Figure 3. Groups 310a, 310b, 310c, 310d, _, 310i, 310j, 310k, 3101, ..., 310w of each double-sided charge trapping non-volatile memory unit 305 on each row of the non-volatile memory array 300 of the present invention 310x, 310y, 310z are connected in the manner described above to form a NAND series string of double-sided charge trapping non-volatile memory cells 305. Each of the NAND series strings 310a, 310b, 310c, 3, ..., 310i, 310j, 310k, 3101, ..., 310w, 310x, 310y, 310z has: a top selection transistor 3i5a, 315b, 315e, 315d, 315i, 315j, 315k, 3151, ···, 315w, 315x, 315y, 315z; and a bottom selection transistor 320a, 320b, 320c, 320d, ..., 320i, 320j, 320k, 3201, ..., 320w, 320x, 320y, 320z. Each of the top selection transistors 315a, 315b, 315c, 315d, ..., 315i, 315j, 315k, 315, ..., 315w, 315x, 315y, 315z has a first source/drain connected to each NAND series string The drains of the double-sided charge trapping non-volatile memory cells 305 at the top of 310a, 310b, 310c, 310d, ..., 310i, 310j, 310k, 3101, ..., 310w, 31〇x, 310y, 310z. Each of the bottom selection transistors has a first source/drain connected to each of the 19 200845014 NAND series strings 3i〇a, 31〇b, 310c, 310d, . . . , 310i, 310j, 310k, 3101, ..., 31Gw The source of the double-sided charge trapping non-volatile memory cell 305 at the bottom of '310χ, 310y, 310z. The top selection transistors 315a, 315b, 315c, 315d, ..., 315i, 315j, 315k, 3151, ···, 315w, 315x, 315y, 315z and bottom selection transistors 320a, 320b, 320c, 320d, .. .. 320i, 320j, 320k, 3201, ···, 320w, 320x, 320y, 320z The source and the pole are functionally interchangeable, so for the sake of clarity, they are specifically designated as the first and second sources / no pole. a second source/no pole of the top selection transistors 315a, 315b, 315c, 315d, ..., 315i, 315j, 315k, 3151, 315, 315x, 315y, 315z is connected to the bit line 325a, The first of the associated bit pairs in 325b, 325c, 325d. A second source/drain of the bottom selection transistors 320a, 320b, 320c, 320d, ..., 320i, 320j, 320k, 320, ..., 320w, 320x, 320y, 320z is connected to: bit lines 325a, 325b, The second line of the bit line pair in 325c, 325d. The second source/nopole of the top select transistors 315a, 315b, 315c, and 315d are connected to the bit line 325a. The second source/drain of the top select transistors 315i, 315j, 315k, and 3151 are connected to bit line 325b. The second source/drain of the top select transistors 315w, 315x, 315y, and 315z are connected to bit line 325C. The second source/no pole of the bottom select transistors 320a, 320b, 320c, and 320d are connected to the bit line 325b. The second source/nothing of the bottom select transistors 320i, 320j, 320k, and 3201 is coupled to the bit line 325c. The second source/drain of the bottom select transistors 320w, 320x, 320y, and 320z are connected to the bit line 325d.

The rows of the non-volatile memory array 300 of the present invention (in this embodiment, the NAND series strings 310a, 310b, 310c, 310d, ..., 310i, 310j, 310k, 310, ..., 310w, 310x) One of 310y, 3i0z) is connected to a pair of bit lines associated with one of bit lines 325a, 325b, 325c, 325d. In this example, a plurality of sets of NAND series strings 3i〇a, 3i〇b, 310c, 310d, ..., 310i, 310j, 310k, 310, ..., 310w, 310χ, 310y, 310z and bit lines 325a, 325b A separate bit line pair in 325c, 325d is related. As shown, NAND series strings 31A, 310b, 310c, and 310d are associated with bit lines 325a and 325b. The NAND series strings 310i, 310j, 310k, and 3101 are associated with bit lines 325b and 325c. NAND series strings 310w, 310x, 20 200845014 310y and 310z are associated with bit lines 325c and 325d. Obviously, each of the associated bit line pairs in the bit lines 325a, 325b, 325c, 325d is further connected to the rows 3i〇a, 3i〇b, 31〇c, 310d of the double-sided charge trapping non-volatile memory unit. ..., 310ι, 310j, 310k '310b..., 310w, 310x, 310y, 310z are related to two adjacently set lines. For example, bit lines 325b and 325c are primarily associated with NAND series strings 310i, 310j, 3101A, and 3101, but bit lines 3251) are also associated with adjacent lines of >^>© series strings 31 (^, 31013) , 310c and 310d are related, and bit line 325c is associated with adjacent rows of NAND series strings 310w, 310x, 310y, and 310z. There is a set of NAND series strings 310a, 310b, 310c, 310d, ..., 310i, 310j, 310k, 31 (Π, ..., 310w, 310x, 310y, 310z rows of top select transistors, and an adjacent set of NAND series strings 310a, 310b, 310c, 310d, ..., 310i, 310j, 310k, 3101, ..., 310w, The bottom select transistors of the 310x, 310y, 310z rows are commonly connected to bit lines 325a, 325b, 325c, 325d to provide the bit line structure of the intersecting pillars of the present invention. All bit lines 325a, 325b, Both 325c and 325d are coupled to a bit line controller 330. The bit line controller 330 provides the necessary bit line operating voltage to the selected double-sided charge trapping non-volatile memory unit 3〇5 for capture. The charge is programmed, read, and erased, where the captured electricity The charge represents a plurality of digital data bits in each of the selected double-sided charge-trapping non-volatile cells. The non-volatile memory array 300 of the present invention is arranged on each column. A control gate of each of the double-sided charge trapping non-volatile memory cells 305 is connected to one of the word lines 335a, 335b, ..., 兕一, 335j, 335j+b..., 335m-l, 335m The top selects the gates of the transistors 315a, 315b, 315c, 315d, ..., 315i, 315j, 315k, 315, ..., 3l5w, 315x, 315y, 315z and the top select gate lines 34〇a, 34〇b, 340k -l, and 34〇k are connected. In this embodiment of the non-volatile memory array 300 of the present invention, each set of NAND series strings 310a, 310b, 310c, 310d, ..., 310i, 310j, 310k, 310 Each of the top selection transistors 315a, 315b, 315c, 315d, ..., 315i, 315j, 315k, 3151, ..., 315w, 315x, 315y, 315z of 310w, 310x, 310y, 310z is connected to The top selects one of the gate lines 34〇a, 340b, 21 200845014 340k-l, and 340k, so that the top select gate line The number of 34〇a, 340b, 340k-1, and 340k and each group of NAND series strings 310a, 310b, 310c, 310d, ..., 310i, 310j, 310k, 31 (M, ..., 310w, 310x, 310y, The number of rows in 310z is equal. The gates of the bottom selection transistors 320a, 320b, 320c, 320d, ..., 320i, 320j, 320k, 3201, ..., 320w, 320x, 320y, 320z are connected to the bottom selection gate lines 345a, 345b, 345k-1 and 345k . All word lines 335a, 335b, ..., 335H, 335j, 335j+b..., 335m-; 1, 335m 'top select gate lines 340a, 340b, 340k-1 and 340k, and bottom select gate lines 345a, 345b, Both 345k-1 and 345k are connected to a word line controller 350. The word line controls the operating voltage of the zigzag 350 shift word line for programming, reading, and erasing the captured charge, wherein the captured charge represents each of the selected double-sided charge trapping Volatile memory unit 305 - a plurality of digital data bits within the charge trapping region. NAND series string sets 310a, 310b, 310c, 310d, top select transistors 315a, 315b, 315c, 315d, and bottom select transistors 32〇a, 3, 32〇c, 32〇d form a double-sided charge trapping Non-volatile memory block 355. In Fig. 3, the double-sided charge-trapping non-volatile memory unit f35 between the pairs of bit lines in the bit lines 32乂, 325b, 325c, 325d each behaves a single double-sided charge trapping type. Volatile memory block 355. Now, the double-sided charge-trapping non-volatile memory block 455 has the same structure and function as the double-sided charge-type non-volatile memory block 355 of the third figure. In this embodiment, a more general version of the non-volatile memory array 4 of the present invention is discussed in which a plurality of double-sided charge trapping non-volatile memory block taxes are listed herein. Line configuration. As depicted in Figure 3, each double-sided charge-type non-volatile memory block milk has a plurality of =AND series strings having connected top select transistors and associated bottom select cells. The top selection transistor is connected to the _th line of the bit line 425a, 425η·2, ···, heart], and the closed bit 7〇 line pair. The bottom selection transistor is connected to the second line of the associated bit line pair in the bit lines 4仏, 425b, η 2 ···, 425n-1, 425η. Each double-sided charge-trapping type on each column of the horn array of hairy memory. A control gate of the body 70 is connected to the word lines 435a, 435b, ... 435m. In this embodiment of the non-volatile brother memory array 400, each group of NAND strings is % The top select transistors of the string are connected to the top select gate line her, Na, ... 440m, 22 200845014 so that the number of top select gate lines 440a, 440b, ... 440111 and double-sided charge trapping non-volatile The number of rows in each group of NAND series strings in memory block 455 is equal. The gate of the bottom select transistor of the double-sided charge capture non-volatile memory block 455 is connected to: the bottom select gate lines 445a, 445b, ... 445m. All word lines 435a, 435b, ... 435m, top select gate lines 440a, 440b, ... 440m, and bottom select gate lines 445a, 445b, ... 445m are all connected to a word line controller 450. The word line controller 450 shifts the operating voltage of the word line for selecting, programming, reading, and erasing the captured charge, wherein the captured charge represents non-volatile in the present invention. Each of the selected double-sided charge trapping non-volatile memory cells of the memory array 4 is a plurality of digital data bits in a charge trapping region. Referring now to Figure 5, the functional structure of the word line controller 500 of the non-volatile memory array of the present invention is described. The word line controller 5 receives: a program planning control signal 5〇5, an erase control signal 510, and a read control signal 515. The program planning control signal 5〇5, the erase control signal 510, and the read control signal 515 provide the startup commands necessary to determine the secret mode of the non-volatile memory array of the present invention. Those skilled in the art will appreciate that the program planning control signal 5〇5, the erase control signal 51〇, and the read control signal 515 may in fact be applied to the sub-line controller 500 to perform program planning, erasing, and reading. A component of the function's command word structure. Control decoder 52 receives program planning control signal 5〇5, erases control signal 510, and reads control signal 515, plans control signal 5〇5 for the program, erases f signal 51G, and The read control signal 515 is decoded and the non-dead unit of the present invention is initiated. The function operating unit connected to the control decoder 520 receives a command to selectively activate the word reading unit, and the traveling sample unit includes: a character job planning circuit, a child line erasing circuit 540, and a Word line read circuit 545. The programming circuit core u has a character-threaded planning voltage source 536 connected to the word line selected by the word line 56〇a, • 56Gm 1 56Gm, thereby providing a very large program size, =, a voltage 琢 is generated between the control channel and the channel region of the double-sided charge-and-capacity non-volatile memory cell. The hot carrier is extracted from the channel region and injected into a charge trapping region of the selected double-sided charge trapping non-volatile 23 200845014 LV. Your privately-planned circuit milk has a first-choice threaded planning voltage source 537, which is provided in an extended manner - moderately large. The moderate large-face voltage will be transferred to the top = gate line 555a, 555b, ... 555k], one of the selected ones to initiate the NAND of the double-sided charge trapping non-volatile memory cell The top of the series string selects the transistor. The second selected threaded planning voltage source 538 selectively provides a moderately large selection voltage. The modest large selection voltage will be transferred to the bottom selection gate, line pool, lion, ... =65k-b 5 on paper 'to start the double-sided charge-trapping non-volatile memory unit selection A^iD The bottom of the string % string selects the transistor. The program planning circuit provides a connection line to the connection = test cake source, the ground reference voltage · Yang drunk yuan line steal, 働, ... m 1 560m towel is not in the word line, gate line 555 & 555b, ··· Bu 55 = the selected gate line, and the bottom selection line in the bottom selection line, Shu, ·,····]. (10) The sub-decrance circuit 54G has a 'word line erase voltage source 543, which is connected to the word line ^Lu with two, I-, and a hat-selected word line' thus providing - a very large wipe selection The "-control gate of the surface charge-trapping non-volatile counter unit=<selected double-sided charge 转发-type repeatability, with the unit-channel area generating a Ϊ catch-through forwarding record i 1 And is injected into the charge trapping area. In the non-volatile recording unit, the practitioner is a hot electron. The summing circuit 540 has a first select line to find the voltage source 541, which is selected 55m, which is 35^. The '" high selection voltage will be transferred to the top of the top selection gate line 555b, ... 555k· 555k, to select the non-volatile dragon unit to select the second _ NAND (four) string Select the gate line 565a, 565b, ··· 565k-Bu 565k, to start the 雔 雔 帝 帝 、, nand wii secret-connection line 544 to the ground reference electric dust source, even the ground reference source is ^ 24 200845014 to the word line 560a, 560b, ... 560m - 560m towel unselected word line, top select gate line 555a, 555b, ... 555k- 555k unselected top selection gate Line, and the bottom selection of the application, 565b, ··· 565k4, 565k towel is not selected (four) silk selection line. - A word 7G line read circuit 545 has a word line read voltage source 546 connected to the selected character of the word line 56 〇 a, lion, ... 56 〇 111 _ 56 〇 m a line, thus providing a read voltage (v_) for the control gate of the selected double-sided charge trapping non-volatile memory unit, and whether the control gate is turned on or not depends on the read electric dust (v_) Value. The voltage level of the word line sense source 546 is incremented to determine the selected double-sided charge trapping non-volatile boundary level W' which represents the selected double-sided charge trapping non-volatile memory.

A plurality of digital data bits stored in two charge trapping regions of the early 7G. The read circuit 545 has a -first select line read voltage source 548, = TDD equal 観 level. The supply voltage source Vd is traversed to a selected one of the top select gate lines 555a, 555b, ... 555k-b 555k to enable the NAND t bit 551 to be selectively provided - with the supply voltage The source Vdd is equal to the voltage level of the soap and is transferred to the bottom select line 56, Μ%, 5, double-sided charge trapping non-volatile ticks on the 'on to start the crystal. The bottom of the N-series string selected by the read circuit 545 selects the electric -a ^ 560b . . : to the grounded loser #Π η The spine circuit 545 provides a connection line 544 555a, 5 says, the reference source is applied _ part selection In the gate line selection, the 565a, 鄕, woven/^^/ surface touch line, and the bottom selection line in the bottom selection 565k are not selected. Except, the data is decoded from the word line address. ^=^==^: The decoded address is invented. The non-volatile memory array 2 〇〇 decoding address decision is transmitted to the column selection circuit 550. The column n is activated; the decoded control signal, the packet 55 is used to determine that it will be transferred to the word line 25 200845014 560a, 560b, . . . 560m-b 560m, top select gate line 555a , 555b, ... 555k-1, 555k and the operating voltages of the bottom select lines 565a, 565b, ... 565k-1, 565k, thus programming and erasing the selected columns of the non-volatile memory array of the present invention And read the voltage level necessary to provide. Reference is now made to Fig. 6 for explaining the structure of the bit line control of the nonvolatile memory array of the present invention of 600. The bit line controller 6 receives a program planning control signal 5, a wipe control signal 510, and a read control signal 515. As previously described, the program plan control signal 505, the erase control signal 510, and the read control signal 515 provide the start commands necessary to determine the mode of operation of the non-descriptive 5 array of the present invention. A control decoder 6 still receives the program planning control signal 505, the erase control signal 510, and the read control signal 515, and the program planning control signal 505, the erase control signal 510, and the read control signal 515 φ are performed. The bit line function operation unit necessary for decoding, and starting the non-volatile memory array of the present invention for program planning, erasing, and reading functions. A functional operating unit coupled to control decoder 605 receives a command to selectively activate a bit line functional unit including a one-bit threaded planning circuit 615 and a one-bit line erase circuit 62. 〇, and a bit line read circuit 625. The bit threaded planning circuit 615 has a first and second bit threaded planning voltage connected to a selected bit line of the bit line 635a, 635b, 635c, 635m 2, 635m Sources 617 and 6i8 are used to provide the bit threaded planning voltage (vBLn) necessary to program the charge trapping regions of the double-sided flash memory cells of the selected column. The equipotential setting is based on the binary digital data, wherein the binary digital data is stored as the captured charge in the first and second charge trapping regions of the selected double-sided flash memory cell. The delta sigma wiping circuit 620 provides a connection line 623 to a ground reference voltage source, wherein the ground gangue source is applied to the bit line 635a, the coffee, the 635e, the 635m_2, and the 6 gamma 6 times. The selected bit line. - Bit line inhibit voltage source 622 is connected to bit line gamma, _, =, ··· 635ιη·2, 635m_ 635m unselected bit line to provide one bit line more than _ (V Face), thus eliminating the erasure of unselected double-sided charge trapping non-volatile memory elements. ~ 26 200845014 Bit line read circuit 625 has a one-bit drain voltage source 627 that is connected to selected bit lines 635a, 635b, 635c, ... 635m-2, 635m-1, 635m a bit line, thus providing a read drain voltage (VDRAIN) for the source/drain of the selected double-sided charge trapping non-volatile memory cell, wherein the source/drain conduction is dependent on the The value of the word line read voltage. The bit line read circuit 625 provides a connection line 628 to a ground reference voltage source, wherein the ground tea reference voltage source is selected by the bit lines 635a, 635b, 635c, ... 635m-2, 635m-1, 635m The bit line is applied to the opposite source/drain of the double-sided charge trapping non-volatile memory cell. Address sub-525 defines a selected portion of the non-volatile memory array of the present invention that is programmed, erased, or read by bit line address decoding g 61 。. The decoded address is transmitted from bit line address decoder 610 to bit line select circuit 63, which determines the non-volatile memory array of the present invention, which line of J 200 will be start up. The decoded control signal is transmitted to the bit line selection circuit 61〇, and the mosquito is transferred to the bit line 635a, 635b, 635e, 635m-2, 635m_b 635m cap. The operating voltage of the selected bit line ' thus provides the selected voltage levels for programming, erasing, and reading of the selected columns of the non-volatile memory array of the present invention. In the read operation, the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Na loses to the bit line selection circuit and the sensory unit _. Sensing amplification & according to the voltage of the read voltage (卩_), the double-sided charge trapping type non-volatile single το Whether it is turned on. From then on, the double-sided charge-trapping type of forward-receiving memory is selected by the mosquitoes of the meta-charged level of the element, and is determined in two charge trapping regions _ a plurality of bits of data bits. b back to the ia diagram 'The charge levels in each of the charge trapping regions 65 and 7〇 are adjusted such that the y bound level (Vt) is a set of threshold voltages 2 according to the charge set in the charge trapping region. In Figure 1c, an array of double-sided charge-trapping non-volatile memory cells of the present invention has two binary digits of each charge trapping region of the body-level charge profile. Threshold voltage level 27 200845014 1〇5, 115 and 125. Again, the program planning time is adjusted to provide s〇N〇s/ M〇N〇s the distribution of the double-sided flash memory cells 102, 112, 122, and 132, so that the program planning voltages VPV1 105, VPV2 115, VPV3 125, and the erase voltage VEV 135 are used as the word line voltages. The sequence is applied to the control gate of the double-sided charge trapping non-volatile memory unit to detect the program planning state of the double-sided charge trapping non-volatile memory unit. The threshold voltage (Vt) control of the first or second charge trapping regions 65 and 70 of the drain and source regions 15 and 20 of the volatile memory cell is independently performed by the band-banded hole injection program. One side programming of the double-sided charge trapping non-volatile memory unit. Since the crosstalk program plans the interference effect, the charge trapping is then performed on the opposite side of the channel region of the double-sided charge trapping non-volatile memory unit. The first program planning threshold voltage (%) of the program programming h, and the polarity of one of the charge trapping regions 65 adjacent to the pole 15 or the second charge trapping region 70 adjacent to the source 20 will be Reduce. For example, wear The bit line voltage level applied to the drain or source by the first bit line or the second bit line is set to VBL4=3.5V, VBL3=4.0V, VBL2=4.5V, and VBL1 − 5.0 V. Please note that the above settings are approximate and can be changed according to the needs of the particular application. In addition, the example illustrates two binary digital information bits stored in charge trapping regions 65 and 7 respectively. The voltage shown is applied to the first or second bit line at a programmed time of 150 jliS, and then to the drain and drain, if the bit line voltage level VgL] is applied to the drain or In either of the source terminals, the change in the threshold voltage level does not change. Similarly, when the bit line voltage level VBL2 is applied to either the drain or the source terminal, the change in the 6-level voltage level, AVt, is approximately 〇·7ν. If the bit line voltage level VB £2 is applied to either the drain or the source terminal, the change in the threshold voltage level, AVt, is approximately i 7v. If the bit line voltage level VBL1 is applied to either the drain or source terminal, the change in the critical lightning level, AVt, is approximately 2.5V. ’ Referring again to FIG. 2a, a control operation of the non-volatile memory array 200 of the present invention for program planning, reading, and erasing of trapped charges is discussed, wherein the captured charge represents a selection of ^^charge-balanced non-volatile A plurality of digital poor cells in the two charge trapping regions of the memory cell 2〇5. The double-sided charge trapping type of the non-volatile memory array 2 of the present invention is substantially the same as the structure shown in the U-picture. Multiple digital data bit-loading type of mixed-type memory single-two separate columns into a single choice of road 615 Kai (four) two internal figure 6 threaded planning electric = ^ ^ two brother The two-bit thread _] voltage sources 617 and 618, thus providing a process block voltage ^) for each charge trapping region of the capture-type forward memory unit. The path 535 shown in Figure 5 of the word line controller 250 initiates the character threaded planning voltage source 536, while providing the unit ·if ^ generation is located in the selective double-sided charge trapping non-volatile memory: L!tr selection The double-sided charge-trapping non-volatile memory-channel area element 3 is in the channel-selected double-sided charge-trapping non-volatile memory single. The program programming voltage is from about _7Όν To about ·v. Alternatively, if the selected double-sided charge trapping non-volatile memory unit 2〇5 is a ρ·channel type two-position, the sub-70 line voltage level is from about +7 na to about + then V. It should be noted that the hot carrier charge of the double-sided charge trapping non-volatile memory unit 2〇5 is a thermoelectric hole in the Π-pass and the double-sided charge trapping non-volatile memory is selected in the ρ-transport. The charge of the unit carrier is a hot electron. The size of the charge trapping area of the selected double-sided charge-trapping non-volatile memory unit 2G5 is determined by the number of thieves of each of these charge-viewing areas. In order to program the charge in the two charge trapping regions at the same time, the first bit line planning voltage source 617 is difficult to be drawn to the scale by the mosquito net table - the position of the 荷 _ _ digital data Ί line: pressure office (vBLN And the second bit line is assigned to the electrician, 618 is set to represent the bit line electric dust level (: BLN) of the digital dragon of the second charge enemy zone. For example, if a _ binary input word is used in each of the electric capture zones, the first bit threaded planning voltage source 617 and the second bit threaded planning electrical point 618 are based on the voltage level of Table 1. set up. Planned to the first figure is planned to the first figure VbLh bit VlJLn bit 29 200845014

As mentioned in the article by Atwood et al., "Flash memory power is critical to the storage of multiple bits in a single unit. Flash units beta can be stored instead of - digital storage devices , which stores the charge (in a single electron position.) The bit line controller 230 and the word line controller 25 of the present invention are in the charge trapping region 30 200845014 = ° ^ to enable the present invention The distribution of 4 s in the non-volatile memory array _, such as flc ® , is determined by the aging of each charge trapping region. The non-volatile memory array of the present invention is described. In the two known cases, the distribution of the 'information planning state is set to the threshold voltage (four) in a small difference, and thus has - about, the _ _ mouth. Suppose there is the ability to distinguish the threshold voltage of the ^ ^ bit number of the program _ The change of the level CVt), then any number of bits can be "the 2, 70 line controller 230 and the word line controller 250 are programmed to select the double-sided electric capture type non-volatile memory. Unit 2〇5 in the charge trapping region. One for erasing double-sided charge trapping non-volatile The bit line erase circuit of FIG. 6 in a selected element line controller 23G of the memory unit 2〇5 _ bits in the bit line 225a, lion, 225c, ... 22511-2, 225n-1, 225n The pair of potentials must be connected to the ground reference voltage source. 2 Under 2 = 225b, 225c, ... 22511-2, 225x1-1, 225η related bit line pairs, consider an unerased bit line connected The voltage source 622 is disabled to the bit line to prevent erasing of the charge trapping region. The bit line inhibit voltage source 622 is set to a disable voltage level, from a large = 7.5V to about +10V. The selected double-sided charge-trapping non-volatile body unit 2〇5 is injected into the hot carrier during the miscellaneous planning, and the word line erase circuit is set to the η-channel double-sided charge trapping non-volatile memory. Cell 2〇5 provides a word line erase voltage that is from about +15 V to about +20 V. Alternatively, if the double-sided charge trapping non-volatile interstitial unit 2〇5 is a ρ_channel device, then The word line erases the electric fort from about -15V to about -20V. A read of the non-volatile § memory array 2〇〇 of the present invention The processing is performed where the first charge trapping region is read from one direction and the second charge trapping region is read from the opposite direction. During the read operation in each direction, the word line controller The word line read voltage source 546 in the 25-inch word line read circuit 545 is connected to the selected word line among the word lines 235a, 235b, ..., 235j, 235j+: 1, ... 235m_: 1, 235m, A read voltage (Vread) is thus provided. To read the programmed state of the first charge trap, the word line read voltage source 546 is set to the read voltage level (Vr£ad). The bit line read circuit must set the first bit line pair in the associated bit line pair 425a, 425b, 425n-2, ... 425n1 425n to a ground reference voltage level (ον), the second bit The pair is set to the drain read voltage level (Vd_). 31 200845014 As mentioned earlier, the read voltage level (ν_) must be incrementally changed through the critical threshold voltage levels shown in Figure lc to determine the programmed state of the first charge trap. In order to read the programming state of the second charge trapping region, the word line voltage source 485 is set to the read voltage level (Vread). The bit line read circuit 625 sets the first bit line pair in the associated bit line pair 225a, 225b, 225c, . . . 225~2, 225n-1, 225n to the drain read voltage ( Vdrain) 'Set the first bit line pair of the associated bit line pair 225a, 225b, 225c, ... 225n-2, 225n-1, 225n to the drain read voltage (Vd_), and the second The bit line pair is set to the ground reference voltage (0V). Again, as described above, the read voltage level (Vr£ad) must be incrementally changed by each critical threshold voltage level (vpVn) shown in Figure lc to determine double-sided charge trapping.

The programmed state of the second charge trapping region of the selected column of the non-volatile § memory unit 205. During the item fetching operation, the sense amplifier 64 in Fig. 6 determines that the selected double-sided charge trapping auxiliary volatile domain unit is torn in all directions. According to the critical threshold voltage level (VPVn) and the conduction of the double-sided charge trapping non-volatile memory unit 2〇5, the sense amplifier determines the binary digital data that is programmed in each charge trapping region, and via The data log/output bus 645 transmits the binary digital data to an external circuit. As described above, the bit line controller 515 and the word line controller 5〇5 are functional in the operation of the non-essential memory array of the present invention. Referring to Fig. 2a and Fig. %, a program planning shot of the array of double-sided charge trapping non-volatile memory cells 2〇5 is described.

Work. A selected column of the double-sided charge trapping non-volatile memory unit 2〇5 is connected to the word hit 235a ^ 235b ... 235H . 235j ^ 235j+l ... 235m.l ^ 235m t' thus also connected To the selected double-sided charge-trapping non-volatile memory single & 的5 control paste pole' where the selected character line is applied to the character threaded planning voltage level (u. The uncharacteristic column of the memory unit 2G5 is connected to the character line gamma of the volatile corpus _ of the present invention, 2 、, ··· 2 2, 2 、, 235j+b.. =35m-l, 235m The remaining word line. The word line controller isolates the word lines, 235 bu, yang j, 23 +1, ..., 35111·1, 235m unselected word lines, and佑='s double-sided charge-trapping non-volatile memory unit 2()5 is set to ground reference voltage level 32 200845014 #bit 7G line console 230 generates double-sided flash memory unit for pair of selected columns〇 5, each of the electric capture area, the program, the butterfly must be riding the bit thread-based voltage program planning lightly (1) throwing the record 225a, 2 now, 225... line 225η-卜225η towel related bits line 'And the choice of the double-sided charge-trapping non-swing n = the early το 205 of the source and the 1st level of the brewing is based on the binary digital data into the play, it is looking for the second entry: New Zealand The first and second storage areas of the New York County light surface charge trapping (four) non-volatile memory unit 205 are stored as captured charges. Examples of such levels of the binary digital data are shown in Table i.

The erasing of the non-volatile memory array of the double-sided charge trapping non-volatile memory unit 205 of the present invention is illustrated in Figures 2a and 7b. The erase is displayed as a column erase, - the selected column is selected from the word line 235a, 235b, ··· 235H, 235j, 235j+b··· 235m-l, 235m selected word line reception is controlled by the word line A word line is applied to erase the voltage level (Vers). Injecting hot electrons into the charge trapping region for the η-through 迢 double-sided charge trapping non-volatile memory cell 2〇5 provides a character miscellaneous voltage level of +15V to about + shoulder. Alternatively, if the double-sided charge trapping non-volatile memory cell 2〇5 & ρ·channel device, the word line erase voltage level supplied to the charge trapping region into the thermoelectric hole is from about _15V. Up to about _20V. The word line controller 250 applies a ground reference voltage level (〇v) to the unselected word lines of the word lines 23祉235b, . . . 235H, 235j, 235j+1, . . . 235m-:l, 235m. And thus also applied to the double-sided charge trapping non-volatile memory unit 2〇5 to prevent the captured charge from the first and the first of the unselected double-sided charge trapping non-volatile memory unit 2〇5 The two charge trapping regions are removed. Bit line control benefit 230 applies a ground reference voltage level (〇v) to each of the associated bit line pairs in bit line 225a, 225b, 225c, ... 225n-2, 225x1-1, 225n for complete Erase. In an array configuration, a particular cell requirement is not subject to the erase operation. In this case, the bit line controller 230 to the bit line 225a, 225b, 225c, ... 225H-2, 225n-b 22511 is specifically erased and does not need to be further erased. For the pair, apply a large inhibit level (Vn^) of approximately +7.5V to approximately +10V. Referring again to Figures 2a and 7c, the reading of the double-sided charge trapping non-volatile memory 33 200845014 single 205-read column is described. A selected column of double-sided charge trapping non-volatile memory cells has a word line read level (v_) applied to the word line plus, j 1 235j, 235j+1, ... 235m- l, 235m related word line pairs, and thus also applied to the selected double-sided charge-trapping non-volatile memory unit 2〇5 ugly control pole and bread street capture type non-volatile memory unit 2〇5 The unselected columns are connected to the array, and the meta lines 23 = ' 235b, ··· 235> 235j, 235j+b... 2 times _ 235 235m the remaining word lines. The word line controller encodes the unselected word lines of the word lines 235a, 235b, ... 235H, 235j, 235, ... 235m-: 1, 235m, and thus the unselected double-sided charges Capture = Foot-type non-volatile memory unit 2G5 is set to the word line read-through voltage level (^w). The word 兀 line read voltage level (Vpass) ensures that the double-sided charge-trapping non-volatile memory single unselected column of το 205 is not activated during reading. In order to take the first charge trapping region of the double-sided charge trapping non-volatile memory cell 2〇5, the bit wire_23G will be connected to the bit line center of the first charge trapping region, 225b: 225c The first strip of the bit line pair in the ..., 22Sn], 225n is set to the ground reference voltage (GV), and is connected to the second charge trap _ bit line, 2 said, 22^ 1··· The second line of the bit line pair associated with 225ϊ>2, 2251> 1, 225n towel is set to immersed reading power, (vDRAIN). As described above, the read voltage level (v_) must be incrementally changed by the non-critical boundary voltage (VPVn) in the ic diagram to determine the selected double-sided charge trapping non-volatile memory unit 2G5. The program-dependent state of the first-charge trapping region. In order to read the programming state of the second charge trapping region of the double-sided charge trapping non-volatile memory cell 2GS, the bit line is controlled to be connected to the bit line 2 of the first charge trapping region, 2b: 225:, 225., 225η·2, 225η·1, 225η, the first bit of the relevant bit lining is set to the polarity read voltage (V_)' and will be connected to the second charge trapping The bit line of the region, =5b, 225:, ··· 225η-2, 225η·1, 225η, the second bit setting of the relevant bit line pair, the ground reference voltage _. Again, as described above, the read voltage level (乂诵) must be incrementally changed through the critical boundary voltage levels (%▽〇) shown in Figure lc to determine the selected double-sided charge trapping non-volatile The second charge trapping region of the memory unit 2G5 is programmed. Please note that the immersive read voltage level (Vd_) must be large enough to overcome the threshold voltage of the first and second charge 34 200845014 capture regions and insufficient to cause soft writing of the double sided charge trapping non-volatile cell 205 . During the f f read operation, a sense amplifier in the bit line controller 230 determines whether the selected two-sided capture type non-volatile second memory unit 2〇5 is conductive in all directions. According to the critical threshold (ypVn) and the double-sided charge profile = I conduction: the _ amplifier is determined in (4) fine __ formula: shell material, sub-data registration / output bus 645 the binary digit Data is transferred to an external circuit. Referring again to Fig. 8, the construction of the double-sided non-volatile memory unit of the present invention is carried out. The township office (4) turns the memory fresh element is provided (block 700) and is configured by column and row (block 7〇5). The double-sided non-volatile memory unit on each row of the double-sided non-volatile memory array of the present invention forms a __string of square capture and scaly memory fresh elements (blocks. a (four) string-top double-sided charge trapping non-volatile memory cell to each of the double-sided charge trapping non-volatile memory cells. Similarly, a crystal is connected (block 715) to each double-sided charge trapping non-volatile memory cell. Volatile memory unit = double-sided money-like forwarding counter unit = ^ each line of the memory unit is related to the bit line (block 7 outside "= top Ϊ select ^^ surface charge capture type non The volatility record is related to the adjacent line of the cell. The source/source of each anode is connected to (block 725) the first post-pair of the associated bit line pair. /not connected to (block 725) the associated bit ft: the two bit line controller is coupled to the block BO of the non-volatile memory array of the present invention) the associated bit line pair. a line and each of the double-sided charge trapping non-material elements. The double-sided charge 敝-type scalar memory unit is connected丨 丨 = 735) instead of having a _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ a control gate of the memory cell. The top selects the crystals of the set of double-sided charge trapping non-volatile memory cells of each group. 200845014 == there is a _ bit line-long-strip connection, and the bottom The transistor is selected to be connected to the second strip of the bit line pair ' thus forming a bit line structure of the father-join of the non-volatile memory array of the present invention.

A portion of the non-volatile memory array 2 of the present invention shown in Figure 2a is illustrated. As described in FIG. 2a, the double-sided charge trapping non-volatile memory unit 2〇5, 鸠, 厅, and· are connected in a row on the non-volatile memory array of the present invention to form a double Surface charge trapping non-volatile memory unit 2G5 (10) fine series string. Each of the NAND series strings 21a, 21〇b, 210c, 210d has a top selection transistor 215a, b and 215c and a bottom per transistor 22a, 220b and 220c. Each of the top selection transistors 215a, 215b, and 215c has a top-side double-sided charge-type non-volatile memory cell 2 with a first source/no-pole connected to each of the tantalum series strings 21a, 210b, 210c, and 210d. 〇5 is not very good. Each of the bottom selection transistors 2, 2 and 22〇c has a first source/no-pole connected to each of the NAND series strings 21〇a, 210b, 21〇c, and 21〇d. The source of the non-volatile memory cell 2〇5. Select the cell core, weave, and 215 at the top. And the selection of the bottom of the transistor, the application and the secret of the application are interchangeable, so it is designated as the first and second source / no pole for clarity.

A second source/drain of the top select transistors 215a, 215b, and 215c is coupled to the first strip of associated bit line pairs in bit lines 225a, 225b, 225c, and 225d. Each bottom select transistor 220a, 220b, and 220c has a second source/nothing connected to a second strip of associated bit line pairs in bit lines 225a, 225b, 225c, and 225d. Each row of the non-volatile memory array 2 of the present invention (in this embodiment, one of the nand series strings 210a, 210b, and 210c) and one of the bit lines 225a, 225b, 225c, and 225d Related to the bit line. Each of the associated bit line pairs in bit lines 225a, 225b, 225c, and 225d is more related to a first adjacent row 210a, 210b, and 210c of the double-sided charge trapping non-volatile memory cell, and The second line of the pair of bit lines 225a, 225b, 225c, and 225d is further connected to a second adjacent line 21 (^, 21〇1), and 210 of the double-sided charge trapping non-volatile memory unit. (:Related. The first adjacent row 21 (^, 21〇13 and 21〇 (: a second source/no pole of the top selection transistor is connected to the bit line 225&, 22513, 22 and 225 ( 1 in the 36 200845014 related bit line pair, and a source/drain of each bottom selection transistor of the second adjacent row is connected to the bit line 21, 225b, 225e and 225d The bottom selection transistor on an adjacent row of the top selection transistors 21%, 21A and 215c, and 2103⁄4 210b and 210c on the first row of the first pair 210a, 210b, and 210c 22 plus, 220b and 220c are connected to one of the bit lines 225a, 225b, 225c and 225d, thus providing the intersecting connections of the present invention For example, the row containing the NAND series string 210b is associated with the bit lines 225b and 225e. The first adjacent NAND series string 210a is associated with the bit line: and the bottom is selected for the transistor The second source/drain of 220a is connected to bit line 225b. The second adjacent nand series string 210c is associated with bit line 225c and the second source/nopole of top select transistor 225c is connected to the bit A line 225c. All of the bit lines 225a, 225b, 225c, and 225d are connected to the bit line controller 23A. The bit line controller 23G is a selected double-sided charge trap type non-volatile memory unit 2 5 providing a bit line operating voltage necessary for programming, reading, and erasing the captured charge, wherein the captured charge represents a charge trapping region of each selected double-sided charge trapping non-volatile cell a plurality of digital data bits. A control gate of each double-sided charge trapping non-volatile memory unit 205 located on each column of the non-volatile memory array 2 of the present invention is connected to the word line 2 ,...23, 235j, 235j+: l,··· 235 One of the m. The gates of the top selection transistors 2i5a, 21A, and 2(5) are connected to the top selection gate 'line 24〇a # 24〇b. This embodiment of the non-volatile memory array 200 of the present invention. The top select transistor 2, (4) and (10) are connected to one of the top select gate lines 240a* 24〇b, and the other two of them are connected to the top select gate lines 240a and 24〇b The other one. The gates of the bottom selection transistor Wei, and 220c are connected to the bottom selection gate, line 245. All word lines 2, 2, 2, 235, 235, +1, 235, 235m, top select gate lines 240a and 240b, and bottom select gate lines are connected to a sub-line controller 25〇 . The word line controller, the word line operation = pressure, the selection program depends on, reads, and erases the trapped (four) charge, and the captured private charge represents each selected double-sided charge trap type non-volatile memory. A plurality of digital data bits within the charge trapping region 37 200845014 of the cell 2〇5. "The NAND series string sets 210a, 210b, and 210c of the double-sided charge trap type non-volatile memory unit 205 having the shared word lines 235a, ... 235j-1, 235j, 235j+1, ... 235m are defined as one page. Program planning, erasing, and reading can be performed on a page or half page basis, as explained below. In the following description of the operation, the word line controller 25 starts with the appropriate voltage level. A line WLj 235j for programming, erasing, or reading the selected double-sided charge trapping non-volatile memory cells 2〇5a, 205b, and 205c. Simultaneously, the word line controller is The top select line 24 and 24 〇 b apply appropriate select line voltage levels to activate the top select transistors 215a, 215b, and 215c, and apply the appropriate select line voltage level to the bottom select line to initiate the bottom select transistor 22〇a, 22〇b*22〇c, thus connecting the NAND series strings 210a, 21〇b, and 21〇c with the bit lines 225a, 22沁, 22 and 225d φ. In order to program the following devices in sequence: the selected pair Charge-trapping _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The second charge trapping regions 270a, 270b, and 270c are programmed. The word line controller 250 initiates the character threaded planning voltage source gamma in FIG. 5, thus applying the very large value to the word line WLj term. The program gauge pressure. This very large program planning voltage is then applied to the selected double-sided charge-trapping non-volatile memory unit 2, 2〇5b and 205c control gates. Word line controller, starts The first select threaded planning voltage source · 537 ' thus applies a moderately large selection voltage to the gates of the top lion cell, biliary and germanium to activate the top select transistors 215a, 215b and 215c, thus aligning the Nand series 2i0a, 2i0b, and 2i〇c are connected to bit lines 225a, 2, 2仏 associated therewith. The word line controller 250 connects the ground reference voltage source 539 in FIG. 5 to the bottom turns 220a, 220b, and 220c. Gate to cancel the start of the bottom selection transistor 2 Thus, the double-sided charge trapping non-volatile memory unit 205 at the bottom of the NAND series strings 21a, 21〇b, and 210c is prevented from being connected to the second bit associated with the bit lines 225a, 225b, 22 The bit line controller 23() starts the first bit threaded programming Laiyuan 617 because: 2008 200814 applies a bit threaded planning voltage (VBLn) to each of the element lines 225a, 225b, 225c, and 225d. The bit threaded planning voltage (VBLn) is transferred to the first electrical capture region 265a of the selected double-sided charge trapping non-volatile memory cells 205a, 205b, and 205c via top select transistors 215a, 215b, and 215c, 265b and 265c.

After the first charge trapping regions 265a, 265b, and 265c of the selected double-sided charge trapping non-volatile memory cells 205a, 205b, and 205c are adequately programmed, the word line controller 250 cancels the first selected threaded plan. Voltage source 537, and ground reference voltage 539 of FIG. 5 is coupled to the gates of top select transistors 215a, 215b, and 215c to sever top select transistors 215a, 215b, and 215c. The word line controller 25 initiates the second selected threaded planning voltage source 538 of FIG. 5, thereby providing a modest large selection voltage to the gates of the bottom select transistors 22a, 22〇b, and 22〇c to The bottom electrodes are selected to turn on the transistors 22〇a, 22〇b, and 22〇c. The conduction of the bottom select transistors 220a, 220b, and 220c turns the second charge trap regions 270a, 270b, and 270c of the selected double-sided charge trapping non-volatile memory cells 205a and 205b with associated bit lines 225b, 225c and 225d connection. The bit line controller 230 activates the second bit threaded planning voltage source 618 of FIG. 6, thereby applying a bit threaded planning voltage (vBLn) on the associated bit lines 225b, 225c, and 225d, the bit line A threaded planning voltage (VBLn) is also applied to the second charge trapping regions 270a, 270b, and 270c of the selected double-sided charge trapping non-volatile memory cells 2〇5a, 2〇5b, and 2〇5c. ° During word programming, all word line controllers connect unselected word lines of word lines 235a, ... 235 > 1, ..., 235m to the ground reference voltage source in Figure 5, for the present invention The selected double-sided charge-trapping non-slip mark on the array of the non-volatile memory array 2〇〇, the fisherman, the crane* version of the read-forward, the red book, the non-volatile memory array Half of the page is implemented. The half-page is a double-sided electrical capture type f volatile memory unit 2〇5 NAND series string group 21〇a, 21% and the intersection is to perform half page reading, and the word line controller 250 starts the first Selecting the line reading power ii Meng Jiedi a selection line reads the voltage source 551, thus the voltage level of the power voltage source Vdd is applied to the top selection line 24〇a and the bottom selection line 245, and then moved to The top selects the electrical = body 39 200845014 215a and 215c, thus connecting the first half of the non-volatile memory array 2A to the associated bit lines 225a and 225c. Word line controller 250 connects top select line 240b to ground reference voltage source 539 of FIG. 5 to cancel activation of top select transistor 215b from bit line 225b associated with top select transistor 215b. In order to read the first charge trapping regions 265a and 265c of the selected double-sided charge trapping non-volatile memory cells 205a and 205c, the bit line controller 230 sets the first metaphysical bit lines 225a and 225c with the sixth The ground reference voltage 628 in the figure is connected and the bit line no-pole voltage source 627 in the Figure 6 is activated, thereby shifting the read gate voltage (Vdrain) to the second alternating bit lines 225b and 225d. The word line controller 25A initiates the read voltage source 546, thereby shifting the read voltage (Vr£ad) to the control gates of the selected double-sided charge trapping non-volatile memory elements 205a, 205b, and 205c. The pole of the control gate is turned on or not = depending on the value of the master voltage (ν^^). In addition, word line controller 250 increments the voltage level of the read voltage (Vread). The word line controller 230 senses the current through the selected double-sided charge trapping non-volatile memory cells 205a and 205c to determine the critical and charge levels of the double-sided charge trapping non-volatile memory cells 205a and 205c. The quasi-values thus determine the values of the plurality of digital data bits remaining in the first charge trapping regions 265a and 265c of each of the double-sided charge trapping non-volatile memory cells 2〇5a and 205c. "After the values of the plurality of digital data bits are determined, the second charge trapping regions 270a, 270b, and 270c of the double-sided charge trapping non-volatile memory cells 205a, 205b, and 205c are subsequently read. The line controller 230 connects the second alternating bit lines 22 and 22 to the ground reference voltage 628 of FIG. 6 and activates the bit line drain voltage source 627 of FIG. 6, thus The immersive voltage (vDRAIN) is shifted to the first alternating bit line 22 and 225c. The word line control, 250 initiates the read voltage source 546, thereby shifting the read voltage (v_) to the selected double sided charge The control gates of the capture type non-volatile memory cells 205a, 205b and 2〇5c, the control, the polarity & pass or not depends on the value of the capture voltage. Furthermore, the word line controller mo hands t? Taking the voltage level of the voltage (VREAD), determining the criticality of selecting the double-sided charge trapping non-volatile memory cells 205a, 205b, and 205c and selecting the double-sided charge trapping non-volatile cells 205a, 205b, and 205c The second charge trapping region 27〇a, the value of this and the r^, the level of the charge level, and thus the decision The values of the multiple 200845014 digital data bits in the second charge trapping regions 27a, 27〇b, and 27〇c of the double-sided charge trapping non-volatile memory cells 205a, 205b, and 20 are selected. To perform a half page read, the word line controller 25 initiates the first select line read voltage source tear and the second select line read voltage source 55, thereby shifting the voltage level of the power supply ship Vdd to the top. Select line 240b and bottom select line, and thus to top select transistor and bottom select transistor 220b, and connect the second half of non-volatile memory array 2 to associated bit line 225b and 225c. The word line controller 250 connects the top select line 240a and the bottom select 'line 24h to the ground reference voltage source S39 of FIG. 5 to take the top select transistor 2i5a from the associated bit lines 25a and 225c. And 215c, and selecting bit lines 225b and 225d associated with transistors 220a and 220c from the bottom cancels the activation of bottom select transistor 22 and φ2. For reading the selected double-sided charge trapping non-volatile memory unit 205b First charge trapping region 265b, The line controller 230 connects the second alternating bit line 22 to the ground reference voltage 628 in FIG. 6, and activates the bit line no-pole voltage source 627 in FIG. 6, thus reading the drain The voltage (VDRAiN) is shifted to the first alternating bit line 225b. The word line controller 250 initiates the read voltage source 546 and shifts the read voltage (Vr^) to the selected double-sided charge trapping non-volatile The control gate of the memory unit 205b, wherein the conduction of the control gate depends on the value of the read voltage (Vread). In addition, the word line controller - increments the voltage level of the read voltage (Vread). The word line controller 230 senses the current through the selected double-sided charge trapping non-volatile memory unit 205b to determine the criticality of selecting the double-sided charge trapping non-volatile memory unit 205b and the memory unit 2〇5b The value of the charge level, and thus the value of the plurality of digital data bits in the selected first-charge buffer region 265b of the double-sided charge trapping non-volatile memory unit 205b. After the values of the plurality of digit data bits are determined: the second charge trapping region 270b of the double-sided charge trapping non-volatile memory unit 205b is then read. The bit line controller 230 connects the second alternating bit line 225b to the ground reference voltage 628 in FIG. 6, and activates the bit line drain voltage source 627 in FIG. 6, thus reading the drain voltage (ydrajn) shifts to the first alternating bit line 225c. The word line controller 250 activates the read voltage source 546, thereby shifting the read voltage (Vread) to the control gate of the selected double-sided charge trapping non-volatile memory unit 2〇5a, 2〇 and 205c And the conduction of the control gate depends on the value of the read voltage (Vread). Additionally, word line controller 250 increments the voltage level of the read voltage (Vread). Word 200845014 catching the hair of the sacred element 2 Na's pendulum and what to catch (four) face-to-face collection of the 2G5b critical and selective 非 type non-volatile memory unit 2G5b (four) two charge capture 2 · love 2 ^ 1 = The value of the plurality of digital data bits in the second charge trapping region 27〇b of the double-sided charge trapping non-volatile memory unit 205b is selected. The % diagram illustrates a portion of the non-volatile memory array of the present invention shown in the figure. As described in Section 2b ®, except for the selection of the transistor at the bottom and the interpole of the fiber, the embodiment is tested. The bottom of the transistor and the gate of the fiber are connected to the bottom selection strand 245a. The bottom select transistor diverter is connected to the bottom select_line 245b. Bottom line selection 245a

The rows of 210c and 210c can be connected to the bit line sum (4), while the gates of the row %, the row 4, etc. of the ΝΑΝ〇 series string 鸠 are connected to the bottom of the row #% crystal 22Gb to the bottom selection gate that is deactivated Line 245b. · As described above, the 双面_联组组, 鸠, and 210c of the double-sided charge-trapping non-volatile memory unit 2〇5 having a shared word line, ... 23SH, 235j, 23, ..., 235m Is defined as a page. Program planning, erasing, and reading can be performed on a page or half page as described below. In the operational description described below, the word line controller 25 turns on the word line % 235" at the appropriate voltage level, thus the selected double-sided charge trapping type, "cells 2G5a, 2G5b, and 2G5e" It lines shout, erase, or read. Simultaneously, the word line controller applies appropriate select line voltage levels to the top select wires and turns to activate the top select transistors 215a, 215b, and (10), and applies the appropriate select lines to the bottom select lines and 245b. The voltage level is used to activate the bottom select transistors 22 〇 & 22 and 22 〇 c, thus connecting the NA nd series string, 鸠 and · with the bit lines 2 仏, 2 。, 225 c and 225 d. The autumn plan for the king page is the first charge trapping region 265a, 265b* 265c of the selected double-sided charge trapping non-volatile memory cells 205a, 205b and 205c, the selected double-sided charge trapping The second charge trapping regions 270a, 270b, and 270c of the non-volatile memory cells 2〇5a, 2〇5b, and 2〇5c are programmed. The programming of the structure of Figure 9b is equivalent to the programming of the 9a program, except that both the bottom selection line 245a and the 鸠 42 200845014 are simultaneously activated. , 'There are multiple bottom selection lines 2 and 245b allow multiple digital f-levels to be simultaneously stored in the selected double-sided charge-trapping non-volatile memory unit 2〇5a, 2〇5b and 2 The first charge trapping regions 265a, 265b, and 265c, and the second charge trapping regions 27a, 270b, and 270c. Simultaneous storage of multiple digital data bits is done in half of the page units. - In order to program the first-half page unit, the word line controller 25 starts the word τ Threaded Planning Voltage Source 536 of Figure 5 to apply the very large programming voltage to the word line WLj 235j . The very large programming voltage is then applied to the control gates of the selected double-sided charge trapping non-volatile memory cells 205a, 205b, and 205c, and the word line controller 25 initiates the first selected threaded planning voltage. Source 537 applies the modest large programming voltage to the gates of the top select transistors 215a and 21, thereby activating the top select transistor and 215c, and connecting the NAND series ♦ groups 210a and 210c to the bits associated therewith. Yuan 22 brother and 225c. The word line controller 250 connects the ground reference voltage 539 of FIG. 5 to the top select line 240b and thus also to the gate of the top select transistor 215b to connect the NAN〇 series string 210b with its first associated bit. Line 225b is isolated. The word line controller 250 activates a second selected threaded planning voltage source 538 to apply a moderately large programming voltage at the gates of the bottom select transistors 220a and 220c, thereby enabling the bottom k-type pens 220a and 220c And connecting the bottom double-sided charge trapping non-volatile memory unit 205 of the NAND series string sets 210a and 210c to the second bit line 225b and 225d associated therewith. The word line controller 250 connects the ground reference voltage 539 of FIG. 5 to the bottom select line 245b' and thus also to the gate of the bottom select transistor 220b to connect the NAND series string 210b with the second bit associated therewith. Line 225c is isolated. The bit line controller 230 activates a first bit threaded planning voltage source 617 to apply a bit threaded planning voltage (VBLn) on each of the bits 220a and 22C. The bit threaded planning voltage (VBLn) is shifted to the top select transistors 215a and 215c, and the first charge trapping regions 265a and 265c of the selected double-sided charge trapping non-volatile memory cells 205a and 205c. Simultaneously, the bit line controller 230 activates the second bit threaded planning voltage source 618 in FIG. 6 to apply a bit threaded planning voltage (VBLn) on the bit 2008 lines 225b and 225d. The bit threaded planning voltage (VBLn) is also applied to the second charge trapping regions 270a and 270c of the selected double-sided charge trapping non-volatile memory cells 205a and 205c. In order to program the second half page unit, the word line controller 25A maintains the activation of the character threaded planning voltage source 536 of FIG. 5 to apply the very large programming voltage to the word line WLj. 235j. This very large programming voltage is then applied to the control gates of the selected double-sided charge trapping non-volatile memory cells 205a, 205b and 205c. The word line control 250 initiates a first selection of the threaded planning voltage source 537 to apply the modest large programming voltage to the top select line 240b and thus also to the gate of the top select transistor 215b to initiate the top selection. The transistor 215b connects the NAND series strings 21〇b and 21〇c to the bit line 225b associated therewith. The word line controller 250 connects the ground reference voltage 539 of FIG. 5 to the top select line 240a, and thus also to the gates of the top select transistor 21 and 215c to relate the NAND series strings 210a and 210c thereto. The first bit line 225a and 225c are isolated. The sub-line controller 250 activates the second selected threaded planning voltage source 538 to apply a moderately large programming voltage at the gate of the bottom select transistor 220b, thereby activating the bottom select transistor 220b' and NAND in series_group 210b The bottom double-sided charge trapping non-volatile memory unit 205 is coupled to a second bit line 225c associated therewith. The word line controller 250 connects the ground reference voltage source 539 of FIG. 5 to the bottom select line 245a, and thus also to the gates of the bottom select transistors 220a and 245c to connect the NAND series string sets 210a and 245c with its second The strip-related bit lines 225b and 225d are isolated. The bit line controller 230 activates a first bit threaded planning voltage source 617 to apply a bit threaded planning voltage (vBLn) on each of the bits 220b and 220d. The bit threaded planning voltage (VbliO is transferred to the top select transistor 215b, and the selected double-sided charge trapping non-volatile 5 hex early 205b dian-charge trapping region 265b. Simultaneously, bit line control The device 230 initiates a bitwise threaded planning voltage source 618 in the diphant diagram to apply a bit threaded planning voltage (VBLn) on the associated bit line 225c, thereby also threading the bit threaded planning voltage ( %)^) applied to: the second charge trapping region 44 of the selected double-sided charge trapping non-volatile memory cell 2〇5b 200845014 270b 所有 During the programming period, all word line controllers will have word line 235a, The unselected word lines of ... 235j4, 235J+1, ..., 235m are connected to the grounded spring 539' in Figure 5, for selection on the array of non-volatile memory arrays 200 of the present invention. The read operation of the double-sided charge trap type non-volatile memory cells 205a, 2〇5b, and 2〇5c is performed on the half page of the non-volatile memory array 2()() of the present invention. Performing the first-half-face reading, the word line controller 250 starts the first selection Line read voltage source 548 and second select line read voltage source 551, thereby shifting the voltage level of supply voltage source Vdd to top select line 2 and bottom select line 245a, respectively, and thus to top select transistor 21 The brother and the 21st brother thus connect the first half of the non-volatile memory array 200 to the associated bit lines 225a and 225A. The pre-wire controller 250 connects the top select line 240b and the bottom select line 245b. To ground reference voltage source 539 of Figure 5, to cancel the top select transistor = 5b from the associated bit line 225b, and to cancel the start of bottom select transistor 22 from the associated bit line 225c. The two-sided charge trapping non-volatile memory cells 2〇% and 2〇5c of the first charge trapping regions 265a and 265c, the bit line controller 23〇 will be the second alternating bit line 22 north and 22 brothers The ground reference voltage 628 in FIG. 6 is connected, and the bit line drain voltage source f 7 - ' in FIG. 6 is activated to thereby shift the read drain voltage (%_) to the _ alternating bit line 2仏 and 2仏. The subscale controller 250 activates the read voltage source 546 and will read ^ Bladder pressure) to transfer: the selected transfer type double-sided charge enemy facilities and control unit miscellany York side dressing of the electrode, the control gate of $ depends on the value of the read voltage. In addition, the word line controller 25 transmits the voltage level of the voltage (Vr£ad). The word line controller 23 〇 senses the current through the selected two-charged non-volatile memory unit 2G5a and the applied current to determine the selection of the bread-capturing non-volatile memory unit SO% and 2〇5〇. The critical value and the value of the charge level applied to the non-volatile memory cell are selected, thereby determining the margin, and selecting the double-sided charge trapping non-volatile memory cells 205a and 205c The values of a plurality of digital data bits in a charge trapping region 265a and 265c. After the values of the plurality of digit data bits are determined, the second charge trapping regions 270a and 27〇c of the double-sided charge trapping non-volatile memory cells 205a and 205c are then selected. The bit line controller 230 connects the second alternating bit line 225b and the view to the ground reference voltage 628 in FIG. 6, and activates the bit line drain voltage source 7 in FIG. 6, thus reading汲 电, (VDRAiN) # multi-turn to the first-alternating bit line 225a and take. The word line controller fine-starts the read voltage source M6, and the sulfur read voltage (v_) is transferred to the double-sided charge trap type non-volatile memory unit 205a, the control gate of the repeat and the ,, the control terminal The derivative or not depends on the value of the read voltage. In addition, the word line controller 25 〇 increments the voltage level of the read voltage (Vrbad). The word line controller 23 〇 senses the current through the non-volatile memory unit and the pulse to determine the choice of double-sided electricity === the threshold of the body unit and the choice of the double-sided charge The values of the charge levels in the second charge trapping region and 27〇c of the volatile buddy unit cells 205a and 205c are retained in the selective double-sided charge trapping non-volatile memory cells 205a and 205c. - the value of a plurality of digital data bits in the charge trapping regions 27Ga and 27Ge. The second half of the page reads, the word line controller 250 activates the first selection line to read the voltage of the second brother - the transparent selection of the electric lion Therefore, the voltage of the power supply circuit v is 24 〇 b 24 " * 〜 and the bottom port is selected to the transistor 220b, thus connecting the non-volatile memory array 200 to the relevant bit 兀, line 225b And the 225C. The word line controller 250 connects the top and the second selection lines to the ground reference voltage source 539 of FIG. 5 to select the bit line 225a associated with the 3? 215 & 2150 and 225c cancels the top selection of 225Γ; ^ 215C 5 220a ^ 220c Shaw starts the bottom selection of transistors 22〇a and 22〇c. Read the selected double-sided = burst memory unit _ first charge trap area lion ^ and the money ή 的 的 疋 225 225 225 225 225 225 225 225 225 225 225 225 225 225 225 225 225 225 225 225 225 225 225 225 The line has no pole voltage source, 627, thus shifting the bucker voltage (Vd draw) to the position of the line twister. The word line controller 250 starts the read voltage source, 546, because 205 b'丨 咖 ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) The twist line controller 250 increments the read voltage (v_) (four) pressure level. Character 46 200845014 f control ^ 3 〇 _ thief light ridge ship type Lin Fa decided to choose double-sided money summary type hair mask unit Listen =; value = ί volatile steroid unit hired 1 squad test, thus determining the margins in the stipulations and the capture of non-volatile memory

The value of multiple number of gift bits in 265b. (4) Private capture S After the value of multiple digit data bits is determined, the first sleeve (four) of the non-volatile record unit ,, select the capture of the glory - a one of the brothers to capture £ 270b. The bit line controller 230 connects the line 225b to the ground reference power M 628 in Fig. 6, and activates the sixth source, 627 'and thus reads the immersive power, although the coffee is) (four) to the first

Dengzi 70 line controller 250 starts to read the power source 546, thus binding the reading [OW] to the face of the face (4) non-spending series of Yuan Yu fishing, Ju and 205c control side pole, miscellaneous coffee The conduction does not depend on the value of the read electric grind (vy. In addition, the 'word line controller 25 〇 increments the read voltage ^). The word ^ control 230 senses the reading through the selection of the double-sided charge-trapping non-volatile memory unit ,, in order to compare the two-sided riding of the forward-looking ship unit and select the double-sided charge 转发The value of the charge level in the second charge region of the face 2G5b, _determining a plurality of digital data stored in the second charge trap region 27b of the double-sided charge trap type non-volatile memory unit 205b The value of the bit. The erase of the 9a and 9b diagrams is as shown in the % diagram, the erase is shown as a column mode erase, and a selected column is selected from the character line %, 23sb, ... 2 23 Guardian... The ^^^1, 235111 towel selection force word line receives a word line erase voltage level (vERS) applied by the word line controller 250. This is used for the η·channel double-sided charge trapping non-volatile memory unit 2〇5. The word line erase voltage for injecting hot electrons into the charge trapping region is A_5V to about 20V instead, if double-sided charge The capture type non-volatile memory unit is moved to the ρ· force device. The energy level of the ancestors of the lining thermoelectric ancestors is from the large, 15V to about -20V. The word line controller 25 施加 applies the ground reference voltage level (〇v) to the pre-element 235 &, 2351^, .. 235 > 235 』, 235 』 +1, ... 235111 - 235 351111 The selected word το line is thus also applied to the double-sided charge trapping non-volatile memory unit 2〇5 to prevent the trapped charge from the double-sided charge trapping non-volatile memory unit Ms A 47 200845014 and the brothers ^ one electric capture area was removed. The bit line controller 23G applies a ground reference voltage level (〇v) to each of the bit line pairs in the bit lines 225a, 225b, 225e, ..., 225n_2, 225n, 225n to enter & In an array configuration, certain units are not required to undergo this erase operation. Under this =: bit το line controller 23G is sufficiently erased into bit lines 225a, 225b, 225e, ... 225n-2, 225n_/, 22511 and does not need to be erased step by step. There are _ bit line pairs, and the application of two = +7.5V to about +i〇V forbidden voltage level). Although the above description is based on the preferred embodiment of the present invention, it is understood that the form and the scope of the invention can be varied and the spirit and scope of the invention. & [Simplified Schematic] Lath and lb® sub-counties - double-sided charge generalization reversal and cross-section; ^ Figure ^ This program is used to program double-sided charge trapping non-volatile memory Threshold voltage of each memory cell of the array of body cells (VW (4): a pattern of the number of double-sided charge trapping non-volatile brother cells having a specific threshold voltage, which is used by the control device of the present invention The program planning circuit implements multi-bit programming; the 2a and 帛2b diagrams are the multi-level routable units of the present invention having intersecting columnar bit line structures. A schematic diagram of the second solid detail; FIG. 3 is a single tantalum series with multi-level programmable bi-directional non-volatile memory cells having interconnected columnar bit line structures for each column. A schematic diagram of one of the arrays of arrays; FIG. 4 is a block diagram of a plurality of NAND series strings of multi-layer programmable non-volatile memory cells of the present invention. The unit has a symmetry Connected columnar bit line structure; 48 200845014 FIG. 5 is a diagram of a character line controller of an array of multi-level programmable double-sided non-volatile memory cells having intersecting columnar bit line structures of the present invention FIG. 6 is a schematic diagram of a bit line controller of an array of multi-level programmable double-sided non-volatile memory cells having intersecting columnar bit line structures; 7a, 7b, And the array of 7c for programming, erasing, and reading the array of multi-level programmable double-sided non-volatile memory cells of the present invention having a columnar bit line structure with f-joined connections a table of voltage requirements; FIG. 8 is a flow chart of a process for forming a multi-level programmable double-sided non-volatile memory unit having intersecting columnar bit line structures of the present invention; and 9a and %Fig. For the second aspect of the present invention, the continuation layer of the programmable layer of acid-transferable volatile memory unit having the intersecting structure of the present invention is used to illustrate the riding of the alcoholic layer. Volatile memory 5,205

10 15 20 30 35 40 45 50 55 60 65, 70 [Description of main component symbols] Double-sided charge trap type non-volatile memory cell substrate> and polar region source region oxide layer charge trapping layer-dielectric Oxide layer polycrystalline layer/gate source line terminal first bit line terminal bit position line terminal charge trapping area 100, 110, 120, 130 level 49 200845014 102 , 112 105 , 115 200 210a ~ η 215a 〜 η 220a η 225a η η 230 235a 〜 m 240a, b 245a, b 250 300 310a 〜 315a 〜 340 430a 〜 340 330 355 400 425a 〜 n 430 435a 〜 m 44〇a 〜 m 445a 〜 m 450 455 505 510, 122, 132 threshold voltage, 125 program planning voltage non-volatile memory array NAND series string top selection transistor bottom selection transistor bit line bit line controller word line top selection gate line bottom selection gate Polar line word line controller non-volatile memory array NAND series string set top selection transistor bottom selection transistor bit line controller word line controller double-sided charge trap type non-volatile memory block non-volatile Remember The top of the array bit line bit line controller selected word line at the bottom gate line selection gate line word-line controller formula sided charge trapping non-volatile memory block erase control signal planning program control signals 200,845,014

515 Read Control Signal. 520 Control Decoder 525 Address Word 530 Character Line Address Decoder 535 Program Planning Circuit 536 Character Threaded Planning Voltage Source 537 First Select Threaded Planning Voltage Source 538 Second Select Threaded Planning Voltage source 539 connection line 540 word line erase circuit 541 first selection line erase voltage source 542 second selection line erase voltage source 543 word line erase voltage source 544 connection line 545 word line read circuit 546 word Yuan line read voltage source 547 Read voltage source 548 First select line read voltage source 550 Column select circuit 551 Second select line read voltage 555a ~ k Top select gate line 560a ~ m Word line 565a~k Bottom Select Line 600 Bit Line Controller 605 Control Decoder 610 Bit Line Selection Circuit 615 Bit Threaded Planning Circuit 617 First Bit Threaded Planning Voltage Source 618 Second Bit Threaded Planning Voltage Source 51 200845014 620 Bits Line erase circuit 622 bit line disable voltage source 623 connection line 625 bit line f buy circuit 627 bit line drain voltage source 628 connection line 630 bit line selection 63 5a~η bit line circuit 640 sense amplifier 645 data entry / output bus block 700,705,710,715,720,725,730,735,740

52

Claims (1)

200845014 X. Patent application scope: 1. A non-volatile memory array, including: complex double-sided charge-captured forward memory configured by column and row. Her-style forwarding touch-only private axis at least = double = what capture type Non-initial recording unit, self-distributing (four) double-sided charge trapping two military: in a NAND series string of memory cells, each of the secret series series has two top-selective transistors and a bottom-selective transistor; a plurality of bit lines, the tree being connected to each of the double-sided charge-forwarding pairs and the bit-to-bit line, thereby causing the top 1 to be annihilated, the first of the related bit line pairs, And the source/;: and the pole of the two = are connected to the second one of the related bit line pairs, such that the first one of the bit line pairs of the 阙 is more than a double-sided charge trapping Volatile body # and making the first: in the associated bit line pair a first source of the first adjacent row of the first selected crystal Two, and the source/drain of the bottom select of the second adjacent row is connected to the associated bit line pair The first line; the _-bit line controller, which is connected to the plurality of bit lines, the bit element is privately planned, itemized, and erased, wherein the captured charge represents a choice Double-sided charge-trapping non-volatile memory cell - ^, digital data bit in the charge trap area. 2' ^The non-volatile memory array described in item 1 of the patent application scope includes: a plurality of words, each material line is not related to a column in the forwarding element (4) forwarding element; Jobs, each pair of wires connected to at least one of the NAND φ strings of the double-sided charge-type non-volatile memory unit; the top selects the gate of the electron crystal x body; 53 200845014 a plurality of bottom selections, each The bottom lion line connects at least one of the NAND series strings of the charge surface charge memory unit to the bottom of the NAND series string; and the sub-guar line lake H, Wei connects to the word line, The top selects the county and the bottom select line, and shifts the word line operating voltage for the captured charge selection, the program read, and the erase, wherein the captured charge represents each of the selected &amp;; a non-volatile memory array as described in claim 2, wherein the bit line controller includes : ^ - The first-bit threaded programming power source, its The associated bit line is the source/nothing pole of the top select transistor, and the first source trace and the pole of the selected dual capture memory unit are provided to represent the plurality of digits == wave And for the charge trapping region and the portion of the one or more digits of the poor material bit, the first j table, the younger line of the slave ship view, the double-sided electric turn of the turn The n, the pole/dip pole of the body k is provided to represent the multi-bit data bit ^, the plurality of threshold adjustment voltages, and thus the charge trapping region is set to represent the digits of the digits. The second level. For example, in the non-volatile memory array described in claim 2, the word line controller includes: A A-character threaded surface "source, side-voltage-cut voltage, wherein the voltage field is located in the The selected double-sided charge trapping system selects the double-sided charge-trapping non-volatile memory single- 2 I-to-one memory unit-charge scorpion thief. A non-volatile memory array as described in claim 2, 54 200845014 The word line controller includes: a first-lion threaded planning voltage source, which is selectively provided = Although it is _ 峨 峨 娜 娜 娜 娜 娜 娜 - The sub 7L line reads the voltage source 'which generates a plurality of critical thin voltages', with a fine = double = charge trapping type of non-volatile memory unit, a plurality of programs, cutting the critical power, the program planning the critical electricity county representative a selected one of the plurality of critical adjustment voltages of the knives of the digits of the digits; and the bit line controller comprises: 靖取; and a polar package tester $, which generates _bungee voltage,丨 赖 赖 准 准 准 准 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择a double-sided charge trapping non-volatile memory unit that activates the selection; a: ground reference voltage generator for generating a ground reference voltage, the ground referenced, via the bit line pair The first and second strips are selectively transferred to the first and second source/poles and poles; and a sensing circuit is coupled to the selected two sides via the pair of bit lines a charge trapping non-fluctuating 5 hexameric unit to the first and the first by the bit line pair Planning a program to detect the status bar on behalf of the plurality of digital data bits of the charge trapping region. 7. The non-volatile memory array of claim 2, wherein the word line controller comprises: a sub-line erase voltage source providing a very large erase for generating a voltage field Voltage, 55 200845014 wherein the voltage field is located between the traffic area of the double-sided charge trapping non-volatile memory unit and the control gate of the double-sided, charge-trapped non-volatile memory unit, and thus The charge trapping region injects a hot carrier to be extracted from the channel region of the double-sided charge trapping non-volatile memory cell; and the bit line controller comprises: - a second ground reference voltage generating chirp, The ground reference voltage is applied to the first and second drain/source. 8. The non-volatile memory array according to claim 4, wherein the double-sided charge trapping non-volatile memory unit is an η_channel memory unit. 9. The non-volatile memory array of claim 8, wherein the very large program programming voltage level ranges from about _6 〇 ν to about ι 〇 ν to cause the hot carrier to be injected A thermal hole is injected into the charge trapping layer. 10. The non-volatile memory array of claim 8, wherein the voltage of the plurality of critically-adjusted electric dust ranges from about +10 volts to about +60 volts, and is divided into intervals, the interval being sufficiently large The first and second portions of the plurality of the plurality of digit data bits can be determined. *11. The non-volatile memory array of claim 6, wherein the voltage of the plurality of critical side voltages ranges from about +20 V to 50 V, and is divided to distinguish the plurality of programming priorities. The amount of voltage increase. 12. For example, the non-volatile memory array described in the 11th patent application, wherein the = and the collar level must be a voltage level, which is large enough to overcome the first and second electrical capture regions. The critical power is not sufficient to cause soft writing of the double-sided charge trapping non-volatile memory unit. 56. The non-volatile memory array of claim 7, wherein the non-systematic erasing voltage level ranges from about +HOV to about +2 〇〇v to increase the double sided The charge-carrying turns to the miscellaneous voltage of the family. 14. The non-volatile memory array of claim 4, wherein the double-sided charge trapping non-volatile memory unit is a -P-channel memory unit. K is a non-volatile memory array with a patent coverage of 帛14, where a moderately large program is simple, from about %GV to about +V, so that ..., the carrier injection is injected into the charge trapping layer for the thermoelectric hole. I6. For example, in the non-volatile memory array according to Item 14 of the scope of the patent application, in the basin, the plural number of ships is from about 10,000 to about □, which is large enough to determine the plurality of digits. ^ ' is also divided. For example, the non-volatile memory array described in the scope of the patent application 帛6, wherein the voltage of the plurality of critical side cakes ranges from about _ to about v as a distinction between the plurality of programming priorities The amount of voltage increase. The core of the non-volatile memory array as described in the scope of the patent application, the threshold voltage of the charge-trapping region, and the soft writing of the raw and non-volatile cells, and the abundance of the double-sided charge-trapping The second electro-acoustic memory is used to reduce the repeatability of the pair as described in the application of the sputum, and the very large erase level ranges from about _15 〇ν to about (10), the surface charge Capture type _ _ _ _ _ _ _ _ _ _ _ · ' 57 19. 200845014 20. A non-volatile memory volume circuit comprising: a plurality of double-sided charge trapping non-volatile memory cell arrays arranged in columns and rows, the double-sided charge trapping on each row The non-volatile memory unit forms at least two double-sided charge-trapping non-volatile memory unit groups, and is disposed in a NAND series string of the dual-carrying non-volatile memory unit, each nand _ having a top selection power The crystal and a bottom selection transistor; a plurality of bit fields, the reduction is caused by the double-sided charge tearing test memory, and the memory is picked up, and the L-Gen is closed. The pole is connected to the bit line of the fiscal (4)-bar, and the job selection: the body-source/drain is connected to the second of the _ bit line pair, and: The bit line pair ___ is more related to the _ double-sided charge trapping type, the -first adjacent line of the memory unit, and the % of the _ bit line pair is the second A second adjacent/row of the surface charge-type non-volatile memory unit, wherein the first a source/no pole connection of the top surface transistor of the adjacent row, to the second row of the ray, and a source/drain connection of the bottom selection transistor of the second row To the first one-degree of the associated bit line pair; The control gates of all the double-sided charge-trapping non-swing-memory cells of the array in the array of the 健 各 各 ( 四 四 四 四 四 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 1_Line' each front squama is connected to the miscellaneous charge. Her type of forward characterization is at least one of the NAND series strings of the top unit. The top selects a gate of a plurality of lines of the transistor, reducing the load of the miscellaneous s. At least one of the bottom row of the NAND series string of the volatility unit is selected from the bottom of the transistor; the anode and the gate are separated from the bit line, which depends on the reduction factor line, and the voltage shift of the element Transferring to the selected double-sided charge-trapping non-volatile memory cell, thereby programming, reading, and erasing the captured charge, wherein the captured charge represents the double-sided charge selected by each of the selected 2008 200845014 a digital data bit in a charge trapping region of the 转发-type forward memory fresh element; and a sub-twist controller/, a reverse-to-sub-line, the top select line, and the bottom select line to shift characters Line operating voltage for the trapped charge Row selection, the program rules ^, read, and erase, wherein charge representative of the captured each of the selected charge trapping dual ^ Formula charge trapping non-volatile memory cell region of the data bits as many as the number of bits. 21) The non-volatile memory volume circuit as described in the scope of claim 2, wherein the sub-twist control | § comprises: - the word 70 thread-type ship view, raised side to generate __ light field - a very large planning voltage, wherein the voltage field is between the selected double-sided charge-trapping non-volatile body soap-pick-control pole, and the selection is light &quot;charge-captured forward-sense Between the i-channel regions, the hot carrier to be injected into the charge trapping region of the selected double-sided capture non-volatile memory cell is thus drawn from the channel region. ^ 22 · The non-volatile memory volume circuit described in the second paragraph of the patent application scope, the bit line controller includes: - the ^^^^^^^^^^^^^^^^^^^^^^ Volatility • The early source of the genius, providing the part of the multi-digit data bit, is difficult to achieve, and (4) the charge her area is set to represent the part of the plurality of digits. a first level of the hot carrier charge; and a second bit threaded planning voltage source providing the thin portion of the non-volatile memory fresh element to represent another portion of the plurality of digital data bits ^ Boundary adjustment electric red Dijon will be able to record the second level of the hot carrier charge in the far part of the bit. 23. The non-volatile memory volume circuit of claim 21, wherein the 2008 20081414 word line controller further comprises: - a word line read voltage source 'which generates a plurality of critical detection voltages One, to detect the selected double-sided charge ship error (four) sex note, single material, one of the critical electric x pressures, where the practiced critical electric grind is the part representing the plurality of digital data bits. The selected one of several critical adjustment voltages is generated. 24. The non-volatile memory volume circuit as described in claim 1, wherein the bit line controller further comprises: ', Ί and poles to generate 3', which generates a _ secret voltage level, Weiji The first and second strips of the voltage level passing through the pair of bit lines are selectively transferred to the first source and the second source, and depending on the t a charge level of 槪 to initiate the selected double-sided charge trapping non-volatile memory unit; a first-ground reference voltage generator 'for generating a ground reference voltage via which the first pair - the strip and the second strip are transferred to the first and second source embodiments; and - the sensing circuit, wherein (4) the spacer element is connected to the selected double-sided charge trapping non-volatile memory unit, and By means of the first and second strips of the bit line pair, the swaying state of the charge zone representing the multi-station data bit is pre-measured. The non-volatile memory volume circuit as described in claim 23, wherein the word line controller further comprises: ', a word line wipes away the Xia source, and the character line is connected to the chat. A double-sided charge trapping non-volatile memory cell providing a very large erase voltage for generating a voltage field, wherein the voltage field is between the double-sided charge trapping non-volatile memory cells of the chat The transport zone, and the control gate of the double-sided charge-trapping non-volatile memory cell selected by the 5th chamber, thus injecting into the charge trapping region, the double-sided charge trapping non-slip property to be selected from the 5 The hot carrier of the channel region of the body unit. 1 6 The non-volatile memory volume circuit of claim 1 , wherein the 200845014 bit line controller further comprises: applying the ground reference voltage to the first second ground reference voltage Generator, second drain/source. 27·如申谙真利铬囹筮who. 28. For example, the non-volatile memory volume circuit of the 2γth item of Shen Qing patent range, the very large program planning voltage level ranges from about -6.0V to about:; 0·0ν, to cause 9. The non-volatile memory volume circuit of claim 22, wherein the plurality of critically adjusted voltages of the electric dust range from about +1 〇 v to about +6 〇 ν, being the interval ' The interval foot dog is large enough to determine the plurality of digit data bits of the plurality of digits. ^ 3〇. The non-volatile memory volume circuit of claim 23, wherein the plurality of critical thin voltages range from about +2 〇v to about +5 〇v, and are drawn 31. The non-volatile memory volume circuit of claim 30, wherein the 1 汲 electrode level must be a voltage level that is large enough to overcome the first and second charge trapping regions. The threshold voltage is not sufficient to cause soft writing of the double-sided charge trapping non-volatile = body unit. &quot;^ 32. The non-volatile memory volume circuit of claim 25, wherein the very large voltage removal level ranges from about +15V to about +2〇ν to increase the double The threshold voltage of the surface charge trapping non-volatile memory cell. 200845014 33 body = 1 she specializes in the non-volatile memory integrated circuit described in Item 33, in which the programming order voltage level of the two Ili ranges from approximately +6·〇ν to approximately +L, to cause s~, The carrier is injected into the thermal trap to inject the charge trapping layer. 35. The non-volatile memory volume circuit according to Item 22, wherein the voltage range of the ❿=number boundary voltage is approximately torn, and is divided into a second shape and is large enough. The first plurality of the plurality of health data bits are the first non-volatile memory circuit described in item 23, and the threshold in the basin is about _ wide to about 5. Zheng Wei & Knife The number of programs is programmed to increase the threshold voltage. A = the non-volatile memory volume circuit described in the patent item 5%, "The voltage level of the immersion voltage must be "voltage", the threshold voltage of the charge capture zone, and not enough to make the brother - and the second The soft writing of the body unit. From the "facial surface cast her type of non-volatile memory 38.", as described in the non-volatile memory volume circuit described in the ninth patent range of Shen Qing, the voltage level range of Γ~t is from approximately _15·ον to about _20 qing, _ low-lying bread, the threshold voltage of the capture non-volatile memory unit. _^又39· A method for forming a non-swept memory barrier comprising the following steps: providing a complex 槪 &lt; forwarding a memory unit; 62 200845014 a plurality of double-sided charge 非 non-volatile memory The unit is arranged in columns and rows; the double-sided charge trapping non-volatile memory unit located in each row of the dead forms at least a face charge trapping non-volatile memory unit group; and the connection is configured to be double-sided charge trapping non-volatile The memory unit of the memory unit, each NAND series string has a top selection transistor and a bottom: connecting multiple scales of her scale, 峨 概 , , , , , — — — — _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Where the first pair of the line pair, and the second line of the bottom bit line pair, and: the second: the strip is more than - double-sided charge her type of forward memory unit: brother - money, and The second stop of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ = , ', , , , , ~ brother one, and the first adjacent row of δ Hai The part selects a source/secret of the transistor to connect to the scale-strip with the _bit rag; and, the connection-position is still controlled||head·her money' hides the _ 赖 式 非 non-volatile memory a unit for charge trapping of a double-sided charge trapping non-volatile memory unit for carrying a trapped charge. 40. The method of claim 39, further comprising the step of: providing a plurality of words a line connecting the word lines to the Weim surface charge trapping (4) in the transmissive recording unit; providing a plurality of top selection lines; connecting the top selection lines to the double-sided charge generalized hetero-cell unit At least one of the NAND series strings is selected from the top of the transistor - a closed pole. A plurality of bottom select lines are provided; '63 200845014 will be each bottom. a t-wire is connected to at least one of the =AND (four) strings of the double-sided charge-trapping non-volatile memory unit - the gate of the bottom selection transistor; and the -, the meta-wire is connected to the word line Selecting the line, and the bottom selection line, to turn the word line operation power s, for selecting the charged charge, the rule rule, and the erase, the captured charge represents each A re-primed bit in the charge trapping region of the selected surface charge trapping non-volatile memory cell. The method of claim 39, wherein the bit line controller comprises: a first plant bit threaded planning voltage source, the first piece of the bit line pair Selecting the source/drain of the transistor to the top portion, and providing a first source/no pole of the selected double-sided charge trapping non-volatile memory unit with a portion of X representing the plurality of digital data bits One of a plurality of threshold adjustment voltages, and the charge trapping region is set to a first level of the hot carrier charge representing the portion of the plurality of digit data bits; and / - the first bit threaded The planning voltage source 'provides a second source/drain of the selected double-sided charge trapping non-volatile memory unit with a second plurality of thresholds representing another portion of the plurality of data bits The voltage is adjusted and the charge trapping region is set to a second level of the hot carrier charge representative of the portion of the plurality of digital data bits. The method of claim 39, wherein the word line controller comprises: a character-threaded planning voltage source providing a very large programming voltage for generating a voltage field, Wherein the voltage field is between a control gate of the selected double-sided charge trapping non-volatile body unit and a channel region of the selected double-sided charge trapping non-volatile memory unit, and The channel region captures a hot carrier that will be injected into a charge trapping region of the selected double-sided charge trapping non-volatile memory cell. 43. The method of claim 39, wherein 64 200845014 the word line controller comprises: - a first-choice-reduced power view, a financially provided-character domain selection, the voltage is Moving to the top selection line to activate the double-sided charge-trapping non-volatile memory single τ 翻 翻 NAND (4) (4) lion's Cong transistor; and - the second selection wire-type planning electric source, which selectively provides a Moderately large selection of electricity 'This voltage is shifted to the bottom select line to activate the bottom select transistor of the selected NAND series string of the double-sided charge trapping non-volatile memory cell. 44. The method of claim 39, wherein the word line controller further comprises: ^ a word line reading electric^, which generates a plurality of ballast side voltages to finely select the double-sided electric charge Capturing a plurality of programming threshold voltages of the non-volatile memory cells, wherein the program planning threshold voltage is generated by a selected one of the plurality of threshold adjustment voltages representing the portion of the bits of the plurality of bits; The bit line controller further includes: a term takeout pole voltage generator that generates a _bungee voltage fresh, the brewing voltage level being selectively transferred to the fresh bar and the second bar of the miscellaneous pair 2 a first immersive/source and the second crypto/cell, depending on the charge level of the charge _ captured, to initiate the selected double-sided charge trapping non-volatile memory unit; The voltage is generated by generating a ground reference voltage, the ground reference voltage is audibly mixed to the first and second sum poles/sources via the bit_position and the second strip; and the sensing circuit 'The true line of the bit line is connected to the selected double-sided charge Formula catch nonvolatile memory 5 has a single body 70, to the first bit line pair by the helmet and two fine represents the charge number of the plurality of «__ feed-bit capture state planning program. 45* The method of claim 39, wherein the word line controller further comprises: a character line-age electric ship, and the shed is generated--the non-social erasing power 65 200845014 pressure, Wherein the electric lining is located in the double-sided charge trapping non-volatile recording channel region, and the hot carrier of the channel region of the double-sided charge trapping non-volatile recording control unit; and the 7-capture capture type The non-volatile recording of the bit and the line controller further comprises: a first Hiir generator </ RTI> for applying the ground reference voltage to the method described in claim 42 and wherein the method of claim 42 is wherein The double-sided charge trapping non-volatile memory unit is a one-channel memory unit 47. The method of claim 46, wherein the voltage level axis is caused by the very large program. _6〇v to about torn V This hot carrier injection injects the charge trapping layer into the thermal cavity. 48. The method of claim 46, wherein the voltage of the plurality of ship boundary fibers ranges from about +ι〇ν to about +1 and the second portion is a corpse, the interval being large enough to determine the plural The plurality of digit data bits = 49. The method described in claim 44, wherein = a number of critical _ voltages of the face are 'about +2 qing to Daru / knife to distinguish the plurality of programs Plan the incremental amount of threshold voltage. The method described in claim 49, wherein:::: is to serve the soft writing of the first and second electric units. The method of claim 45, wherein the very large erasing voltage level ranges from about 2 to about 2 To increment the threshold voltage of the double-sided charge trapping non-volatile memory cell. 52. The method of claim 42, wherein the double-sided charge trapping non-volatile memory unit is a -p_channel memory unit. 53. The method of claim 52, wherein the large program programming voltage level ranges from about +6 nas to about + diced V to implant the cooked carrier into the thermoelectric hole to inject the charge trapping layer. 54. The method of claim 52, wherein the electric pressure of the second part of the g-pressure is divided from a large foot to about 6 and is divided into "m" to determine the plural. The plurality of digits: the method of claim 44, wherein the voltage of the critical gamma is difficult to change from German to about, and is divided into zone cutters. The amount of increase in the threshold voltage. 56. The method of claim 55, wherein = and the age of the electric potential must be a margin, and the money is greater than that of the female, and is insufficient to cause the double-sided charge trapping non-volatile ^ The method of claim 52, wherein the very large erasing voltage level ranges from about _ls 〇v to about the surface charge capture memory. -20.0V to lower the double 67 57.