TW200839503A - Nonvolatile memory with modulated error correction coding - Google Patents

Abstract

Data is stored in a nonvolatile memory so that different pages of data stored in the same memory cells are encoded according to different encoding schemes. A first page is decoded according to its encoding scheme and an output is provided based on the decoding of the first page that is subsequently used in decoding a second page.

Description

200839503 IX. Description of invention: [Technical field to which the invention belongs]

This invention relates to non-volatile memory systems and to methods of operating non-volatile memory systems. X [Prior Art] • Non-volatile § Remembrance systems are used in a variety of applications. Some non-volatile ticks are embedded in a larger system, such as a personal computer. Other non-volatile memory systems are removably connected to a host system and can be interchanged between different [: host systems. Examples of such removable memory systems include memory cards and USB flash drives. Electronic circuit cards including non-volatile memory cards have been implemented commercially in accordance with a number of well-known standards. The memory card is used with personal computers, mobile phones, personal digital assistants (PDAs), digital still cameras, digital cameras, portable audio players and other host electronic devices to store large amounts of data. Such cards typically include a reprogrammable non-volatile semiconductor memory cell array and a controller that controls and supports the operation of the memory cell array and interfaces with a host to which the card is connected. Several cards of the same type can be interchanged in a host card slot designed to accept this type of card. However, the development of many electronic card standards has produced different types of cards that are incompatible with each other to varying degrees. Cards manufactured according to the standard are not normally used with mainframes designed to operate on another standard card. Memory card standards include PC Card, C〇mpactFlashTM Card (CFTM+), SmartMediaTM Card, MultiMediaCard (MMCTM), Secure Digital (SD) Card, miniSDTM Card, User Identification Module (sim),

Memory StickTM, Memory Stick Duo Card, and micr〇SD/TransFlashTM 126159.doc 200839503 Brother Remembrance Module Standard. A number of USB flash drives with the trademark "Cruzer®" from SanDisk are commercially available. USB flash drives are usually larger and different in shape from the memory cards described above. Stored in a non-volatile form when reading data. Data in the memory system may contain error bits. Traditional methods of reconstructing corrupted data include applying an error correction code (ECC). When writing data to a memory system, a simple error board is coded by storing additional parity bits. Meta-encoded data, the equi-bit bit sets the parity of the bit group to a desired logical value. If the data is incorrect during storage, the parity of the bit group may change. Read from the memory system After the data, the homonym of the bit group is again counted by the ECC. Because the poor material is damaged, the calculated parity may not match the required co-location conditions, and the ECC can detect the damage. The ECC can have at least two functions. • Debug and error correction. The capabilities of each of these functions are typically measured in terms of the number of bits that can be detected as erroneous and subsequently corrected. The detection capability can be compared to the correction capability. Same or greater than it. A typical ECC can detect the number of error bits higher than the number of error bits it can correct. Sometimes a data bit and a set of parity bits are called a word. An early example system (7 , 4) Hamming code, which can detect up to two errors per word (7 bits in this example) and can correct an error in the seven-bit word. More complex ECC can correct each word More than one single error, but the reconstruction of the data becomes more complicated in computation. The convention is to recover the data with a probability of accepting a small error recovery. However, as the number of errors increases, the probability of reliable data recovery is also rapidly decreasing. Or the additional hardware and / or performance phase 126159.doc 200839503 associated costs become extremely high. In the semiconductor memory φ - one, including the EEPROM system, the data can not be the threshold voltage of the transistor. __,, Corresponding to different electric castle ranges. If the value of the different digital data storage values deviates from its preferred range, an error will occur in the case of the electric power. The error is ECC and can be corrected in some cases.SUMMARY OF THE INVENTION A method for storing data in a non-volatile semiconductor memory material includes: encoding a data according to a _ _ coding scheme (4) obtaining a plurality of encoded data bits; the first plurality : the coded negative bit is stored in the plurality of cells of the array of U baskets, each of the cells comprising a plurality of encoded data bits to > one, and Storing a second plurality of data bits in a plurality of units having the two encoded data bits, the plurality of single π comprising at least one of the second plurality of data bits, not according to the plurality of data bits The first encoding scheme encodes. - Decoding stored in a non-volatile body material inventory - The exemplary method includes: reading each of the plurality of cells stored in the plurality of cells including at least one first data bit a second level bit of the plaque; using the read result to generate a plurality of first: correction data values corresponding to the plurality of second::, the plurality of first correction data values are caused by the plurality of first ECC correction of data bits The generation of the reading result is followed by using the reading result and also using the plurality of first correction materials = generating a plurality of double 1st stipulation data corresponding to the plurality of second data bits 126159.doc 200839503 value. An exemplary non-volatile semiconductor memory system includes: a memory array comprising a plurality of memory cells, each of which individually holds a first first data bit and a second page - a second data bit And an ECC encoder that encodes the data of the (four)-page according to a first code = scheme before the storage of the plurality of cells, and encodes the data according to the first coding scheme after the storage of the plurality of cells Two pages of information. Another exemplary non-volatile semiconductor memory system includes: a flash memory array that stores data in a plurality of cells, and a cell storage device-division-data page at least one first data bit and _ And a second data bit; and an ECC decoding system that first decodes the first data page and then decodes the second data page using the decoding result of the first data page. [Embodiment] In many non-volatile memories, reading data from a memory array may be wrong. That is, individual bits that are stylized into the input data of a memory array may be read later at a different logical value. Figure 丨 shows a relationship between the physical parameter (threshold voltage Vt) indicating the state of the memory cell and the logic value of the stylized b system of the memory cell. In this example, only two states are stored in the cell. Thus, the unit stores a data bit. A unit that is programmed to a logic 0 state typically has a threshold voltage that is higher than the unit in a logic 1 (unprogrammed) state. In an alternative, the logic 1 state is the unprogrammed state of the memory cells. The vertical axis indication of Figure 1 reads a unit at any particular threshold voltage based on the desired threshold voltage distribution. 126159.doc 200839503 2 Probability. A first probability function is displayed for the unit of stylized to logical 并 and a second probability function is displayed for units that are morphed to logic 0. However, these functions have some degree of overlap between them. Used in reading such a single 70 - distinguishing voltage Vd. A single having a threshold voltage lower than VD is considered to be in state i, and those having a threshold voltage higher than VD are considered to be in state °. As shown in Figure 1, this may not always be correct, because the overlap between functions 'existing - non-zero probability, ie stylized to a logical 1 state - the memory cell will be read as having a greater than VD bound The voltage 'will read as being in the - logic 0 state. Similarly, there is a non-zero probability, i.e., a stylized to a ^^^ t0-like memory unit that takes the line item as having a logic 1 state. Internal == occurs due to material reasons, including the interference caused by the memory array. The overlap may also occur due to the fact that the normal temperature is not maintained in the first half of the tight threshold voltage II M A 1 . Specialized sizing technology allows the threshold voltage to be quasi-predicted. However, such stylization can take a few (with a smaller standard in - one _: ^^) and S, you need to do it in a memory unit ^ Efficient i Shi tiantian - Putian # Tian Xidi stores the bits. The effective boundary voltage range is used to effectively overlap the sheep fields. The function of the 岫 岫 可 can be non-volatile § 丨 丨 丨 丨 系统 系统 普遍 普遍 普遍 普遍 普遍 记忆 记忆The occurrence of / in the case of reading from a coding system is to be stored in the -memory based on the '^ input data calculated some 126159.doc 200839503 some additional ECC bits. Other ECC schemes can use _ more complicated way to input data Mapped to the output data. These ECC bits are stored together with the input data but can be stored separately. The input data is read from the non-volatile memory together with the ECC bit and a decoder uses the data and the coffee at the same time.

Bits to check for any errors. In some cases, such EM bits can also be used to identify - error bits. The error bit is then corrected by changing its state (from "0" to "i" or from T to "〇"). Attaching the gamma to the data bit is not used to store the data in The only way to encode data in a non-volatile memory. For example, data bits can be encoded according to the scheme. The scheme provides the following transformations: ❹ to "", old to 1100, 10 to 0011, and ^ To (9)(10) Figure 2 shows an example of input data stored in a memory system. The input data is first received by the -ECC unit 2〇1, which includes an encoder 203. The input data can be The host data stored in the memory system details may be data generated by a memory controller. The example of Figure 2 shows four input data bit reads. Then, the encoder 2〇3 uses the -coding scheme from The input data bits calculate the Ecc bit (1) (1). An example of an encoding scheme is to generate ECC bits for the same bit of the selected data bit group. Then 'the input data bits and the Either ECC bits are transmitted to one The modulation/demodulation unit 205 includes a modulator 2〇7. The modulator 2〇7 converts the digital data transmitted by the ECC unit 201 into a memory array 2〇9 Form. In the scheme, the digital data is converted into a plurality of threshold voltage values in a plurality of memory cells. Thus, for 126159.doc -10- 200839503, the digital data is converted into a memory cell. The various circuits of the voltage can be considered to form a modulator. In the example of Figure 2, each of the syllabic units can hold a data bit. Thus, each memory cell can have one of the two ranges. The threshold voltage, a range represents a logical, 丄, state and another range represents a logical "〇 state, as shown in Figure 。. A memory cell storing a logic "1" state has a threshold voltage that is less than a threshold voltage of vD (<vD) and stores a logic "〇" state having a threshold voltage greater than VD (>VD). The program can be programmed and verified to a nominal threshold voltage above Vd to at least initially ensure that there is a preferred interval between the cells programmed to the two logic states. The data can be stored in memory array 209 for a certain time. Period. During this time period, various events may occur, causing a change in the threshold voltage of the memory cell. In particular, operations involving stylization and reading may require voltage to be applied to the word in one of the other previously stylized units. Lines and bit lines. Such interference is especially prevalent when the size of the device is reduced such that the interaction between adjacent units is more pronounced. Charges may also be lost over a longer period of time. It can cause the data to change during reading. Due to such changes, it is possible to read the data bits and have a different state from the originally programmed data bits. An input data bit 211 is read to have a threshold less than vD (<VD), and initially has a threshold greater than VD (>VD) when written. Memory cell threshold The voltage is converted into data bits by one of the demodulation transformers 213 in the modulation/demodulation conversion unit 205. This is the reverse procedure of the program executed by the modulator. The demodulation transformer 213 can include a sense The amp, 126159.doc -11 - 200839503 reads a voltage or current from one of the memory cells in the memory array 209 and derives the state of the cell from the read. In the example of Figure 2, one has a smaller The memory cell of the threshold voltage of VD (<VD) provides a demodulated output and a memory cell having a threshold voltage greater than VD (>VD) provides a demodulated output "〇". The output sequence 11 11111 is shown. The second bit 208 of the sequence is erroneous due to being stored in the memory array 2 〇 9. The output of the demodulator 213 is transmitted to one of the Ecc units 2 〇 1 215. The decoder 215 determines whether there is any error by the data bit and the ECC bit. A small amount of error within the corrective ability of the code corrects the error. If there are a large number of errors, it can be identified but not corrected if it is within the detection capability of the code. If the number of errors exceeds the code If the power is detected, the error cannot be detected, or an error correction may be caused. In the example of Figure 2, the error in the second bit of the word is detected and corrected. This is provided by the decoder 215. Output (1〇〇1), which is identical to the input sequence. The decoding of the memory system 200 is considered hard input hard output decoding because the decoder 215 only receives data bits representing the input data bits and the Ecc bits. And decoder 215 outputs a sequence of -corrected data bits corresponding to the input data bits (or an output cannot be provided if the number of errors is too high). Figures 3 and 4 show an alternative memory system for the memory system. Figure 3 shows a function similar to that of Figure 1, where ν^〇 and a threshold voltage below VD represents a logical 〇 and a voltage above 5% represents a logic. Instead of displaying a single voltage threshold voltage, the system is divided into two different ranges, where the threshold voltages are indicated by the actual number of voltages. The function corresponding to logic 1 is centered above 0 volts, and the function corresponding to logic "〇, is 126159.doc -12-200839503 centered below οV. Figure 4 shows a data system similar to the memory system 42 1, the data storage program is similar to: = - and the memory system 2 〇. y , t store programs (using the same input data bits) and have - different readers. Specific; =; = whether the threshold voltage is higher or lower than the - specific value, the system 421 reads the threshold voltage, as shown in R Figure 3. Will understand that you don't have to read ί,

=Community L other unit operating components to store and retrieve _ shell material (eg current sensing). Voltage sensing is only used as an example. Generally, the voltage of the boundary voltage - the transistor is turned on as a idle voltage. Figure 4 shows that an item takes place, which is more informative than the previous example. This can be seen as a read of the graph with a resolution (and a resolution that exceeds the resolution for the stylized state). As in the previous example, the error occurred in the reading. Here, the reading corresponding to the second bit and the third bit is erroneous. The second and third dimension logic "〇" is stored by a stylized unit with a threshold voltage less than -VD, but the cells are read to have a threshold voltage of 0.05 volts and 〇·1〇V, which is higher than Vd (Vd=(^). The original voltage system read from the memory array 423 of FIG. 4 by a series of read operations is transferred to a modulation/demodulation unit. One of 427 demodulators 425. The original voltages have a finite resolution as indicated by the resolution of the analog to digital conversion. Here, the original data is converted into probability data. The unit reading is converted to a probability that the corresponding bit system is one or zero. The series of readings from the memory array (0.75, 0.05, 0·10, 0·15' 1·25, 1·0, 3〇, and 〇·5) Volts can not only indicate the status of the unit 126159.doc -13 · 200839503 ' but can also be used to provide a certain degree of certainty about the state. This can be expressed as a probability of staging a memory unit using a particular bit. Thus' Readings close to 〇Vat provide low probability values, and the farther away from crouching The selling number of the mouth and the value of the probability of the supply. The probability value shown is the logarithmic probability ratio (explained below). This provides a negative number for a unit in a logical state and a unit for a state in a logic 1 state. A positive number, the digital value indicates the probability of correctly identifying the state. The second probability value and the third probability value (01, 0·2) indicate a logic "1". The second value and the third value indicate a relatively low probability. It is transmitted to one of the decoders 429 in an ECC unit 431 (in some cases, obtaining a probability value from the original value can be considered to be performed within the decoder). The ECC unit 431 also includes an encoder 432. The decoder 429 pairs the probability The value performs the decoding operation. This decoder can be regarded as a soft input decoder. In general, soft input refers to a round, iΜ ________

For better performance and some hard output to the other unit. SISQ decoder generally provides a harder loss than hard input.

The use of a SISO decoder can implement the addition amount (the number of ECC bits. Error correction capability. For effective proper encoding/decoding scheme, 126159.doc •14-200839503 and the demodulation system is adapted for efficiency. Obtaining a soft input without undue complexity and without undue time for reading data from the memory array. In one embodiment, one of the soft inputs for a SIS0 decoder is used by using a resolution Reading the data in a non-volatile memory array provides a resolution that is greater than the state used to program the memory. The memory unit can be programmed to Two criticalities [range t I to write data and then read by parsing three or more threshold voltage ranges. In general, the number of threshold voltage ranges for reading will be used for stylization. Several times the number of threshold voltage ranges (4), for example, up to two times). However, this is not always the case. An ECC unit can be formed as a dedicated circuit or this function can be performed by a moving body in a controller. In general, a controller is a specific application integrated circuit (ASIC) that has a design for a specific function (for example, a circuit and also has a body to manage the controller operation. Thus an 'encoder/decoder can borrow Formed by a combination of hardware and objects in the memory controller. Alternatively, an encoder/decoder (ECC unit) can be located on the memory chip. = (4) / ^ 4 may be on the memory chip, On a control wafer on a separate wafer or a combination. In general, a modulated sea modulation unit will include at least some components of the memory chip (eg, a peripheral circuit to a memory array) Although Figure 4 indicates the threshold voltage: read to a high resolution (- analog reading), the selected resolution range = month. 4 depends on the right stem factor 'including the non-volatile memory used Figure 5 shows a more detailed view of 31 (especially the decoder ❺). 126159.doc 200839503 The decoder 429 includes a lion decoder function and a soft-to-soft converter 534. The original probability data is accepted and Performing a coffee calculation on the original probability data to The probability data is calculated. The calculation_data can be regarded as a soft output. In many cases, 'the soft output is then provided as an input to the coffee decoder, so that the second decoding repeat process is performed. - SISO decoding n executable Continuously repeating the process, the direct frequency is at least a predetermined condition. For example, the predetermined condition may be that all the bits have a probability of being greater than a certain minimum value. A predetermined condition may also be one of the probability values (for example, an average probability) Value) - The predetermined condition may be a convergence from the result of repeating the next repeated process (ie, maintaining the repeated process until there is almost no improvement from the additional repeated process). - The predetermined condition may be the number of times the preview is completed. A combination of these conditions can also be used. The decoding is performed using a 'coding pattern' in the data, which is the result of encoding on the data by the encoder 432 before storing the data. Encoder 432 and decoder 429 Both are considered part of the ECC unit 431. Efficient decoding depends on having an appropriate encoding/decoding scheme. Various schemes are known for The data is encoded in a manner that is subsequently decoded by a -SIS0 decoder (eg, still decoding 532). The encoding/decoding scheme includes, but is not limited to, turbo code, product code, BCH code, Li De. Solomon coded (5) · Solomon Eodes), convolutional codes (see US Patent Application Nos. ιι/383, 4〇ι and 1 1/383, 405), Hamming codes and low-density parity check (1^^) codes. LDPC codes and turbo codes and A detailed description of how it can be used with SIS〇 decoding is available on September 28, 2006, titled “Soft Input Soft Output Decoder for Non-Volatile Memory” and "Non-Volatile Cases 126159.doc -16 - 200839503 Soft input soft output decoding method 丨, cover ^ ^ ^ ^ ® ^ t tf t ^ 1 1/536, 286 and ll / 536, 327. In some cases, statistics may be collected regarding corrections implemented by the _ECC decoder. Such statistics can be used to adjust the operational parameters of a memory array. Non-volatile memory systems with adjusted operating parameters and methods for adjusting such parameters are described in U.S. Patent Application Serial No. PCT/536,347, filed on Sep. 28, 2006. In some memory arrays, 'single memory cells maintain more than one data bit. Such multi-level cell (MLC) memory maps data bits to a memory state. For example, in a flash memory, more than two data bits can be mapped to a memory state, each state having an assigned threshold voltage range. Figure 6 shows an example of three data bits stored in a memory unit. These three data bits require eight (23) different memory states. Generally, s, the data is stylized into a MLC unit in units of pages, where the elements in one unit come from a different page. Thus, in Figure 6, the lowest bit 636 (least significant bit or LSB) is in one page, the middle bit 638 is in another page and the highest bit 64 〇 (most significant bit or msb) is in another In the page. The mapping of bits to memory states can be based on any convenient scheme. Figure 7A shows an example of mapping the threshold voltage of a memory cell to sixteen different memory states S0 through S15 to store four data bits. Unlike the example of Figure 6, the bit map here is mapped to the memory state such that the LSB differs for neighboring states. Other bits are also different between adjacent states. In an example, the LSB is first decoded and used to decode higher bits. Since 126159.doc -17- 200839503 - the LSB of a particular memory state is different from its neighbors, it is decided that the coffee helps to resolve between adjacent states. Figure 7B shows the difference between the (10) 〇) and % (brain) voltages of the adjacent memory state - the extra read voltage Vl"6 is used to provide the memory state S5#S6 (4) additional resolution. Four different threshold voltage readings of four of the four readings of the voltage can be used to provide a soft input for soft input decoding. Adjacent states 35 and 86 are in both least significant bits. Different. In the case where the unit is read as having a characteristic boundary voltage, this indicates four bits. However, if there is an error in the read voltage, the read voltage corresponds to the other state, then one is dead. Bits (four in this example) may be erroneous and may require positive. In some cases, 'the pages are separately subject to correction, and each error bit requires separation correction so that - single-misread status It may be required to separately correct the four errors. In the alternative method of correcting stored data, the one-bit correction may provide information for subsequent corrections for other bits stored in the same unit. For example, a single reading may be performed. Take a critical electric Reading B, which indicates the memory state S5 (1G1G), so that the LSB (the first bit) will be the next one. When the Ecc correction is performed on the LSB (for example, on the page containing the B dip) In the case of 杈, the ECC correction can indicate that the LEB is 1. Given B is close to Vreadn and 4 LSB is 1, the stylized state is likely to be S6 (1〇〇1). This is 4 _bits possible Therefore, instead of i, the result of the ECC fork performed on this indicates a possible value of one of the second bits. Based on the threshold voltage of the unit, the second bit is erroneously determined to be 1. However, 126159.doc •18-200839503, the ECC corrected LSB indicates that the second bit 彳艮 may be 〇. Additional information about the second bit is provided to determine the one of the μ 罘 one ECC decoder. This additional information may allow decoding of data containing erroneous numbers or may allow decoding with a smaller number of bits TL. Similarly, the result of decoding the second bit may be used. To solve higher bits. ~ and r In the -example, where the - unit contains more than one data bit, first Decoding - the first bit (and other encoding bits in other units) and using the result of this decoding to provide an indication for at least one subsequent bit. In a scheme ι use - high shirt level to correct _ - Bit: This correction result is used to determine the extra bits in the unit. Different redundant levels can be used to encode the data in different pages so that even if it contains a large number of errors, it can be up to the stomach. A first page is corrected, and the results can be used to correct additional pages stored in the same unit. These additional pages do not necessarily require the same redundancy level because the correction of the first-data page provides bits for additional pages. Additional information. Figure 7: At /, / ϋ scheme is not 7L to memory "suitable mapping so that decoding the LSB to provide information for decoding higher bits. Fig. 8A shows a memory state SO to S1 5 mapped to 1I7A> of one of the four bits 842, 844, 846 and 848 of the -memory unit. These four bit cutters are from 842, 844, 846 and 848 of four W-like pages (pages to 3). The tongue unit can be read by determining its threshold voltage using _ 疋 resolution. For example, the ^, '11 boundary voltage can be within the threshold voltage range indicating that the memory state is S7. In some cases, certain probability information 126159.doc -19- 200839503 also obtains some probability information during the reading as described above. The information read from the pages of the unit and other units is transmitted to a decoder (e.g., a SISO decoder), and a first Ecc operation in # generates a corrected data bit corresponding to the units. For example, the LSB 842y can be determined, so state S7 is incorrect. This information can be used to decode higher bits 84 and 848. Since the LSB is 1, it is possible to eliminate all the considerations of having a lsb 8 core from the determination of the third bit, as shown in the figure. This means that the remaining eight states (S0, S2, S4, S6, S8, si〇, S12, S14) can be considered to have a larger valley than the initial sixteen states 8〇 to 5 (extensible mapping) The threshold voltage range to the remaining state is in the range of the sorrow of the elimination. The threshold voltage of the cell can be compared to the extended L-bound voltage range of the remaining state. This provides a higher chance of getting the right result due to the increased tolerance. Thus, the threshold voltage reading of the previously indicated state can now indicate state 88 because S7 is eliminated. A second ecc operation produces a corrected data bit for bit 70 of page 1. The second ECC operation is subject to the page The result of the first ECC operation on the bit of 0 is such that it may not require the same high redundancy level. In the example of the figure, the bit 844 of the page i stored in the cell is determined by Ecc decoding. 1. This is used to determine the next bit 846. Figure 8C shows the remaining states (SO, S4, S8, S12) when the two least significant bits are considered to be up. The state is eliminated, so the tolerance is increased for the remaining state. For example, a threshold voltage reading corresponding to 87 will indicate S8, assuming that S5 to S7 are eliminated at this point. Thus, the solution 126159.doc -20- 200839503 is least effective. The results of bits 842 and 844 provide information to assist in obtaining the next 846. Bits 846 based on the increased tolerance are used to obtain the decoding and display the remaining state (9) when determining the bit of page 2 for the page 2 ―). It can be seen that the remaining state (S0 to S8) has a broad Tolerance, which allows the MSB to be determined by probability. Then, decode this - the result of the decision is corrected for the MSB 848. For example, at the threshold voltage

Where not US7, given the remaining state, 88 is the most likely state and 848 is most likely to be 〇. The above example can be implemented using soft input or hard input for the first ECC decoding operation. Subsequent brain operations receive soft input because the data received from reading the memory unit is taken into account in the ECC decoding. . Decoded data both. In one example, a memory unit is read using resolution, which resolves the stylized memory state and is also parsed within the stylized memory states to provide a single copy relative to the memory. The probability value of the bit in the middle. In this example, the probability value corresponding to the higher bit can be adjusted based on the result of decoding the lower bit. This provides another way to use the result of a first ECC decoding operation in a second ECC decoding operation. Adjusting the tolerance for the remaining state or adjusting the probability for the remaining bits is a different technique for incorporating the decision to decode a lower bit of information into a higher bit. Figure 9A shows an example of a portion of a soft input memory system 950 that uses ECC correction of a first page to provide ECC correction for a subsequent page. A memory array 952 includes eight memory cells C0 to c?, each of which records 126159.doc -21 - 200839503. The body unit stores four Shenyibei material levels, one element from four pages 1> to p3 The data stored in pages P0 to P3 are encoded before storage. In particular, the shellfish in P0 is encoded so that it can be decoded separately. • The decoder 954 is coupled to the memory array and the demodulation output is provided as an input 955 to the ECC decoder 956. The demodulation 2 956 may include a suitable read circuit to use at least a sufficient resolution to determine the threshold voltage of the 体fe body early to identify a stylized memory shape. The output of the demodulation transformer 954 is provided for a first ECC decoding module ECC0. The output of the demodulator 954 can be an indicator of a bit (hard input), a probability value (soft input), a threshold voltage, or other state of the memory cell. ECC0 decodes the data stored in page p(). This can be hard input or hard output decoding or siso decoding. In general, $, SIS〇 decoding provides better result modulo, and £CC 〇^ is entitled to positive data p〇, which can be a set of probability values or “correction bits associated with the bits stored in page P0” The correction data is used to provide a decoded output from the first output of the Ecc decoder 956, ie, from page P. It can be performed by performing a soft-to-hard conversion (if P0, the output is fortunately And also stripping any redundant data bits added as part of the encoded data before storing the data in the memory array 952 to generate the output 0/P〇〇" the right data P0' is provided as a One of the two ECC modules ECC1 inputs 'decodes the data stored in page P1. The module ECC1 receives the correction data p〇 generated by ECC0 and also receives an input 958 from the demodulation transformer 954. The input 958 of the demodulation transformer 954 can be a set of probability values or based on reading the bit of the memory array 952. The correction p〇, the data and the combination of 126159.doc * 22 - 200839503 It is considered to form a soft input to the module eccr. For example, provide suggestions in E(10)^ The bit is hard for !, but the input from the demodulation transformer 954 suggests that the bit is a 〇 'this can be combined to provide a low probability of (10). In the curry and from the demodulation Both inputs 958 of 954 are suggested as i, and these may be combined to a high probability of H. Where probability values are provided, the basins may be combined in a suitable manner (e.g., by an average probability value). Module

ECC1 performs decoding based on the combination of the input from the ECCG and the input 958 from the demodulation heart to provide corrections (4). The correction data P1' can be used to provide an output 〇/P1 (decoded data from the heart) which removes one of the redundant data bits. The calibration data is also provided to another ECC module (ECC2). The ECC module ECC2 receives P1 and also receives input 960' from the demodulation transformer 954 and performs Ecc decoding on the combination of such inputs to provide correction data P2 as previously described. The correction data p2 can be used to provide an output 〇/p2 (decoded data from page P2) which removes one of the redundant data bits for hard output. Next, the correction data P2 is passed to the ECC module ECC3, where it is combined with the input 962 from the demodulation transformer 954 to determine the correction data P3'' which corresponds to the material stored in the page P3. The correction data ^ can be used to provide output Ο / P 解码 decoding data from page P3), which is to remove one of the redundant data bits of the hard data. The ECC modules ECC1 to ECC3 may be of any suitable type and may use a similar coding scheme or a different coding scheme. ECC 1 can accept a hard input or a soft input and can implement decoding using hard input hard output decoding, SIS decoding or other techniques 126159.doc -23- 200839503. The ECC modules ECC1 to ECC3 each receive two inputs, and each of the two inputs can be a soft input or a hard input. Even if both inputs are hard inputs, they can still be considered as providing a soft input in combination. In other examples, pages can be encoded and decoded together. For example, a first page and a second page can be decoded together. Subsequently, a third page and a fourth page can be read and the results of decoding the first and second pages can be used to decode the third and fourth pages.

U Figure 9B shows a first example of an eCC module 964 that can be used with one of the ECC modules ECCuECC3. Two inputs 960, 968 are provided to the ECC module 964. One input 968 is provided by a demodulator to reflect data read from a memory array and another input 9M provided by a previous ECC module. Decode another data stored in the same memory unit. The two inputs 966, 968 are provided to a combination circuit 97A which produces a single output 972 based on the two inputs 966, 968. For example, an increased tolerance can be provided by a previous ecc group and a threshold voltage can be provided by a demodulation transformer. These are combined in the combining circuit 97G to provide a soft output. Where the second demodulator provides a probability value, the probability values from the demodulation transformer 先前 previous ECC module may be combined to provide a combined value, i.e., the probability values: average. The group can be hard-computed by assigning a high probability that the two hard inputs are the same and assigning a low probability at the difference between the two hard inputs. Circuitry 97G may use a look-up table or other suitable component to provide an output that depends on the two inputs. Next, the soft output 972 generated by the combining circuit is sent to the _SIS 〇 decoder 974, which performs - or multiple iterations to determine the output probability value (or output bit if executed soft :: 126159.doc • 24-200839503 Conversion). Figure 9C shows an alternative ECC module 976 having a combination circuit 978 that combines input 978 from one of the demodulators with input 98 from one of the other ECC modules to provide a soft output, As mentioned earlier. In this U condition, the soft output 982 is then converted to a hard output 984 by a soft to hard converter 986 (the largest possible bit is provided as the output). The hard output 984 is then provided to a hard input hard output (hih) decoder that decodes the data to provide correction data. Alternatively, it is possible to perform a combination and soft to more conversions, such as using a lookup table that provides one of the hard output values for different input values (hard or soft). The decoder module ECC0 only receives the input (5) (from which the demodulator can be - soft or - hard input and the decoder ECc can produce a soft or a hard output. For example 'can be similar to Figure 5 The decoder 429 to form the module ECC〇ECC〇 to ECC3 can be as shown in FIG. 9B or FIG. 9C. The ECC modules ECC0 to ECC1 can be formed as separate circuits or can be formed into n-circuits, which are configured To perform continuous ECC operations. In the example, the ECC modules are formed as part of the controller ASIC. As described above, separate decoding steps can be used to decode different pages. The result of decoding a first page is provided. Help decoding - second page. The result of decoding the second page can be provided to help decode a third page, etc. Separately encoding the pages for separate decoding of the page. By decoding the page provided The extra information 'allows the use of less redundant pure green lines (four) two pages of decoding. According to an example 'providing a different number of Ecc bits for different pages. The page can provide a large number of redundant bits to allow A The wrong amount of school 126159.doc -25- 200839503 positive. Because because of The wider margin (or higher probability) associated with the first page due to the first page results in a smaller amount of redundant bits for the second page. The different coding schemes are used for different pages. In general, the addressable unit for a memory car display system is a segment. In one example, a segment is stored in a portable device. More than one page in an MLC memory. Different numbers of ECC schemes can be used for different pages of the same segment. The different bits of the redundant bits / Figure 1〇 are stored in the cell so that the individual cells contain - - eight segments of the four bits of the segment (bit 0 to bit 3) (segment 〇 to 7). The segment 〇 to 7 is stylized as corresponding to the bit 〇 to 3 Page. In the case where the bit system is assigned to the memory state as shown in the figure, it is expected that the page will be read as having a large number of errors, page # has fewer errors than page 0, and page 2 has fewer errors than page number. 'And page 3 has fewer errors than page 2. This is because the larger the tolerance for the higher the page (or the probability ρ this means the more Low pages may require a lot of error corrections, especially pages. You can choose which encoding side to use = including the amount of redundant data. The term "page" is used to mean - stylized in the memory array Units. An MLC scheme can be used to store multiple pages in the same unit. In the specific example presented here, all pages that are stored in a unit group are read together and do not execute one page. Individual reads. Thus, the minimum unit of read for this system can consist of multiple pages. It will be understood that the term "page, means that together the stylized cross-cell group 2 is in the same validity - the bit Groups, rather than groups of bits that are read together as a unit in a particular ticker system. _ Figure 11A shows an example of a section 1190 extending across four pages (pages to 3) and including one of two different codes 126159.doc -26-200839503. The data in pages 0 and 5 is encoded using an LDPC, flat code scheme, which produces redundant data bits of 1%. This material can be decoded using SISO decoding, which allows for a large number of erroneous corrections. The data in pages 2 and 3 are not encoded using an LDpc code. However, the shells of pages 2 through 3 are encoded using a BCH code which provides redundant data bits 1194. BCH encoding can also be used to encode pages to i, or BCH encoding can be limited to pages 2 through 3. In the case where the BCH code is overlaid, the data of page 〇 to 4 is first encoded according to the BCH code, and then the page 〇 to 丨 is further coded according to the LDpc code. Later, LDPC is first used to decode the data in page 〇 to 1, and then BCH is used to decode page 〇 to 4. FIG. 11B shows another example of encoding a page 丨195 by only one LDpc code, so only the page 〇 contains redundancy ^1) (:: generation bit 1196. Higher pages 1 to 3 are used A BCH code is encoded, which uses bch to generate redundant bits 1198. The BCH code can be extended to cover pages other than pages 1 through 3, or can only cover pages 1 through 3. Thus, not for other pages. A coding scheme is used to encode the page. Figure 11C shows another example of a different coding scheme for each page 〇 to one of the segments 1199. According to a first coding scheme, redundant data ECca is generated for the page ,, according to a The two encoding scheme generates redundant data ecCb for page i, generates redundant data ECCc for page 2 according to a second encoding scheme, and generates redundant data ECCd for page 3 according to a fourth encoding scheme. The page is smaller than other pages/, Even more than a few times ECCa, page 0 is first decoded and used to provide information to decode other pages. The coding scheme for different pages can be the same class 31 (such as all LDPC schemes) or different types (example and side 126159.doc -27- 200839503 Case ^The same type of scheme is in The number of different redundant data can be used in two ways: see different schemes. In some cases, the coding scheme of the high page also covers the lower pages. Therefore, the ECCB can cover the pages and work to make these pages According to the second coding scheme, decoding is performed. Eccc^ covers the page (1) such that the pages are decoded together according to the third coding scheme, etc. Such pages must also be encoded together. Although the examples of FIGS. 11A to 11c Displaying redundant data and other data can be mapped to encoded data in a more complicated manner as described above. The number of extra bits used to encode the data can be compared with the uncoded data. It is considered as the number of redundant bits, even in the absence of detachably identified redundant bits. Header information 1101 is displayed on page 3 of the above example. However, header information may also be provided at other locations. Figure 12 shows an exemplary feature 5 of a memory system using different encoding schemes for different pages, the memory system displaying an encoder 1205' which applies LDPC encoding to certain data and applies BCH encoding to other data. (In other examples, 8 (::11 encoding applies to all data and LDPC encoding applies only to certain data). The encoded data is then passed to a modulator 1207, which stores the data in a memory. In the array 12〇8, in particular, the modulator 1207 stores the LDPC encoded data in a first page and stores the BCH encoded data in a higher page in the same memory unit. A suitable scheme (e.g., the scheme of Figure 7A) maps the data bits to the memory state such that a first bit (one bit in the first page) is replaced from a memory state to a next memory state. The data is read from the memory array by a demodulator 12〇9 and is provided to 126159.doc -28-200839503 for a decoder 1211, which implements LDpc decoding on the data from the page and comes from BCH decoding is implemented on the data of other pages. An output 1213 from LDpc decoder 1215 is provided to the bch decoder m 7 such that the BCH decoder 1217 can use the correction by the LDpc decoder i2i5 = to assist in performing BCH decoding. There may also be some output of the BCH decoding operation after one of the -BCH decoding operations. In some cases, the output from a BCH decoder is also fed back to the r LDPC decoder for LDPC decoding. For example, LDPC decoding may be & overlay decoding, which performs a number of iterative processes and then provides an output to the BCH decoder. If the BCH decoder is unable to correct the provided data, it can return a -signal to the LDPC decoder to indicate that more repetitive processes should be performed. 13 shows a memory system 1319 including an encoder 1321 which encodes the first bedding in a first encoder 1323 and a second encoder according to the second encoding scheme. The first and second data in 1325 are programmed by the modulator 1329 to share the cells in the memory array 1327. The data system is read from the memory array 1327 by the demodulation transformer 1331 and decoded by the decoder η". According to the first scheme, the decoding is performed in the first decoder i 3 3 5 corresponding to the first data. Reading the data, and decoding the read data corresponding to the second data in a second decoder according to the second scheme. The output 1339 from the first decoder 1335 is provided to the second decoder 1337 so that the result of decoding the first data can be used to decode the second material. Similarly, the output 1341 from the second decoder Ur is provided to the first decoder 1335 so that the result of decoding the second 126159.doc -29-200839503 can be used to decode the first data. Thus, the first decoder 1335 fish-decode IIU37 interacts with a total of (10) code data. The first-transmission: case: the coffee-making scheme, which has different redundancy in the -example: capital. In another example, the stomach first coding scheme is an LDPC scheme and the second coding scheme is a BCH scheme. f describes various examples with reference to flash memory. However, various other non-volatile memory devices are currently in use and the techniques described herein are applicable to any suitable non-volatile memory system. Such memory systems may include, but are not limited to, memory based on ferroelectric memory (FRAM or FeRAM), magnetic memory-based (MRAM)-based memory systems, and phase-based changes (pR趟 or " 〇ϋΜ" ("phase change memory"))) memory. All patents, patent applications, articles, books, descriptions, other publications, documents, and objects referred to herein are hereby incorporated by reference in their entirety for all purposes. To the extent that there is any inconsistency or conflict between the definition or use of a term between any incorporated publication, document or thing and the body of the document, the definition or use of that term in this document shall prevail. Although the various aspects of the invention have been described in terms of a particular preferred embodiment, it is understood that the invention is in the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows the probability function of the threshold voltage of a unit programmed into a logical state and a logic 0 state in a non-volatile memory, including one for distinguishing between logic 1 and logic state. Voltage vD. 2 shows a component of a memory system including a memory array, a 126159.doc -30-200839503 fader/demodulator circuit, and an encoder/decoder circuit. Figure 3 shows the probability function of the read threshold voltage for a unit that is not programmed to a logic 1 state and a logic state, showing the threshold voltage value. The Θ 4 member shows the components of the suffix system, which includes a memory array, a fader/de-arc circuit and an encoder/decoder circuit, and a demodulator provides a probability value to a decoder. Figure 5 shows an ECC unit having a soft input soft output (sis 〇) decoder.

Tian 6 does not store the threshold voltage of one of the two data bits and how the two bit systems such as 7^4 are mapped to the memory state. #图7A shows that the threshold voltage I of one of the four data bits is not stored, and how the two bits are mapped to sixteen memory states to make the adjacent state The least significant bits are different. Figure 7B shows an example of a voltage used to read the distortion of Figure 7a to provide a soft input voltage for ECC decoding. Figure 8 shows the sixteen memory states of a memory that is considered in the decision of a basket of ^ _ a singularity (LSB). Figure 8B shows the eight remaining memory states of the memory cell in the second bit ^, the other eight

^ U state is eliminated due to ECC decoding of the first bit.

The four ECCs of the second bit are shown in Fig. 8C. The decision is made to determine the remaining s replied state in a third bit, and the extra four states are decoded and eliminated. Figure 8D shows the two 126159.doc •31 - 200839503 remaining memory states of the memory cells considered in determining the four bits of a younger brother. The additional two states are caused by the Ecc decoding of the third bit. eliminate. Figure 1 shows a portion of a memory system comprising an ECC decoder of one of four Ecc modules for decoding four data pages, transmitted by the output of the decoded page to a subsequent decoding module 'where it is used for decoding A data page. Figure 9 B can not be used in the example of Figure 9 a essay transfer from the ^ U system, the system - the decoding module - an example. Figure 9C shows another example of a decoding module that can be used in the printer of Figure 9a. The graph shows how the data segments can be stored in the memory array such that - individual segments are stored using the bits in each of the four pages. Figure 11A shows an example of one of the sections stored in four pages, the two pages being encoded using L-hop encoding and the other two encodings. Figure 11B shows an example of a section stored in four pages in storage, one page using LDPC encoding to disk n τ-, ,, and the other three pages using BCH encoding to encode 0. Figure 11C shows four hundred An example of a section of Jian Liu's memory, each page is coded to have a different amount of redundant data. Figure 12 shows a memory system having a dependent BCH code to encode certain data and an LDPC code to encode one of the other codes of the other, which has a solution. On the mouth, Ma Mazhai, which decodes the LDPC coded data and provides one of the human pC solutions to decode the bCh coded data. Figure 13 shows that the different parts of the data stored in the same memory unit are coded according to two different coding schemes before storing the Wei and Zhu in the memory. 126159.doc •32- 200839503 In the memory system, the data is decoded using two decoders for the two schemes, and one output from each decoder is provided to the other decoder. [Main component symbol description] ('

200 Memory System 201 ECC Unit 203 Encoder 205 Modulation/Demodulation Transform Unit 207 Modulator 208 Second Bit 209 Memory Array 211 Input Data Bit 213 Demodulator 215 Decoder 421 Memory System 423 Memory Body array 425 demodulator 427 modulation/demodulation transformer unit 429 decoder 431 ECC unit 432 code 532 SISO decoder 534 soft and hard converter 636 lowest bit 126159.doc -33- 200839503 Γ 638 intermediate bit 640 highest Bit 842 bit/LSB 844 bit 846 bit 848 bit/MSB 950 memory system 952 memory array 954 demodulation 955 input 956 ECC decoder 958 input 960 input 962 input 964 ECC module 966 input 968 Input 970 Combination Circuit 972 Output 974 SISO Decoder 976 ECC Module 978 Combination Circuit 980 Input 982 Soft Output 126159.doc -34- 200839503 984 Hard Output 986 Soft-to-Hard Converter 988 Hard Input Hard Output (HIHO) Decoder 1190 Zone Segment 1192 Redundant data bit 1194 Redundant data bit 1195 Segment 1196 Redundant LDPC generated bit (1198 BCH generated Remainder 1199 Segment 1203 Memory System 1205 Encoding 1207 Modulator 1208 Memory Array 1209 Demodulation Transformer 1211 / Decoder \ ^ 1213 Output 1215 LDPC Decoder • 1217 BCH Decoder. 1319 Memory System 1321 Encoding 1323 first encoder 1325 second encoder 1327 memory array 126159.doc -35- 200839503 1329 modulator 1331 demodulator 1333 decoder 1335 first decoder 1337 second decoder 1339 output 1341 output 126159. Doc -36-

Claims (1)

200839503 X. Patent application scope: 1 · A method for storing data in a non-volatile book, which comprises: '-, first, flat code scheme to encode the first part of the data to obtain the younger brother a plurality of encoded data bits; ζ the first number of encoded data bits are stored in the memory array, and the plurality of units of the plurality of cells comprise the first plurality of encoded data bits At least one of the plurality of data bits of the younger brother; and the plurality of data bits of the younger brothers are stored in the first plurality of encoded &gt; material bits of the Fuling age s — , ^ plural early In the meantime, each unit of the plurality of units has at least one of the plurality of data and the at least one of the plurality of units, and the second plurality of units are not encoded according to the first coding scheme. 2. The method of claim 1, wherein the idiom-^ is one-of-a-kind and a plurality of data bits are encoded according to a coding scheme. 3. According to the method of claim 2, the first, flat code scheme uses more redundant bits than the second coding scheme. 4. The method, wherein the first coding scheme is a low density parity check (LDPC) scheme. 5. As requested! The method </ br> takes a 罝 &amp; and # 匕 3 items to take the plurality of memories to provide the read data to an ECC decoder. 6. The method of claim 5, wherein the reading is for $1, and is provided as a soft input to the main CC decoder, which performs soft input soft output decoding. • If the method of item 6 is studied, the first item of information is 4 - the first plurality of coded Becco bits, and the first plurality of data is decoded by 126159.doc 200839503 Decoding the second plurality of data bits. 8. A method for decoding and storing in a non-volatile semiconductor memory array, comprising: - (10) obtaining data stored in a plurality of cells, each of the plurality of cells 3 being at least one first a data bit and a second data bit; using the result of 4 jing to generate a plurality of first 桉 慎 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖 祖仪正贝枓值, the number of first corrected data values And generating, by the ECC correction of the plurality of first data bits; and subsequently using the result of the reading and also using the plurality of first corrected data values to generate a complex number corresponding to the plurality of second data bits Corrected data values. W-9: A method for requesting decoding of data of item 8, wherein the plurality of second corrected billimetric values are generated using soft input soft output decoding, and a corrected data value is expected to be soft input. a method for decoding data of a monthly item 8, wherein the plurality of second corrected lean values are generated using a second encoding scheme that causes one less redundant bits than the first encoding scheme . : The method for decoding data of page 8, wherein the plurality of first data bits are formed as οσ^, and the wind is programmed as one of the first pages of the early position, and the plurality of first-care 4 music A 枓 枓 兀 is formed as a unit to be programmed and read as one of the second pages. 12. A request + first; method of decoding data, wherein the reading provides a first-origin probability value associated with the one, level TL and providing associated with the second breeding bit The second original probability value. 126159.doc 200839503 The method of claim 12, wherein the first-original probability value is provided as a soft input for generating the plurality of first corrected data values and subsequently producing the second probability values' The plurality of first corrected data values are provided as inputs for generating the plurality of second corrected data values. 14. A method of organizing a data in a flash memory, comprising: (d) - a coding scheme to encode the data - part 1, and 'the first part of the encoded data (9) a plurality of orders The second encoding scheme encodes the second portion of the data, and stores the second portion of the code data in one of the plurality of cells, and then reads the plurality of cells to obtain the reading. Obtaining data; decoding the first part according to the first coding scheme; and taking the material to obtain the data, and then solving the second part of the data according to the second coding scheme, according to the second coding to obtain the data The decoding of the first-coded (four) (d) solution is used according to the method of claim 14, wherein the first bit check (LDPC) scheme. ',, 'Scheme system - low density same 16. The method of claim 14, which has fewer redundant bits of coding scheme. -, the flat code scheme uses the method - 17. The method of claim 14 wherein the decoding system is based on the first-party check round and the decoding system is soft-in and out decoding. Its use is based on the first output as a soft input. The decoding of the horse program 126159.doc 200839503 18. The method of claim 14, wherein the plurality of units further comprises at least a third page. 19. The method of claim 14, wherein the host addressable section comprises a first portion of the data and a second portion of the data. 20. The method of claim 14, wherein the first portion of the data includes data for a first host addressable segment and further includes information for a second host addressable segment. 21. The method of claim 14, further comprising encoding the first portion of the data along with the second portion of the data in accordance with the second encoding scheme prior to encoding the first portion of the material in accordance with the first encoding scheme. The method of claim 21, wherein the first portion of the data and the second portion of the data are decoded together in accordance with the decoding of the second encoding scheme. 23. The method of claim 14, further comprising additional decoding in accordance with the first coding scheme, the additional decoding being output using one of the decodings in accordance with the second scheme. A non-volatile semiconductor memory system, comprising: a memory array comprising a plurality of memory cells, wherein the plurality of memory cells individually hold a first data bit of a first page And a second data bit of a second page; and an ECC encoder, which encodes the data of the first page according to a code-one encoding scheme before being stored in the plurality of cells, and is not stored in the The data of the second page is previously encoded in the plurality of units according to the first encoding scheme. 25. The flash memory system of claim 24, wherein the data of the second page is 126159.doc 200839503 encoded according to a second encoding scheme. 26. The flash memory system of claim 25, wherein the plurality of redundant bits are used more than the second encoding scheme. The flash memory system of claim 24, wherein the first low density parity check (LDPC) scheme. Case 28. The flash memory system of claim 24, wherein the step comprises: 1 taking a circuit 'reading data from the plurality of memory cells; and decoding the read data by an r ECC decoder. 2 9 ·If the clear flash of the item 2 8 is from the volts, the Π圯 Π圯 思 , , , , , , , , , , , , , , , , 读取 读取 读取 读取 读取 读取 读取 读取 读取 读取 读取 读取 读取 读取 读取 读取 读取 读取 读取 读取 读取And use the decoded-output and the read of the first page: to decode the data of the second page. 30. The flash memory system of claim 24, wherein the first page includes a region I and the second page includes information for the segment. 31. A non-volatile semiconductor memory system, comprising: a flash memory array storing data in a plurality of cells, - an individual cell storing at least one first data bit of a first data page and a second data bit of a second data page; and an ECC decoding system that first decodes the first data page and then decodes the second data page using the decoded result of the first data page. 32. The flash memory system of claim 31, wherein the Ecc decoding system comprises a soft input soft output decoder that uses the decoded result of the first page and reads from the plurality of cells The data is used as a soft input 126159.doc 200839503 into 0 33_ as in the flash memory of claim 31, the direct material is based on - the first code is fortunate / the information stored in the first page is not based on the first The end, the Λ 玛 玛 ' and stored in the second page according to the 亥 弟 - encoding scheme to encode. 34. If the flash of the request item 33 is ψη^^^^心-, the 枓 中 stored in the second page is encoded according to the H code scheme. 35. =f (41) memory of item 31, whose step-by-step includes - reading circuit, rate value. A flash memory system for transmitting to the ECC decoding system, comprising: - a flash memory array storing at least one data page in a plurality of single &amp; The first page - the third page: each unit of several units - the second page - the second bit; .,,, and the eight according to a first coding method to compile the data and according to a first - full Gu An, code the first page of the ^ brother, the flat code program to encode the second page of information; the plural two take power: 'it reads the plurality of units and provides and stores in the number of early 70 The probability value of the individual bit in the middle; and: the soft input soft (four) coffee decoding ^, which receives the value from the decoding to decode the first data page, and uses the result of the solution to decode the second data page. 37.=Please, item 36 of the flash memory system, wherein the __lower, degree parity check (LDPC) scheme. ', monthly flash memory system 36, which uses less redundant bits than the first encoding scheme. 4 code scheme makes 126159.doc 200839503 3 9 · as requested in item 3 6 Day &lt; flash memory system, wherein the plurality of unit packs at least one third page 0 3 is equivalent to the flash memory system of claim 36, wherein a single host addressable section extends over the first page and Above the second page. 41. The flash memory of claim 36, wherein the encoder encodes according to the second compilation scheme before the data of the first page is compiled according to the first encoding scheme The data of the first page. 42. The flash memory of claim 41, wherein the decoder uses the second encoding scheme to decode the second material page and the first data page together. The flash memory system of claim 36, wherein the soft input soft wheel out E-CC decoder uses the decoded result of the second data page to solve the first data page of the stone horse. 126159.doc