TW200534132A - Delta information design closure in integrated circuit fabrication - Google Patents

Abstract

Systems and methods for timing-driven shape closure in integrated circuit ("IC") fabrication are provided. These Integrated Design-Manufacturing Processes ("IDMP") include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.

Description

200534132, IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method for manufacturing an integrated circuit, and in particular, to a systematic method. " [Prior art] In very large scale integrated circuits (VLSI), designing and manufacturing highly complicated electronic circuits requires multiple steps. A typical system-on-chip (SoC) or chip design is based on the conceptual chip characteristics Yin Shi's "includes the chip" and the various input and output terminals required, two broad design concepts It is transformed into an architectural design, which contains various elements with functional descriptions and their connection relationships with each other. The various functional units are described in more detail but still not specific, such as using logic gates to describe the function of the unit. Finally these logics will be converted into integrated circuit layouts and then applied to make real chips. Therefore, the integrated circuit layout is the basis for the final real chip manufacturing. Analysis and integration tools are added between design and manufacturing to ensure that manufacturing and design are consistent with each other. These analysis tools can detect layout errors in many ways, such as design-rule violations, or higher-level design errors, such as circuit logic errors, short circuits, or improper power supplies. One of the basic analysis techniques involves the analysis of signal timing in the integrated circuit layout. "Time limit" In the integrated circuit design, it means that the transistor in the circuit must be switched within a limited 'and pre-planned time window. The time margin is divided in advance according to the delay of each component in the circuit. A deep sub-micron system chip may operate at a frequency of one billion hertz (Hz) or higher, so the transistor must complete the switch within a time margin of a few hundred trillionths of a second, and the switch time is about 100 One millionth of a second. Therefore, SoCs that operate at high speeds require smaller time margins. The small time margin is highly sensitive to the size of the component and the way the components are connected, especially in deep submicron system chip designs. Therefore, the use of fine dimensions in integrated circuit design has a bad effect on the time margin. For example, resolution enhancement technology (200534132_ techmques, RET) will cause a significant increase in transistor switching time, because it will lead to the deviation between the actual length of the polycrystalline silicon gate and the design length — Small or chemical mechanical polishing (CMP) can lead to a significant increase in lead delay time, as it can cause dishing effects (c.e.ffects) in high-density connection areas. Therefore, the products produced in the "4 towels in the system" will be offset from the original size in various sizes, which will affect the functional performance. The Yidingxing process was originally the result of the expected low cost and high yield rate, although many offsets were generated in the process; However, the various time problems caused by it make circuit designers have to

Design the original design of the chip beyond the specification to obtain a larger time margin. For example, add an extra buffer to the necessary path to correct # non-gap time errors. These over-spec designs make the circuit description database more and more, thus increasing manufacturing costs, chip area, and reducing chip yield. The above-mentioned problems are mainly due to the specific gaps in the design and manufacturing process of the Coconductor 4. The chip is in the compilation stage, the current job certificate before production is offline, and the geometry verification of the wafer after production (geometry veriflcation) is Separate and without any intersection. Therefore, = Crystal and Circuit Descriptor (ne_ is only used in the design stage, and will not be used in =. Similarly, the crystal image finally printed on the wafer will not be provided to the designer in the model The middle plate f integrates the design and manufacturing process in the positive 4 program. At the same time, it is possible to establish a design and time analysis and verification method, 75 is desired. Integrate the electric power generation m methods for making integrated circuits, especially about ―A systematic production

DeSign Μ ^ 3 Japanese film method, the integrated design process (Integrated g-Manufact with g Processes, IDMp), including the process of time and shape confirmation procedures, and imported by the heart ° integrated circuit flow M1 contains Fresh ㈣ like ㈣ electricity K. The different flow system-progressive line is too difficult to order, in order to deal with the υ Λ peach difference flow can use the difference of the circuit characteristic parameters or () 200534132 ^ bias information, independent re-characterization-integrated electric meter. This deviation process provides a progressive deviation output, which can enhance or re-characterize the corresponding parameters in the tilting element and the relay, without the need for a new line ship record, and without all the information of the reprint_material series. [Embodiment] A system and method for changing the manufacturing process for integrated circuit in terms of time and shape are disclosed as follows: The system and method illegally used for manufacturing integrated circuit are hereinafter referred to as Integrated Design Manufacturing Process (Integrated Design Manufacturing Process) Design-Manufacturing Processes (IDMP), and use the deviation process including the time-deformation prediction procedure and the day-to-day external paste measurement procedure for the application of the integrated circuit. Α Figure Α is an integrated design process program. It is based on the details of the tonnage. The main asset is _ 1 tender, which contains-deviation flow ㈣ 1, which contains-deviation 102 ^ 104, «4 ^, and then 101 The heterogeneous shape time prediction program 102 and / or the deviation time shape pre-adjusted product operates independently or in combination. Panhe style design process program 1ϋ0Α Move and make _ 时 __; its marriage integration is shaped by shape. Cough up the human i1 system to determine the difference _circuit model information ’to get an enhanced circuit model. Program 1_Re_This enhancement is generated by the road model—transmittable error Ϊ = Γ3Γ is designed for use. The ™ model is imported into the time offset meter program (ΗΚ) Α_ 肖 __ying time offset county information. This integrated design generates size __, and uses i ,,, and 6 products to design the model. Provided by H second sequence 1〇〇Α, the different currents_yuji «Lin ^ system works together to output a good signal, can be used independently or with integrated circuit design and manufacturing • x and the connection point structure required Relevant parameters are specific and different. 7 200534132 · "Enhanced partiality information", "Enhanced partiality parameter", or "Partial information". The enhanced deviation parameter information generated by the deviation process 101 can be imported into a typical integrated circuit design and manufacturing process system, such as an automated electronic design system (EDA, system). The enhanced deviation parameter Information has several types that can be applied to integrated circuit design. For example, it can provide separation results corresponding to various parameters, including biased resources Λ of various parameters. The enhanced bias parameter information may also include a modified or redefined integrated circuit design database, which may include linking or appending the enhanced bias parameter information to a circuit description file such as a SPICE netlist. , Or a model, such as in the Berkeley short-channel IGFET model ("BSIM"); it can also include directly replacing the training in the circuit description file with enhanced bias parameter information. The additional connection points and / or component models can be imported without any restrictions based on experience, actual size, or both. Compared with the typical integrated circuit design process, this deviation process has the difference of generating and using parameter deviations to make sense of the integrated circuit design. For example, the parameter deviation can include one or more time differences (which can be referred to as time offset error, deviation time, or unloading and rule difference) in integrated circuit design (known as dimensional offset error, deviation size , Or. The difference may also include circuit parameters used to define the integrated circuit design, such as leakage energy ⑽kagep_ ·). The circuit parameter_ includes but is not limited to, for example, resistance difference, capacitance difference, and inductance difference, and leakage energy, etc. The deviation process ωι includes procedures for processing input information, such as deviation information, and 2 procedures for generating a predetermined assignment of deviations based on one or more components or connection points. The pre-determined allocation of bias may include a number of different parameters, such as including, not equal to, resistance, capacitance, inductance, circuit or component parameters, shape parameters, and parameters. The input information can be other Deviating process or other legs and / or designing the system, but not limited to the above examples. Japan, = Different process 1101 also produces a deviating output to violate or affect the circuit when the difference Designed the source or location of the «generated. The biased output can be generated according to the source 8 200534132 * Independent output information, such as ΛΓ In addition, the biased process ⑻ the independent capacitance value of the component C in the white road Differences. Multiple procedures and fine details. Can provide a lot of dependence to Huan_species, and provide poor efficiency efficiently. It can reduce the reliance on dragon library and other information. It can increase the efficiency of circuit design and reading system. And it can reduce the database. It depends on the ship ’s time. It is a half-mesh that reduces the number of simulation operations. It is even more important that Si rides on the wire, instead of re-simulating the entire circuit after adding new parameters. ^ 文 /, 介绍, 后, 将, 将 will introduce many detailed features and understanding of the circuit system. Any of the examples in this embodiment can be operated separately. After reading this manual, you can understand this: Guan_le ~ Do not use 'combination' or combine materials with other lines and other examples are only illustrative to illustrate the system and Fang Shulan Wu of the present invention = She Niu, α_machine integrated circuit diagram -B system is- Integrated The block diagram of the calculation process program is in process _ circuit towel, according to-practical supplement, job combination _ process = layout, ^ secret in-domain multiple circuit design program 1G, circuit layout program 12 (including ^ & coffee reading office 14, Weinuo Office 2 卩, Qi Laihua Technical Process ^, Fine Sequence 24, Deformation Shape Time Prediction Program (Sweep ⑽ ⑽㈣ ⑽㈣ 测, 郭 nTentp sunny coffee side. The deviation process includes the deviation shape 2 Sequence 102 uses the bias time contour prediction program 104, but in other embodiments, it can be selected separately for operation, or it can select more than one bias shape time prediction program 102 and the partial time.

The temporal shape prediction program 104 operates simultaneously. ”T Simultaneous circuit design program 10, circuit layout program 12 (including layout and connection), time analysis program Η 'distortion shape time prediction program (Μ_ρι, _㈣ ，, deviation time Liu Yancheng Cheng Tent pss) just It can be called a design program, and you can also select the required combination of operations according to your needs, or integrate it with other integrated circuit manufacturing processes. Similarly, the shape verification program 20 'resolution enhancement technology program 22 and process program 24 can be called The manufacturing process can also be selected according to the needs of the selected combination of operations, or integrated with other integrated circuit manufacturing processes. * ,,, 9 200534132 * In general, the circuit contains a large number of independent parts, so electronic circuit design Usually, computer programs are used to assist and automate circuit design procedures. The integrated design process 100B may include one or more automated electronic design systems (EDA SyStern) or other auxiliary design and manufacturing systems. Therefore, the following for In the description of the integrated design process, each subroutine of the integrated design process can be independently fulfilled -One or more automated electronic design systems or other auxiliary design and manufacturing systems. Wen 1 said that δ and juice process procedures 00B accepts one or more high-level hardware description languages, such as VHDL, Verilog, etc., and then It is translated into a low-level description language, such as the circuit description file φ case (lletllSt). A circuit description file will describe the design, components, connection points, and connection methods of the integrated circuit, which can be converted into —feng_ Circuit image, where each connection point will have a corresponding connector. In a higher-level abstract description, a generic circuit description architecture (generic⑽㈣ can be obtained through a technically independent original slot (techn〇bgy inde _ ^^^ primitives): The integrated design process program surface can translate this type of circuit description file into a low-tech circuit description file based on a technology characteristic database (technology ecihclibrary). The technical characteristics f library also It is called the unit database (1 out of rary), or the component database ((1_ 诎 ㈣), which contains a logic closed model to predict a circuit design Time and power parameters. The integrated design process program system uses the preview, takes the media storage circuit description, weaves and verifies the circuit description age, to generate a physical component layout mask format, which can be directly in the process. It is used to integrate circuit components. Λ 7 Circuit designers design circuit programs and produce high-level bribe languages to describe circuit designs, such as using hardware description languages such as Vei, iiog, or VHDL. This high-level hardware bribe It is transformed into a circuit description program, which describes the components of a circuit and these elements; the wires that are connected to each other (that is, the "connection" or "network" of the circuit). This circuit description program does not represent the position of these components on the real Shixi chip, nor does it represent the connection path of the physical wire. The integrated design process 100B uses the circuit description program in the layout program 12 to generate a physical layout diagram. The layout program 12 determines, for example, a configuration program and a connection program. 10 200534132-Determines the configuration of the physical components and the access routes of the wires, so that the component configuration program uses the information of the circuit description program to determine the position within each chip. The position information usually contains two axes, for example, Shi Xiyue said that this position usually takes into account many optimization goals, such as the width of the wire, two = electricity = this cloth is fruitful to include-with each component structure to 1 The circuit description program uses the private location data to connect the endpoints that need to be connected. The path connector is structured according to the component, and the component location data structure will be used at the same time to determine the shell material library for manufacturing. Used for solid volume circuits. The integrated design process program] _ through any program 10_ circuit design layout when the axis deviates from the shape 丨 program] G2 knot: =, 102 ^ = size deviation information. In other implementations, you can also continue to get the size offset information in a selection of 10-24, or a private combination of 10-24. The size offset error condition includes at least one horizontal and domain vertical offset error related to each piece: Buttons, such as length or money offset errors, thickness offset errors, and other reading parameters. Offset error material. Circuit components include all the components and connection points that general integrated circuit materials would use. The misalignment of the inch size includes but is not limited to the material of each layer in the wafer and the deviation shape information of the position (x, y) (which can be expressed as "the deviation shape" or "record"). In the case of cattle, the change of the county's light duty position and / or other close-knit nature (Tao-yin-based) will lead to a shape deviation error. The thickness offset error 々 represents a thickness offset error that can be caused by the layered material_systematized characteristics in the wafer. The deviation shape time prediction program usually uses the deviation shape △ _ to integrate the integrated circuit 200534132 · The time and shape deviation error program in the process, that is, the design information program that will disturb during the process, such as resolution enhancement Technology (RET), detection, and so on, and then import the results into the layout of the integrated circuit design. To achieve the above purpose, the deviation shape time prediction program 102 integrates the deviation shape Δά / Δί and introduces it into a circuit model to form a time description and / or an enhanced circuit model. The deviated shape time prediction program 102 can use the output result 'from the resolution enhancement technique prediction tool to generate the deviated shape Ad / At result described above.

In the integrated design process program iOOB, the component weight sequence including the deviation shape time prediction program 102 is generated using an enhanced circuit model—a model that can be simulated by integrated circuit design, and generated based on the model The time offset error information (Δτ) is described in more detail below. The integrated design process program 100B couples the time offset error information to the time analysis program 14 and can also consume the time offset error information into one or more circuit design programs ig, layout programs 12, and shape verification programs 2 〇 Among the resolution enhancement technique program 22 and the process program μ, various known EDA programs may be used instead. The integrated design process can also integrate the time offset error information into the InTent processes 104. The deviation time shape prediction program outline uses the time shift error «tfUX to generate a deviation shape weave or _ for subsequent integrated circuit manufacturing processes and integrated design process program planes, including the deviation shape time prediction program. ^, Used in, described as T. The deviation time and shape prediction program just outputs the deviation shape △ _, and the "Finished_Making Miscellaneous Pre_sequences" is described in _touch, and can be coupled to other verification procedures in the design and manufacturing process. Min Yi Tiao Yi Ye leaves a detailed block diagram of the process program, which contains a partial display process, which «made <<«, root system-actual supplement, process = includes but is not limited to-one or more circuits Design program ω, circuit layout process including layout and continuous driving) Mock analysis, M shape program μ, analysis details ^ order 22 'manufacturing process 24, deviation shape time prediction process Guo) is processes) 104. The explanation in ♦, W Reward coffee_ = 12 200534132 · Information about the deviation of the shape of the material 15 and / or the manufacturing process 25 △ Qin Xi 嶋 = and / or time prediction. In addition, the time of the deviation is different, multiple design processes are 15 and / 势 生 生 %% ^ debt gangmumu-one or more Griffon-shaped rules to make it to-one or in the deviation __ gift == Miscellaneous __ sequence of heart design and information on the shape of the deviation from the integration of electrical components and / or connection points. This extraction procedure includes and any = one or and is not limited to components or connection points. … Ten information about related objects. The biased information can include bias capacitance value, bias and a bias resistance value △ can represent —, U valley value f violates the integrated circuit about-specific connection point The first design limit map is a product f-way design of a shape-distance prediction program 102 shape time range 庠 HP to H. The deviation program 丨 02 will then output the information including the deviation shape f and; = shape time reward. In addition, the deviation shape time prediction program 102 can still use the result. Deformation information is used to enhance the application. In the embodiment, two = programs 102, such as but not limited to resistors, capacitors, inductors, circuits or components continued, Γ &gt; forging shape parameters, and time 13 200534132 parameters, etc. Prediction procedures for the misshapen shape included in the process program are stored and / or other electronic models produced by the miscellaneous materials and the sequence are used for integrated circuit design. &amp; The biases described here can be made by using the biases of the various parameters in the design of the product f-way. fl to reduce the dependence on the cell database and connection point database in the integrated circuit design process. However, the 'reliable shape time prediction process 彳 i () 2' uses the biased resources in the biased process' to the above-mentioned single lean database and / or connection point database. The modified component or single 7L package in Hunan Province is produced in the database. Wei Wei makes appropriate and progressive modification of the original component model database. • As described above, the abnormal shape time prediction program 102 receives the physical description of the offset difference data from the integrated circuit layout and size, which includes at least the gate length offset difference of the components and connection points on the layout Δ (1, the difference from the thickness offset Δί, etc. The entity description can be, but is not limited to, an image or a text slot case. The deviation shape time prediction program 102 reads 60% into Ad and Miscellaneous in function M㈣3. Shape Ad / At Integral Integrated Circuit White \ 11 Body Description.

When the components in the center are laid out, the deviation shape time prediction program 102 may block the difference of the parameter deviations from the single-component, such as the deviation capacitance value ^, with each component = == _ „ _ 方 _ 的 _ 讯。 This partial side work _124, take _ Lai Xun to generate time, be Λ and / / strong integrated design process program data, the original unit database data. Enhance Lai database Wei contains For each parameter, the results, and / or = partial corrections or surface definition library components: New York. The correction of Yuanlai type can be linked or appended to 2 or more with the parameter offset difference information of the cup. The circuit description procedure ^ t. „AD SPICE netnst ^ Begley shor, channel IGFET m ode, (BSIM) f The modification of the hardware model replaces the information in the original description program with information that includes parameter offset differences. Circuit At the connection point part of the layout, according to the function block ⑵, it will deviate from the shape to a __ bribe. According to the lion block 123, the outline time = J4 200534132

Ac; AR ^ ^ Γ, information. Coaxial data power warehouse _124, the deviation shape time prediction program ^ Use the deviation data mAC / ARML to enhance the original connection point = side process tender. __ Following the results of ^ K independent, and / or _ deviation fmAC / ARML correction or face definition database connection point model information. Modification of the component model can include job difference information ΔσΔ job link Gaga to one or

^ Circuit description programs' or models. The modification of the component model may also include the use of the information of the original circuit description process with the biased AC / ARML. In function block ’, the time prediction process of the abnormal shape 4 102 is based on the enhancement of the component and connection point database model, and the enhanced model is used to generate the electronic model of the integrated circuit, and the time analysis of the integrated circuit model is performed. The time analysis result includes, but is not limited to, the time offset difference of the circuit model ^. According to function block 126, the deviated shape time prediction program 102 produces a time result, which includes a time offset difference Δτ. Η Figure 4 is a block diagram of the deviated shape time prediction program. Its application is to generate a deviated «to correspond to the connection architecture, according to the embodiment. The abnormal shape inter prediction program receives one or more files from circuit design, database exchange format / design exchange format (LEF / design exchange format, DEF) file 402, a technical file 404, and Parasitic delay format (stancjard parasmc, such as ㈣fomat, spef) weight ^ 406. The deviation shape time prediction program 1021 also receives the deviation y-shaped data Λ of the connection points in an Ad file 408. Database exchange format / LEF / design exchange format (DEF) file 402, technology file 404, standard parasitic delay format (SPEF) file 406, and Ad file 408

The data can represent one or more pre-defined integrated circuit ranges, or the entire integrated circuit design, but is not limited to this C. The deviation shape time prediction program 1021 uses the integration circuit design information and the deviation shape information 200534132 · The capacitance AC double number includes, but is not limited to, the deviation resistance value AR and the deviation time. In the bias case 412, the bias function 406 is used with the MSP to generate a newer bias parameter. Enhancing the SPEF instrument includes adding FU //, center, connection, or addition to the SPEF file 406 as described above. Explanation /, S% prediction program 104 outputs the miscellaneous Δ · rule, referring to the t &gt; 104 5 ^ ^ analysis time in the figure 1 above. The prediction weight sequence 104 receives time points from one or more circuit models. 142 ^ ^ ^ Poor &amp; so ___ points ^ between the early _ inter-offset error database, the content includes human maiden son and daughter in the work block 143, which produces the offset error Δτ node time _ = Zone t error Δτ, and each single core and / or such as the value of the deviation capacitance ..., and the deviation of electricity = and: the following _ to the epicenter ==== == the description of the unit in the database of two matching units , To determine or calculate the single 3 shifts = Γ, in the secret recipe _ towel ming _ then fine _ _ inter-partial bias' to obtain the date of each-connection point _ shift error &amp; the biased capital hole △ c 胤, to Generates, for example, the deviation capacitance value AC, the deviation resistance value slave, and the deviation inductance value: the deviation lean signal of each point. The above method includes, for example, the use of --link ,: 'cooperate with the dependent data to describe and update the link_two fields; 16 200534132 corresponding to each component and the deviated shape △ _, and its contact information △ (: / △ [ In order to generate the deviation ㈣Λ, λ "&quot; The spot has a shape Ad obtained at the m point of the spot. In this example, the deviation information can be obtained from the connection point structure after the deviation time is 104, which can also be taken. Any deviation information defined in Material Road 2. The circuit is also a block diagram of the integrated design process program_, its forecasting procedure, and the time-of-deformation measurement of the deviation, so as to be measured in the integrated circuit_ fiscal

_Figure ... The embodiment of Figures 2, 4, and 5. In this example, the integrated design process shows the time prediction program 102 and the time prediction program of the deviation shape. The program included in the system is 26 μm, which determines your secrets. The functions of the partial fine coffee measurement range 102 and the deviation time profile prediction program are as described in the instruction manual, and can also be described with reference to Figs. 3 and 5. EDA Pure contains the same functions as the order and the general system, but is not limited to this. Each process of the integrated design process will generate an enhanced unit database with biased information based on the original library information to supply the FDA _ procedure. As mentioned earlier, this strong or modified Yuanlong The model can modify the original view so that it contains the ^ different shape △ (!) Of the receiving tree. The process includes modeling of each element, so that the electric valley offset error AC of each piece can be taken out from the deviated shape ^. The above-mentioned process of component parameter modification or update characteristics utilizes Xu Xi principle. One of the components is that the update characteristics are completely compatible with the existing component model. At the same time, the component parameters with updated characteristics are also completely compatible with the signal delay model. The delay can be expressed as Signal Delay ^ k (Vdd / WIon) (Cin + Cout + Cwire). Moreover, the element parameters of this updated characteristic provide current conservation. According to the following current expression, the drain, and pole currents ("Ws ,," ^ eftQx (W / L) [(Vg-Vt) Vds- (m / 2) Vj ^^ 忒 The modified component model (or 1DMp component model) assumes that a transistor used in the component database is in fact Does not have a single-gate length. Moreover, the 1 The DMP element model assumes that the transistor does not have a single gate length. Figure 7 is a block diagram of a transistor 700 with a 1DMP element model. The element model has a non-single interpole length, according to an embodiment. This example The transistor 700 in the assumption assumes that its gate 710 has a non-zero offset error at 17 2005341.32. This assumption is from empirical data. Therefore, the gate length of the gate 710 is calculated from the junction point 702. From about 00nm (gate length offset error is about + 10nm), and about 80nm from the polycrystalline silicon endpoint 704 (gate length offset error Ad is about 10nm) 5 Wu difference Ad is + 10nm and -10nm as shown in this example, and will be shown throughout the gate length. The application of the 1DMP element model is not limited to the transistor with the above characteristics. IDMP The component model can also put the effect of gate length offset error Ad on the component parameters into the model. Generally, e, because of the non-uniformity of the gate length, the IDMP component model assumes that a component φ contains many gate length offsets. Parasitic capacitance due to the error Ad. For example, Eight series is a block diagram of the gate / junction capacitance of a transistor 700 of an IDMP element model, according to an embodiment. The transistor 700 includes a base plate 802, a source region 804, and a drain region 806. An empty area 808, and a gate 810. The parasitic capacitance in this model, for example, includes at least one gate-source capacitance (Cgs), gate-drain capacitance (cgd), and source- Base plate capacitor (csb), gate base plate capacitor (Cgb), and drain base plate capacitor (cdb).

Using these parasitic capacitances, the IDMP model assumes an input capacitance (uCin55) of the device to be approximately |

Cin = Cgs + Cgd + Cgb. 隹 丁 IDMP model also assumes an output capacitance (“Cout”) of the device to be approximately

Cout = Cdb + Cgd. Using these parasitic capacitances, the IDMP model assumes that an input capacitance Cin can be expressed as Cin = Cgs + Cgd + Cgb. The IDMP model also assumes that an output capacitance c0Llt can be expressed as Cout = Cdb + Cgd It can be found in this example that the IDMP model of the transistor 700 uses the gate length offset error Ad information generated by the uniform gate length model and the parasitic capacitance model to enhance the component parameters of the cell database. 18 2005341-32 Figure 9 illustrates a modified element model parameter 900 of a transistor with a gate length of deep sub-micron (about 100 nm), according to an embodiment. The gate length offset error of the transistor is used to modify the parameters of the element model 900, including the effective channel length, the on voltage, the Cgd / Cgs overlap capacitance value, the input capacitance value, the output capacitance value, and other various parameters. The gate length offset error Ad can be used to modify parameters of other component models applied to the component. Figures 10A and 10B are related to the influence of the gate length offset error Ad on the operation of the element. Figure 10A is a graph of a signal delay of 1010 of a transistor model of an integrated design process corresponding to a gate length offset error of 1020, according to an embodiment. Figure 10b is a graph of the saturation current 1012 of the transistor model of the integrated design process program Φ corresponding to the gate length offset error 1020, according to an embodiment. In addition to enhancing the unit database, other procedures of the integrated design process also use the modified original EDA system to include the deviated shape of the connection points in the design, Δά / Δι, to produce a modified connection point database, as described above. This correction includes modeling the connection points so that each connection point can take one or more capacitance offset errors Δ◦, resistance offset errors AR, and inductance from the corresponding deviated shape △ center. Offset error AL data. The connection point parameters (connection point database) are modified or updated by the wide IDMp connection point model. Figure 11 is a cross-sectional view of an IDMP connection point model 1100, according to an embodiment. The connection point model 1100 includes a metal wire gift, which has a size d and a thickness t. The metal wire 1 is Connected to at least one requirement location on the same level in the component. The metal wire is at a distance s from the requirement 1104, wherein the requirement can be any component, connection point, and / or other circuit design usable structure. A coupling capacitor Cc is generated between the metal wire 1102 and the element circle. In addition to being adjacent to the element 1104 on the same layer, the metal wire 1102 is also adjoining another 2 m2 in the chip. The connection layer U12 can It is any layer or base plate in the circuit design. The ground connection Cg is the result of placing the metal wire 1102 and the connection layer ⑴2. Multi- ?, A IDMP connection point model 1100, integrated design The process program contains and develops a set of 19 2005341 * 32 sets of integrated circuit design ArJM + Beans * Decoupling / Time Deviation _ Difference &amp; Off _ Function Set. The two depend on the circuit Stuffed coffee loses shape Prediction procedure of deviations), and the use of time deviation 2 △ dM ^^ / At (such as the procedure for measuring the deviation time profile of the compilation), etc. The deviation of the connection point ^ 3 offset error of the bile-like inch d Μ, and the thickness of the wire · [offset error i Δί. The assembly of the integrated design recording sequence is assumed to produce a deviated shape

The size of Ad / At compared to the real drop bucket 9 of the wire is not small, and this is obtained according to the weak perturbation theory.

The above feature set is a linear-like heterogeneous group (quas-ear if deleted), which describes the shape of the deviation Δd / At and the resistance offset, or the progressive parasitic junction resistance ship wind capacitance offset error

Δq or _ of the progressive parasitic junction capacitance AC). The total resistance value of the connection point includes the capacitance Capacitance and the ground capacitance Cg. J C = Cc + Cg (Equation 1) 1-port type. Also, when describing the relationship between the deviation shape and the resistance offset error AR, the process program can be expressed as AR / R ^ -At / t-Ad / d (Equation 2); At the same time, the integrated sap process program is described in The relationship between the deviation shape &amp; the meaning and the capacitance offset error can be expressed as AC / C ^ (Cc / C) (At / t) + (Cc / C) (Ad / 2s) + (Cg / C ) (Ad / d) (Equation The above-mentioned integrated design process uses corrections to these relationships to include one or more modulation factors or variables. These modulation factors can be expressed as K1, K2, K3, K4 And K5, which can tune any error effects caused by weak perturbations and the additional capacitance added to the coupling capacitance Capacitance. The correction relationship between the aforementioned deviation shape Ad / At and the resistance offset error Διι (Equation 2) Can be expressed as △ R / R two-kl (At / t)-k2 (Ad / d) (Equation 4) after considering the modulation factor. At the same time, the above-mentioned deviation shape Ad / At and capacitance offset error AC ( The correction relationship in Equation 3), 20 200534132 can be expressed as △ C / C = k3 (Cc / C) (At / t) + k4 (Cc / C) (Ad / 2s) + k5 after considering the modulation factor (Cg € ^ Eq. 5). Taking the capacitance offset error △ &lt; as an example, Comparing the results of Equation 4 and Equation 5 in a simulation (for example, generated by Sf &gt; ICE simulation), the capacitance offset error AC (after normalization) and the metal wire size d's amplifying disturbance μ (represented as a size) can be obtained. The relationship between the percentages) is a nearly linear relationship. Figure 12 is a normalized capacitance offset error AC 1210 corresponding to the connection point perturbation Δ (ί 1220 size of the hundred-to-blade ratio curve 1200, according to a Embodiment. Similarly, in a circuit mode

Comparing the results of Equation 4 and Equation 5 in the simulation, the relationship between the ship capacity deviation error Δε (the perturbation of the normalized wind metal wire size t after (normalized as a percentage of a size t) is also The relationship is close to linear. Figure 13 is a graph 1300 of the -normalized-capacitance offset error △ CD, which should be connected to the perturbation of the connection point perturbation M ·% / size, according to an embodiment. The above program set is also described The relationship between Ad / At and a-to-A offset error Δτ is described. Using the same assumptions as above, and referring to Equation 15 'Integrated non-calculated process procedure, the time offset error Δ read resistance offset is described. The error and the capacitance offset error AC can be expressed;

At / t ^ ar / R + aC / C (Equation ό) · Substituting # 4 and 5 into Equation 6 ’can be obtained

ΔΚ / R + AC / CL ^ (Cc / C) kl] (Δτ / τ) + k4 (Cc / C) (Ad / 2s) + [k5 (Cg / C)-k2] (Ad / d) (etc. (Equation 7) Comparing the results of Equation 6 and Equation 7 in circuit simulation, we can get the relationship between the time offset error (L) and the perturbation Δ (1 (expressed as a percentage of a dimension d)) of the metal wire size d It is also a nearly linear relationship. Fig. 14 is a graph of the normalized time delay M10 corresponding to the perturbation of the connection point. The percentage of phase in a d-square is just, according to the embodiment, the above equation ^ illustrates In one embodiment, the relationship between the fine current, the uneven resistance, the uneven resistance, and the uneven inductance in the uneven flow axis. However, there are many other functions, such as the 21 200534132 higher-order equation function, and Many different function combinations can be applied to other embodiments in the same manner as disclosed in this specification. Figure 15A, Figure 15B, and Figure 15C are structural diagrams of the connection points after the deviation parameters are extracted. 1500, according to a conventional embodiment, the connection point structure 1500A includes a metal power grid 1520, which is connected to a through via 1560 It belongs to a power supply lead 1504. The power supply lead 1504 has a dimension d and a thickness dimension t. The power supply lead 1504 has a first neighboring structure 1510 and a second neighboring structure 1520 in the same layer. The first The structure 1510 has a dimension dl and a thickness dimension t, and is a distance si from the power supply lead 1504. The first structure 1520 has a dimension d2, and a thickness dimension t, and is distanced from the power supply lead 1504. A distance S2. Figure 15A shows the connection point structure before the partial parameter extraction] 5⑽a. Before the partial parameter extraction procedure, the connection point structure 1500 has about ten child nodes, or the change area (change area ) 1530. Fig. 10B shows the connection point structure 1500B after updating the shape of the connection point using the deviation shape information. After updating the shape of the connection point using the deviation shape information, the connection point structure 1500B has approximately forty child nodes, or Change area 1530 .:, Figure 15C shows a connection point structure 1550c of an end point view (the end point view of the connection point structure 1550A / 15500B), which It has size parameters and corresponding deviated shapes for the use of deviated capacitors. According to the deviated shape time prediction procedure in the description, the deviated capacitors AC 'C and d + ( ㈣sl) Asl + Qing Jiao Fun + (Job Boxing 2 + (5C / ^ 12) Ad2 + (such as / Calling (Equation 8) and AC C (d + Ad5sl + Asl5dl s2 + As25 d2 + Ad2) -C ( d, sl, dl, s2, d2) (Equation 9) Equations 8 and 9 represent an embodiment of the partial capacitance extraction. Other bias information, such as bias resistance and bias inductance, can also be obtained; and different functions, such as higher order equation function '22 200534132 and different function combinations can be performed according to other descriptions in the description. In the design of Kushiro *, the number of refined shells when the shape of the deviation is increased is increased. These additions are a significant burden on the processing efficiency of Code N μ ^ '5 and 5', because of the blood type ~ When faced with newly added characteristic parameters and biased information, it is necessary to reprocess the whole as a whole, ' The typical integrated circuit ② has different calculation processes. The aforementioned inter-prediction procedure and / or deviation time profile prediction procedure) uses the deviation information about a _ ^^^^ parameter to re-characterize the _integral circuit design. This process flow_ can enhance or re-characterize the parameters of the corresponding components and connection points, and it is not necessary to re-process all the information. Borrowing the poor information individually provides the output of biased information. This biased process reduces the dependence of the original library information on the design process, because it efficiently targets specific circuit parameters = n / ... low (or / ) + More in the design process towel (lookup ope theory on). What's more, the biased information allows Gamma to progress progressively, and "to be re-adopted after the generation of a __, so it can increase the efficiency of the design process, slightly more radioactive. The description of the connection point model allows the deviation shape of each node △ her information to take one or more deviation capacitors ^, deviation resistors, or deviation inductances from the points or junction points in the layout. . The bias information M, F, and field & can also represent parameters U ^ f ^^^ menhanced characteron pa ^ ete,) ^, f (enhanced characterization parameters) 〇 ^ points of capacitance, resistance, and / or electrical state new practice. Ride ^,,, and ac / λ ^,: &quot;! M new values for capacitance, resistance, and / or inductance. ^^ Next n points According to Figure 2 and Figure 3, the deviation shape time prediction program 102 or other integrated design system 23 200534132 &quot; ΪλΤΙ :: ™ &gt; and / or the deviation of AL. It will use direct extraction pr〇cess) ^^ # ^, ^ fl ^ ^ tm ac, ar, AL, eXtraCti〇n Pr〇CeSS) ^ f ^ Other embodiments ___ sequence ^ = sequence_ming, but minus For the sake of limitation, the production of towels and unit data bases by Lai Shao or Yun Wei Wei △ ⑽ According to the deviation shape △ She directly calculates the deviation parameter information in the deviation shape △ • with at least one deviation == 程; r:-. «t; Γ! ΓΤ / ΠΓ 'ΓΓ &quot; 1-7 * .AR, U /.- ΛΙ, the deviation information AC, which is the mother and the connection point, and Equation 1 7 Γ money For each link of Sekko Na, △ _, the more one calculates the bias information of each link, service, and / or 乩. Straight two in the library =: Two tweets 讥 扦 扦 偏 偏 偏 &&;: AR, and / or 0 after = = 6 ^ 3 ^ map preview, used to obtain the modified contacts The modification of the shape = Γ, the time prediction program receives or reads the corresponding deviation of the physical electrical layout description, and confirms the connection point of the layout, thereby starting the extraction process. Weaving = allogeneic order In the function block 161G, the state of each-connected points in sequence may include, for example, a sequential silk polygon. It includes when the design shape is partial; point sampling 'and a vector that generates a vector to represent the sampling point Ad disparate shape Ad. This round of procedures relies on vectors to form—polygonal secrets, which can be expressed as a block diagram of [Ad Figure 17 is a polygonal connection point] 700, according to an embodiment. The deformed 24 200534132 prediction program polygonizes the connection point by modifying—area_original size_) or the connection point 175G of part of the original material polygon (that is, the error M vector between endpoint A and endpoint β, — Taking the connection point H0G as an example, the sequential representation of the polygon starts from the original size D0 of im such as Γ to form a new size D2 of the new zone 连 1 at the joint point of the first zone ㈣1. Polygon The program then shifts the frequency due to its corresponding size ^ is the strong size D of the sequence ^ Zhengzhisi__, in the power moon block 1 6 1 0, the pot p shizhi, the ghost f can block ⑹2, the bias A bimorphic program (return to the program in Figure 16), and another one at the beginning of the succession (the Ir test program re-obtains one or more original lookup tables to retrieve the required capital 1, the private sequence of ㈣1 contains 'For example, using one or more methods can also be applied in other embodiments. The node that retrieves information through a database or other source is cleared, and then the use of Ruoxiu to correct miscellaneous fun is also §fl. Characteristic parameters, the comparison process ^ 'number &quot; ^, is about recharacterizing the new junction interval. Compare—the original connection point area ⑧〇 and—corresponds to the difference Μi (in the shape of the coffee _ scale she coffee _ (that is, the difference in size of the size corresponds to the modified characteristic parameter of the modified connection point (capacitance 25 200534132 or inductance). The correction parameter can be changed from the original capacitor, ::: paste rotten __ ==== link, ,,, etc. The information of the lean library is modified. The connection point data is added to one or more circuit description files. ㈣acmrml △ C / △ data to replace one or more original electricity: two containing: material library can also _regular_domain practice of f capacity Lexiu or inductance, instead of one or more circuit description The data of the target case. 丨 And the deviation ====== ^ =: The degree of the measurement procedure, which uses the information of the deviation shape to directly rely on the poor library to calculate and replace the external selection method. For each segmentation point in the inference, if it is allowed to include the direct calculation of the partial m, the EDA and / or other design and manufacturing systems can be used for some of the parts. Procedure for retrieving information.-Retrieve the information in the Λ mode to refer to the places on Figures 1, 2, and 3 for the recorded viewers. Controlled by the server; Control two but many need f a "Ming process _ in detail," the person who is in this technology-can follow the method of the present invention. According to this, "" &quot; ^, ° code, microcode, program logic array or other use of memory, 1 material phase_4 course_algorithm or general operation, can be stored in non-volatile such as optical discs, with == "parts, phase_body area, The erasable medium, as described in the example: =: first: = &quot; ~, semi-other process program, which can be implemented in the computer system or its main sequence. These programs are specifically implemented as code. Stored at 26 200534132. Machine "Π r. It is executed by the processor of the computer system when it is sold or the computer calls for the memory area or computer system components. Although there are many computer systems that can be used to use the integrated design process, FIG. 18 is a schematic diagram of a computer system 180 that controls the integrated design process, according to an embodiment. The computer system 800 generally includes a central processing unit (cpu), or central processing unit 1802, to process information and instructions, and an addressing / data bus 8101 coupled to the cpu 1802 for communication. Ceremony ~ Volatile 5 1 think 1804 (such as random access memory, RAM) handle to the bus] 801 to store dynamic information and instructions from the CPU 1802. The computer system i8㈧ can also include a successful optical storage element 1808, which is connected to the bus iso to store data and instructions. The storage element or data storage element 1808 may include one or more erasable or optical storage media, which is a computer-readable memory. Various combinations of volatile memory 1804, non-volatile memory 1806, and / or storage elements 1808 store the information describing the procedures of the integrated design process program, but the integrated design process sequence It is not limited to being stored in the aforementioned media. …. 'The computer system 1800 may also include at least one optical display element] 8 丨 〇. It is coupled to the bus 1801 to display information to the user of the computer system 180. The embodiment of the computer system 18㈧ may also include one or more optical input elements 1812, which are combined to the bus 1801 for supply. Pass the information and instructions selected to the CPU 1802. In addition, the computer system includes three optical vernier control or pointing components, which are coupled to the bus 1 to 1 to transmit information and commands that are input to the CPU for inspection. The computer system can also include one or more optical signal conversion elements 1816 (such as transmitters, receivers, modems, etc.), which are integrated into the bus 1801 to provide a communication interface with other computer systems. The system and method for manufacturing an integrated circuit described in this specification includes a method that corresponds to at least one connection in a circuit design using one or more functional deviation parameters and a size offset error of at least one of the connection points. Point directly generates a progressive deviation parameter. Among them, the $ deviation parameter includes one or more electronic parameters capable of characterizing the connection point, and each parameter = 27 200534132 Contains-method === inch offset error and one or more electrical characteristics that characterize the connection point: j &lt; pre-defined circuit circuit design, at least one connection into the deviation reference method. The subtraction includes one or more points of electronic participation, tm on each side. Hua Hai links the manufacturing method of this manual «Complete Electricity_News and Methods, including-method, functional deviation parameters, and at least one component's dimensional offset error: the circuit has at least one component and the money has a progressive bias. ⑩ Number of ways. The partial mile in 1: The number contains one or more of the electronic parameters that can characterize the component, and the difference of each parameter is :: Lu fl. v. The system and method for manufacturing integrated circuits described in the Beiben specification, including -methods that use shift errors and one or more electronic parameters that characterize the component. ί ^ ΓΓ Design, corresponding to at least one Directly produces a progressive deviation ☆ 'The towel deviation parameter contains one or more electronic tea numbers that can characterize the component, the difference information of each parameter. The system and method for manufacturing integrated circuits described in this specification include: a method including receiving-including many components and connecting circuit design; using the size difference in the circuit = measuring at least one of the progressive deviations in the circuit design Parameter and progressive time difference, where the deviation parameter includes-or is able to characterize at least-the difference of the parameters of the element and the connection point; and the integration of at least-the size difference and the progressive deviation in the line design Parameter, = progressive time difference, modify the line design. The above method further includes using at least one size difference, a progressive deviation parameter, and a progress time difference to generate a circuit design model. The method described above further includes using at least one size difference, a progressive deviation parameter, and a progressive time difference to enhance the information of the model of at least one component and the connection point. The above method further includes adding at least one size difference, progressive deviation parameter, and progressive day difference to one or more line descriptions, wherein the line description has at least one 28 2005341.32 · image data representation, and _ Text file representation. The above method further includes using information including at least one size difference, a progressive bias parameter, and a difference in progressive time, Qian Xin—one or more _㈣ 中 _ 关 信息 section. The above method further includes using at least one size difference, a progressive deviation parameter, and a progressive time difference to re-differentiate at least one element and the connection point. ’,

The test method of the above method includes the difference of the shape and size, and the progressive deviation parameters are taken by at least one element and the middle one. The way of fetching includes mapping the size difference to the circuit design. The ten tearing method further includes at least one or more functions to form one or more functional differences between the dimensional difference and the deviation parameter; and the direct use of the dimensional difference and the functional relationship to generate the progressive deviation parameter in the above method includes a characteristic Progressive differences in circuit parameters for at least one component, connection point, and one or more connection point intervals. The circuit parameters in the above method include at least ―resistance, inductance, capacitance, junction capacitance, gate-source repair, __ship capacitor, miscellaneous capacitor, _Si Yu, non-polar _ sense version of electricity, and effective Gate length. The _size difference method in the above method further includes at least two or more using a progressive difference and a gap delay time between the connection points to determine the gap delay time. The square second further includes a time delay of mm to generate the progressive deviation parameter corresponding to at least two components and connection points. The above method and circuit design modification further include the progressive deviation parameter of the reward and the size difference rule. The progressive time difference includes the signal transmission delay of the circuit. The above method further includes obtaining the dimensional difference from a shape verification analysis of the -circuit. The method of integrating at least one size difference, progressive deviation parameters, and the difference between progressive deviations includes corresponding real time circuit descriptions of at least one size n progressive deviation parameter H progressive time difference. The continuous description is at least one image data and a text file. The system and method for manufacturing an integrated circuit described in this specification includes a method including at least one of 20052005132132 receiving a circuit design including a plurality of components and a connection point; receiving a difference between the size of the component and the connection point; Use the size difference to obtain the number of progressive deviations in the component and the connection point, where the deviation operand contains one or more difference information that can characterize at least one or more components and the connection point; use at least one size difference and the offset Different parameters to generate the difference between the design and the design; and use the difference between the B to generate the biased parameters corresponding to the design. '

The system and method for manufacturing an integrated circuit described in this specification includes an integrated design and manufacturing method, which includes at least one or more circuit designs that receive a plurality of components and connection points; using a component and connection point size offset error, To achieve progressive modification of the component model and the connection point model, the modified component and connection point model are used to model the integrated circuit; the model is used to generate the time offset error information of the circuit; _ the time offset error information is used to generate the component And the offset error of the connection point; and the base component and the connection unit offset error to generate the size offset error rule of the component and the connection point. The system and method for manufacturing integrated circuits described in this specification includes an integrated design manufacturing method, which includes at least receiving on the _, including the Wei component from the connection, the electricity meter, the use of the component and the connection type, Based on the electric meter, the circuit model is generated, where the enhanced component and connection point model integrates at least one capacitance offset error and resistance offset obtained from component and connection point size offset errors. The error and the inductance offset = poor. The circuit is difficult to produce time offset error f; and the time offset error information is used to generate the details of the controllable ship element and the connection-like size error, which are combined at least one or more The capacitance offset difference, resistance offset error, and inductance offset error obtained from the time offset error information of the circuit model. The system and method for manufacturing integrated circuits described in the verification book includes a system, which includes at least one electronic processing method; and the prediction of at least one circuit design through the electronic square shot size iE '. Means of progressive deviation parameter and progressive time difference, wherein the deviation parameter includes one or more parameters, which can characterize at least one component and connection point of 30 200534132 or more; use the progressive time difference to predict the difference in circuit design size Means; and a means for correcting the circuit design by integrating at least one circuit design with a size difference, a progressive deviation parameter, and a progress time difference. The above-mentioned system further includes means for generating a circuit design model by using at least one size difference, a progressive deviation parameter, and a progressive time difference. The above-mentioned system further includes a means for enhancing the information of the model of at least one component and the connection point by using at least one size difference, a progressive deviation parameter, and a progressive time difference.

The above system further includes means for adding at least one size difference, progressive bias parameter, and progressive time difference to one or more route descriptions, wherein the route description has at least one image data representation and a text file representation. The above-mentioned system further includes a means for recharacterizing at least one element and the connection point by using at least one size difference, a progressive bias parameter, and a progressive time difference. The above-mentioned means for predicting the system further includes a means for taking advantage of the size difference to obtain the progressive deviation parameters. The progressive deviation parameters in the above method include a progressive difference in circuit parameters that can characterize at least one element, connection point, and one or more connection point intervals. The circuit parameters in the above method include at least one resistance, inductance, capacitance, and gate. _Source capacitor, gate-drain capacitor, source-base capacitor, gate-base capacitor, and drain_base capacitor. In the above method A, the prediction size difference system further includes at least one or more means for determining the postponement time by using the difference in progressive time and reading and linking the related delay time. The method further includes a method of utilizing the separated gap time delay to generate the progressive deviation parameter corresponding to at least one element and a connection point. The method of modifying the system further includes a method of finely progressive deviation parameters to generate the rule of the size difference. The circuit design correction of the above system towel further includes a means of measuring the progressive deviation parameter to generate the size difference rule. / The above-mentioned system further includes a means for obtaining the dimensional difference in the shape verification analysis of the -circuit. 31 200534132 The method for correcting the system further includes corresponding at least one dimensional difference, a progressive deviation parameter, and a progressive time difference to a physical circuit description The system and method for manufacturing an integrated circuit described in this specification, including a component, which Including at least one means for receiving a circuit design including a plurality of components and connection points; utilizing a corresponding size difference in the circuit design to predict at least one or more progressive deviation parameters and a difference in progressive time in the circuit, wherein the deviation The operand contains one or more difference information that can characterize at least one or more components and connection points; a means of using progressive time differences to predict the size difference of the circuit design; and using at least one of the integrated circuit design's size difference and progressive Φ bias Different parameters, as well as the difference in progressive time, to correct the circuit design. The system and method for manufacturing integrated circuits described in this specification include a machine-readable medium containing executable instructions that can be executed by a processing system, and its content includes receiving circuit design and utilization including plural components and connection points. Corresponds to the size difference of the circuit design to predict at least one progressive deviation parameter and progressive time difference in the circuit design, where the deviation parameter contains the difference information of one or more parameters, which can characterize at least one or more components and connections Point, use the progressive_difference to paste the size wire of the line design, and / or integrate up to J size differences in the line design, the progressive deviation parameters, and the progressive return to correct the line design. The system and method for manufacturing integrated circuits described in this specification includes a method including * at least-more than receiving-circuit layout including a plurality of components and connection points; receiving corresponding components and connection differences; using financial differences , Taking a progressive bias reading from at least one elementary phase and the center of the connection point, where the deviation parameter includes one or more parameter differences, which characterizes at least one or more components and connection points; and uses at least one More than one size difference and deviation parameter, at least one or more components and the difference in progressive time of the connection point. The method described above further includes the use of at least one size difference, a progressive deviation parameter, and a progressive time difference to generate a circuit design model. The progressive deviation parameter of the embodiment includes mapping the difference in size to the circuit layout. The above method further includes information of at least one component and the model of the connection point by at least one size difference, a progressive bias parameter, and a progressive time difference. The above method further includes adding at least one size difference, progressive deviation parameter, and progressive time difference to one or more line descriptions, wherein the line description has at least one image data representation and a text file representation. The above method further includes updating one or more of the relevant information in the case by using a tribute message including at least one size difference, progressive deviation parameter, and progressive time difference.

The above method further includes recharacterizing at least one element and connection point by using at least one size difference, a progressive deviation parameter, and a progressive time difference. The way to take the progressive deviation parameter in an embodiment is further included in the dimensional difference and the deviation parameter, forming one or more gamma energy relations, and / or directly using the functional relation to generate the dimensional difference. Bias parameter. In one embodiment, the progressive deviation parameters of the connection points include the progressive differences of the line parameters, which are [biochemical to>, more than, and each connection point, and the interval of one or more connection points. The parameters of an embodiment include at least one capacitor, resistor, and inductor. —The above method further includes the use of progressive time differences to determine the time between staleness, the domain segmentation element, and the residual_ganguo time. This method further includes the use of _separation of the closing time ^ late 'to generate materials, and the deviation parameters corresponding to the reduction of _ components and connection points. The method further includes using the sub-gap time delay to generate a connection point where the progressive deviation parameter is called at least ^ or more. The financial law also includes the generated ¥, and the deviation parameters to produce the control of the size difference. The manufacturing integrated circuit _ system and method described in this specification, including ―method, the pot spoon spoon is received by the person-including a lot of 7L pieces and the connection point circuit Design; Integrate at least one ', dagger 3 connection point size difference into the secret towel; reduce the shape and size to obtain at least' elements, and the connection discontinuity progressive deviation parameters, the deviation parameters of which exist in 2 or more pieces It is enough to characterize at least one component and the difference information of the link_electronic parameter. More than one can enter the deviation parameter information to achieve time analysis, and at the same time produce a progressive time difference. The method described above with 33 200534132 further includes generating inter-material results including m time differences. The above method further includes using a model that is at least available to the circuit. Size differences and progressive bias parameters to produce—

The progressive time difference in an embodiment includes a signal transmission delay in the circuit. The above method further includes obtaining the size difference from the shape verification analysis information of the circuit. The dimensional difference in the integration-embodiment includes the dimensional difference corresponding to the physical gamma description of a circuit. The film description-the embodiment of the entity description is at least-similar to the close image data representation and text slot table. The above method further includes at least-more than dimensional errors, bias parameters, and time differences to enhance at least-like Components, and Lai Guanguan information. • Component model information Contains additional one or more dimensional differences, bias parameters, and time-to-one or more circuit descriptions. The enhanced component model information includes the use of new information that contains at least one or more dimensional difference deviation parameters and time differences to replace the original circuit description in the case. The enhanced connection point model information includes recharacterizing the connection point by using at least one of the size difference, the bias parameter, and the time difference. : Taking the progressive deviation parameter in an embodiment further includes forming one or more functional relationships between the size difference and the deviation parameter, and / or determining the difference between the parameters, the difference can make use of the functional relationship, Use the dimensional difference directly to re-characterize at least one or more components and connection points. Taking the progressive deviation parameter in an embodiment further includes confirming one or more parameters that can be characterized to y, more than one element and connection point, and / or using one or more interpolation methods and confirmed parameters to The deviation parameters of the element and the connection point are formed, and the confirmed parameters can characterize at least one or more elements and the connection point. In one embodiment, the progressive deviation parameter of the connection points includes the progressive difference of the line parameters, which characterizes at least one or more connection points and the interval of one or more connection points. In one embodiment, the electronic parameters include at least one capacitance, resistance, and inductance. “34 200534132-The electronic parameters of the component include at least one or more of the following:“ source_base version ”,“ capture base ”capacity. In this case, the system and method for manufacturing integrated circuits described in this article include—integrated design and manufacturing services. It has received 3 to more than three circuits—receiving circuit equipment including multiple components and connection points; using a size of 1 Shift the error to achieve the progressive correction of the component view; · the size of the connection point spoon is determined to achieve the progressive correction of the connection point model; the modified component and the connection point model are used to generate a model of the integrated circuit; Signal delivery delay information; and the use of the signal to transmit the brief form of the Master's face card.

. The above method further includes segmenting the gap delay time between the components and the connection points, wherein the message, the transmission delay information includes the gap delay time; using the segmented gap delay time to generate a private decision of 1 yuan, and a thorough gap of I 彳The delay time generates a joint point offset error; and / or the generated 7L component offset frequency and the connection point offset frequency difference are used to generate a rule that can offset the component and the size offset error of the connection point. -The component offset error in the embodiment includes at least one or more progressive size differences and kinks in the circuit parameters. The more different this is, the more various components can be edited. In one embodiment, the joint point offset error includes a progressive size error:. The connection point offset error includes a circuit parameter_progressive difference. Wei hybridizes at least one connection fUX and one or more connection_intervals. The connection point offset error may also include at least one capacitance offset error, resistance offset error, and inductance offset error. The system and method for manufacturing an integrated circuit described in this specification include a system having at least one or more means for processing electronically; and a means for storing information through electronic means; receiving-including Xu components and connection points Means of circuit design and layout; means for receiving the size difference between the component and the connection point; _ the size difference is a means for gifting at least one component and the progressive deviation parameter of the connection point, wherein the deviation parameter includes one Or the difference of multiple parameters is poor, which can characterize at least one or more components and connection points; and predict the difference in progressive time of at least one or more components and connection points, and at least one of the dimensional differences and bias parameters . 35 200534132 The above-mentioned system further includes a method for generating a circuit design model by using at least one size difference, a progressive deviation parameter, and a progressive time difference. The above-mentioned system further includes a means for mapping the difference in size to the circuit layout. The above-mentioned system further includes a means for enhancing the information of the model of at least one component and the connection point by using at least one size difference, a progressive deviation parameter, and a progressive time difference.

The above system further includes means for adding at least one size difference, progressive deviation parameter, and progressive time difference to one or more line descriptions. The above system further includes using at least one size difference, progressive deviation parameter, and • Means of accumulating time difference information to update one or more related information parts in the circuit description file. The above-mentioned system further includes a means for recharacterizing at least one element and the connection point by using at least one size difference, a progressive bias parameter, and a progressive time difference. The above-mentioned system further includes a method for determining a gap delay time by using a difference in progressive time, and / or a method for dividing a gap delay time between components and connection points. The above-mentioned system further includes a means for using a gap time delay of 5 卩 as the yin to generate the progressive deviation parameter corresponding to at least one element and the connection point. : * 1 The above system further includes the means of using the generated progressive deviation parameters to generate rules to control the size difference. The system and method for manufacturing an integrated circuit described in this specification includes a device having a means for receiving a circuit layout including a plurality of components and connection points; a means for receiving a size difference between a corresponding component and a connection point; using the size difference, Means for obtaining progressive deviation parameters from at least one element and connection point, wherein the deviation parameter includes one or more parameter differences, which can characterize at least one element and connection point; and using at least one The above-mentioned dimensional difference and deviation parameters are used to predict the difference in progressive time of at least one or more components and connection points. The method of taking an embodiment further includes at least one or more means for forming one or more functional relationships between the dimensional difference and the number of deviation parameters 36 200534132; and directly using the dimensional difference and the functional relationship to generate the bias Means of different parameters. The above device further includes means for generating a circuit design model by using at least one size difference, a progressive deviation parameter, and a progressive time difference. The above-mentioned device further includes a means for mapping the difference in size to the circuit layout. The above-mentioned device further includes a means for enhancing the information of the model of at least one element and the connection point by using at least one size difference, a progressive deviation parameter ', and a progressive time difference'. The system and method for manufacturing integrated circuits described in this specification include a machine-readable medium Φ medium, which contains executable instructions and can be executed by a processing system, and its content includes a circuit design that receives a plurality of components and connection points. , Receiving the size difference between the corresponding component and the connection point, using the size difference 'to take the progressive deviation parameter from at least one component and the connection point, wherein the deviation parameter contains the difference information of one or more parameters, which can be characterized At least one or more elements and connection points, and / or a prediction of a progressive time difference of the at least one or more elements and connection points', which uses at least one or more dimensional differences and bias parameters. According to the system and method for manufacturing integrated circuits described in this specification, tea can be used with various force months b. Midnight circuits come to fruition, including programmable logic elements (丨) 1, such as vices (PLDS), such as field programmable logic arrays (iield programmable gate arrays φ (FPGAs)) 'Programmable array logic (programmable array logic (PAL)) components, electronic bites and flat. Memory components and standard component library components ceu7 ased devices), such as special application circuit (ASic). Other ways to implement the integrated circuit and method of manufacturing the integrated circuit include: a microprocessor with a memory, such as an EEPROM, an embedded microprocessor, firmware, software, and so on. Alternatively, the system and method for manufacturing an integrated circuit can be implemented in a circuit simulation separation, system element, neural logic, quantum element with a software library, and a U-processor of the above-mentioned mixed type of each unit. In addition, the basic component fabrication technology can also be used to provide many implementation options such as metal oxide semiconductor field-effect transistor (MOSFet) technology, such as complementary to oxide semiconductor (CMQS), double carrier technology, For example, emitter logic, polymer technology 37 200534132 (such as silicon dioxide conjugated polymer and metal conjugated polymer metal structure, etc.), and hybrid analog digital technology, and so on. It should be noted that, in different systems and methods, the constituent elements included can be computer-assisted anal devices, and are represented as behavior models of instructions or instructions of various computer-readable media. , Logic elements, transistors, layout shapes, and / or other characteristics. Circuits can be implemented in formats and objects including, but not limited to, formats that support behavioral model languages such as C, Verilog, and HLDL; formats that support register-level description languages such as RTL, and formats that support shape description languages, such as GDSII, ㈤S1II, ㈤Milk, CIF, MEBES, and any other combined styles and languages. Computer readable ages containing formatted data and / or instructions may include, but are not limited to, a variety of non-ship storage media such as optical, magnetic or semiconductor storage, as well as wireless optical or wire communication, and their hybrid square wire transmission. _ Formatted data and / or command carrier. Give _ speech 'buttons to transmit this recording format and / or age includes == transmission (upload, download, electronic_, etc.) and other through one or more_ brain ^^^ / 1ΊTP' FTP 'SMTP, etc. ) Computer network. When—the computer system is communicated by electricity ’the above-mentioned data and / or instructions of the various recorded systems and methods may be combined with a processing entity (e.g., one or more processors) to execute a program and other similar programs. The private case of Taoxin's private case has a private style and layout. Unless there is an explicit record in the manual, the "package text must be avoided" am # 二 封 括 and other similar semantic meanings. A conjunctive statement, not a Lai statement; it means a "combined item of wbeme" and all related items "including but not limited to". The embodiments of the system and method of integrated circuits are not meant to limit or exhaust the manufacturing of integrated circuits that have been uncovered. "Principle of the system and method of manufacturing integrated circuits by Gongben and its skills, methods, and methods . Anyone skilled in the art can modify and change the above embodiments without departing from the technical principles and spirit of the system and method for manufacturing integrated circuits. Therefore, the scope of protection of the rights of the system and method for manufacturing integrated circuits should be as listed in the scope of patents mentioned below. The various objects and operation methods disclosed above can be combined into other embodiments. These changes in the system and method of manufacturing integrated circuits can be completed in accordance with the detailed description above. The scope of the following cap patents is not to be construed __ manufacturing integrated circuit _ system and method disclosed in the manual, but should be included in the pulse _ the following towel please paste all the scope _ system and method of manufacturing integrated circuit. The following patents are decided by the patent fan, and are not the limitation of the rights and scope of the system and method for manufacturing integrated circuits disclosed in the present invention. The scope of the following patent applications discloses the system and method of manufacturing integrated circuits. This means, for example, when one viewpoint in the system is explained to be implemented by a machine-readable medium, the other viewpoint is also expected to be implemented by a chicken-readable medium. [Schematic description]; · ;. Figure A is a block diagram 1 () () A of the Integrated Design-Manufacturing Prs (IDMP), which contains a biased flow rate, It includes a deviation shape time prediction program 102 and / or a deviation time shape prediction program, according to an embodiment. Xin ®-B series-block diagram of integrated design process, which includes-deviation process, which is used in manufacturing integrated circuits, according to an embodiment. Fig. Is another block diagram of an integrated design process, which includes a biased flow, which is used in manufacturing integrated circuits, according to another embodiment. FIG. 3 is an InTime processes of a distorted shape, according to an embodiment. FIG. 4 is a block diagram of a time compensation program with an abnormal shape, which is applied to generate an abnormal signal to correspond to a connection structure according to an embodiment. The flow chart of the fifth series λ bias / time profile prediction program (In Ding Ruo prcesses), according to an embodiment. 39 200534132 Figure 6: Block diagram of the integrated m manufacturing process, which includes the time sequence diagram of the distorted shape and the prediction process of the distorted time profile for application in the integrated circuit manufacturing process, and the implementation of FIG. 5 example. Figure 1 shows an example according to an embodiment. Figure 8 is an example of an integrated design process program element / junction capacitor. Very Fig. Nine examples are not-modified transistor device model parameters, according to an embodiment. Figure 7 Series-Transistor Block of Component Model for Enhanced Integrated Design Process

FIG. 10A is a graph of the signal delay corresponding to the extreme length offset error of the transistor model of the integrated design process, according to an embodiment. FIG. 10B is a graph of the saturation current corresponding to the extreme length deviation of the transistor model of the integrated design process, according to an embodiment. Figure 10 is a cross-sectional view of the connection point model of the integrated design process. According to a real figure, the connection of the 12 series-the integrated design process is Lai Xingqi—the scale offset error corresponds to the connection perturbation M at -d. Graph of percentage of size, go to Example. FIG. 12 is a graph showing the connection of Lai-type oscillation-capacitance offset error of the -I combined ☆ calculation process program corresponding to the percentage of the connected perturbation Δ1 at the -t dimension, according to an embodiment. FIG. 14 is a graph of the normalization time delay corresponding to the connection point model of the integrated correction process procedure as a percentage of the connection perturbation Ad at a d size, according to an embodiment. Figure 15-8, item 15 3, 1] Fifteen (: Department-structure diagram of the connection point after the extraction of deviation parameters) according to an embodiment. Figure 16 is a flowchart of an extrapolated extraction process, The modified parameters used to obtain the modified connection points are according to an embodiment. Figure 17 is a block diagram of a polygonal connection point according to an embodiment. Figure 18 is a computer that controls the integrated design process. System diagram, according to an embodiment. 40 200534132 In this diagram, the same figure number represents the same or substantially the same object or action. In order to clearly identify each special sight or action, when the object first appears , A mark will be attached below the figure number. (For example, the object 102 represents that it was first discussed and explained in Figure 1.) [Key component symbol description] 1210 Normalized capacitance offset error AC 1220 Connection point perturbation △ ( 1310 Normalized capacitance offset error AC 1320 Connection point perturbation Z \ t 1410 Normalization time delay 1420 Connection point perturbation △ (! 10 Circuit design program 100B Integrated design process block diagram 100A Integrated design process Cheng 101 Deviation process 1010 Signal delay 1012 Saturation current 102 Deviation shape time prediction program 丨 1021 Deviation shape time prediction program 1020 Gate length offset error 104 Deviation time shape prediction program 1100 Connection point model 1102 Metal wire 1104 Requirements 1112 connection Layer 12 circuit layout program 1200 graph 122 function block 123 function block 124 function block 200534132

125 Function block 1300 Graph 14 Time analysis program 1400 Graph 142 Function block 143 Function block 144 Function block 145 Function block 15 Design flow 1500C connection point structure 1500B connection point structure 1500A connection point structure 1502 Metal power grid 1504 Metal power supply wire 1506 through-hole 1510 first adjacent structure 1520 second adjacent structure; 1530 change area 1600 extrapolation program flow chart 1610 function block 1614 function block 1616 function block 1700 block diagram of polygonal connection point 1701 first interval 1702 second interval 1703 Third section 1704 Fourth section 1750 Part of the original non-polygonal connection point 1800 Computer system that controls the integrated design process 42 200534132

1801 Bus 1802 Central Processing Unit 1804 Volatile Memory 1806 Non-volatile Memory 1808 Optical Storage Element 1814 Pointing Element 1816 Optical Signal Conversion Element 20 Shape Verification 200 Integrated Design Process Procedure 22 Resolution Enhancement Technology Procedure 24 Process Procedure 25 Manufacturing Process 402 Database replacement format ^ ☆ Replacement file 404 Technical file 406 Standard parasitic delay grid h, 408 △ J file 410 appearance K ^ number 412 \ tree SPEl · · file 600, combined; leaf process program 60? Electrical design 604 局 Bureau 〇06 Physical circuit description 608 Original unit database 610 Original connection point database 612 Generation of electronic circuit model 614 Delay calculation 616 Dynamic time analysis 618 GDSII 620 RET 43 200534132 622 Modified GDSII 624 Fabrication mask 626 Wafer development 700 Electrical Crystal 702 Junction end 704 Polysilicon end 710 Gate 802 Base plate 804 Source region 806 Drain region 808 Empty region 810 Gate 900 Element model parameters

Claims (1)

200534132 10. Scope of patent application: 1. A biased design method in integrated circuit manufacturing process, including: A circuit design including a plurality of components and connection points, which uses the size difference in the circuit to predict at least one of the circuit designs The progressive bias parameter and the progressive time difference, wherein the bias parameter contains one or more information that can characterize at least one component and the parameter of the connection point 'means to use the progressive time difference to predict the difference in circuit design size and use integration At least one of the circuit design has a difference in size, a progressive deviation parameter, and a difference in progressive time, so as to correct the circuit design. 2. A bias design method in an integrated circuit manufacturing process as described in item 1 of the scope of patent application, which further includes using at least one of the size difference, the progressive bias parameter, and the progressive time difference to generate a The model of the circuit design. 3_ As described in item 1 of the scope of patent application—a biased design method in the integrated circuit manufacturing process, which further includes at least one size difference, a progressive bias parameter, and f, a time difference to enhance at least Information about a component and the model of the connection point. 4 · As described in the scope of patent application 1__ A biased design method in the integrated circuit manufacturing process, which further includes adding at least one size difference, progressive bias money :, and the progressive time difference to one or more In the line description, the line description has at least one image data representation and a text file representation. 5. As described in Item 丨 of the patent application—a biased design method in the integrated circuit manufacturing process, which further includes the use of information including at least one size difference, a progressive bias parameter, and a progressive time difference ' To update one or more of the relevant information in the line description. 6. As described in item 1 of the scope of patent application-a biased design method in the integrated circuit manufacturing process, which further includes at least one size difference, progressive bias parameters, and progressive time difference to recharacterize At least one component and connection point. 7 • As described in item 丨 of the scope of patent application-a kind of biased design method in the integrated circuit manufacturing process, wherein the prediction method further includes the use of dimensional differences, and the progressive bias parameters are taken from at least one component and the connection point . 45 200534132 8. A biased design method in the integrated circuit manufacturing process as described in item 7 of the scope of patent application, wherein the method includes correspondingly matching the dimensional difference to the circuit design. 9 'As described in item 7 of the scope of the patent application, a biased design method in an integrated circuit manufacturing process, wherein the selection method further includes at least one or more functions to form one or more functions between the size difference and the bias parameter. Sexual relationship; and directly using the difference in size and the functional relationship to generate the bias parameter. 10. A bias design method in an integrated circuit manufacturing process as described in item 1 of the scope of patent application, wherein the progressive bias parameter includes a characteristic that can characterize at least one component, a connection point, and a plurality of connection points. Progressive differences in circuit parameters for intervals. 11. A biased design method in an integrated circuit manufacturing process as described in item 1 of the scope of the patent application, wherein the circuit parameters include at least one resistor, inductor, capacitor, and junction capacitor 'gate, source capacitor, and gate Drain Capacitor, Source-Base Capacitor, Gate-Base Capacitor, Drain-Base Capacitor, and Effective Gate Length. 12. As described in item 1 of the scope of patent application-a biased design method in the integrated Wei process, wherein predicting the size difference further includes using the difference in progressive time to determine the gap delay time; and separating the component and the connection point This gap delay time. : 13 · As described in the application of Patent No. ㈣ 帛 12-a bias design method in the integrated circuit manufacturing process, further including utilizing the gap time delay of the separation to generate the progressive bias parameter corresponding to at least one component And connection points. 14. As stated in Item 1 of the stated patent—a method of partial variation in the process of integrated circuits, wherein the circuit &amp; ten correction further includes using the predicted progressive deviation parameter to generate the size difference rule . 15. The method of deflection meter in integrated circuit manufacturing as described in the application section, wherein the difference in progressive time includes the signal transmission delay of the circuit. The described method is a deflection meter in the integrated circuit manufacturing process, which further includes obtaining the dimensional difference from the shape verification analysis of the circuit. Biased design method in bulk circuit manufacturing process, 46 200534132 The method of integrating at least one size difference, progressive deviation parameter, and progressive time difference includes corresponding at least one size difference, progressive deviation parameter, and progressive time difference to one The circuit description of the entity. 18. A 5-5 method of deviation in the integrated circuit manufacturing process as described in item π of the patent application scope, wherein the entity description is at least one image data and a text file. 19. A biased design method in an integrated circuit manufacturing process includes: receiving a circuit design including a plurality of components and a connection point; receiving a circuit corresponding to the component and the connection The size difference of the points; using the size difference to obtain the progressive deviation parameter in the component and the connection point, wherein the deviation operand contains one or more difference information capable of characterizing at least one or more components and the connection point; using at least one Dry size difference and bias parameter to generate the progressive time difference of the design 'and use the time difference' to generate the bias parameter corresponding to the design. 20 · Integrated design process method to apply to the production of a product A circuit including: receiving a circuit design including a plurality of components and a connection point; using the component and connection point size offset errors to achieve a progressive correction of the element j model and the connection point model; using the modified component and the connection point model To model the integrated circuit; use the model to generate the time offset error information of the circuit; use the delta time offset error information to generate component and connection point offset errors; and use the 7C component and the connection point offset Error to produce component and connection point size deviation error rules. ° Ten manufacturing methods to apply to produce a integrated circuit, which includes: receiving a circuit design including a plurality of components and a connection point; using a 7L piece and a connection point model that are strong, called the enhanced component and the word Miscellaneous ^ ㈣ 寸 寸 寸 二 寸 整合 Integrates at least one or more of the electric power from components and the size of the "ridden electricity. Shift error, resistance bias ore difference, and inductance bias 47 200534132 shift error and use this circuit model to generate time bias The shift error information uses the time shift error information to generate a controllable rule. The rule fits at least one capacitor offset error obtained from the message of <size error, and the residual time = the time from the circuit model. Offset error information _ „Take the left and offset #rank, and the inductance offset error. 22 · —A system for manufacturing integrated circuits, which includes: means for electronically processing and storing radio signals; means for receiving a circuit design including many components and connection points; Use the size wire of the corresponding design to pay at least-the progressive deviation of the road series to count the number of progressive time I, the number of partial necks of the towel contains one or the parameters of the company: it can be characterized by at least one or more Components and connection points; means for predicting circuit design size differences using progressive time differences; and means for correcting circuit design by integrating size differences, progressive deviation parameters, and progressive time differences of at least one circuit design. 23. The system for manufacturing an integrated circuit as described in one of the 22nd scope of the patent application, which further includes the use of at least one of the size difference, the progressive deviation parameter, and the time difference to generate a model of the circuit design. means. 24. The system for manufacturing an integrated circuit as described in item 22 of the scope of the patent application, which further includes using at least one of the size difference, a progressive deviation parameter, and a progressive time difference to enhance at least one of the component and the connection point. Means of model information. 25. The system for manufacturing an integrated circuit as described in item 22 of the scope of the patent application, which further includes a means for adding at least one of the size difference, the progressive deviation parameter, and the progressive time difference to one or more of the circuit descriptions, The line description has at least one image data representation and a text file representation. 26. The system for manufacturing an integrated circuit as described in item 22 of the scope of patent application, which further includes using at least one size difference, a progressive deviation parameter, and a progressive time difference to re-characterize at least one component and the connection point. means. 48 200534132 Scope Item 22—The Secret of Manufacturing Integrated Circuits, which is used to predict the reason and also includes a means to use the dimensional difference to get the progressive deviation. 28. If the scope of the patent application is No. 22 ☆ The system of integrated circuit of Bei 7 乩, in which the progressive deviation parameter is already within the progressive difference of the circuit parameter, and the left side "〃," will sexualize at least one component, Junction point, and one or more junction point intervals. 29. The system of the integrated circuit described in the manufacturing method described in item 22 of the scope of patent application, wherein the circuit parameter includes at least one resistor, thunder, thunder, pq Otani Gate-Source Capacitor, Gate-I Capacitor, Source-Base Capacitor Base Capacitor, and Non-Polar_Base Capacitor. 30. The system described in item 22 of the scope of the patent application; the system of the Ik integrated circuit described in iL contact person A, wherein the predicted size difference /, the hand lx t contains at least one or more progressive time Difference and the gap delay time between components and connection points to determine the gap delay time. The method further includes a method of utilizing the separated gap time delay to generate the progressive deviation parameter corresponding to at least one element and the connection point. 3 丨. As described in the application note «Item # 1—Manufacturing the amount of circuit, the means for predicting the size difference of the cap, and the means for separating the gap delay time are included. 32. The system for manufacturing an integrated circuit as described in item 31 of the scope of patent application, further comprising a means for utilizing the separation delay time of the separation to generate the size difference. 33. As described in item 22 of the scope of the patent application-a system for manufacturing integrated circuits, wherein the means for amending the system further includes a means for generating the rule of the size difference by using the predicted progressive deviation parameter 0 34 · Ru Shenqing The secret of manufacturing integrated circuits is described in item 22 of the patent scope, which further includes a means of using the shape deviation error analysis of the circuit design to obtain the size difference. 35. The system for manufacturing an integrated circuit as described in item 22 of the scope of the patent application, wherein the hand to modify the system * k further includes corresponding at least one of the size difference, the progressive deviation parameter, and the progressive time difference to the A physical description of the circuit. 36. —A device for manufacturing an integrated circuit, comprising: means for receiving a circuit design including a plurality of components and connection points; 49 2005341.32 using the corresponding size difference in the circuit design to predict this characteristic of at least one or more components in the circuit And the difference information of the connection points; at least one of the circuit design using the progressive time difference to predict the size difference of the circuit design, the size «, progressive deviation to correct the circuit design. Difference between μ objects ’37: == The machine-readable interface of the instruction, when executed by an operating system, will receive multiple 7L pieces of package S and the circuit design of the connection point; Use the size difference corresponding to the circuit design to predict the time difference of at least one it number in the circuit design 'where the deviation parameter contains the difference of one or more parameters', which has at least one or more components and characteristics Point; using the progressive time difference to predict the size difference of the line design; and using the integrated line 5 to account for at least one of the size difference, the progressive deviation parameter, and the progressive time difference to modify the line design. A method for manufacturing integrated circuits that includes one or more functional relationships between the deviation parameter and the size offset error of at least one connection point, and directly corresponds to the circuit being received. a takes into account the progressive deviation parameter of 'JL less than one connection point', where the deviation parameter contains the difference information of one or more electronic parameters, and its inclination connection point. 39 · -A method of manufacturing an integrated circuit, which includes one or more functional relationships between at least one size offset error and one or more predefined information of electronic parameters, and directly generates corresponding correspondences. In the design of the circuit, the progressive deviation parameter of at least one connection point, wherein the deviation parameter includes difference information of the electronic parameter, which can characterize the connection point. 40 · —A method of manufacturing an integrated circuit, which includes using one or more functional relationships between the deviation parameter and a dimensional offset error of at least one component to directly generate at least one component in a corresponding circuit design that is received The progressive bias parameter, wherein the bias parameter contains difference information of one or more electronic parameters, which can characterize the component. 41. A method of manufacturing an integrated circuit, comprising using one or more functional relationships between at least one dimension offset error between the component and 50200534132 and one or more pre-defined information of electronic parameters to directly generate a correspondence. In the received circuit design, the progressive deviation parameter of at least one element, wherein the deviation parameter contains difference information of the electronic parameter, which can characterize the element. 51