TW200427858A - Atomic layer deposition of high k dielectric films - Google Patents

Abstract

A method of processing a semiconductor substrate includes reacting in a reactor a first reactant gas, evacuating the first reactant gas from the reactor, reacting a second reactant gas, and evacuating the second reactant gas. The reacting of the first reactant gas reacts the first reactant gas with an exposed surface of the semiconductor substrate in a reactor to convert the exposed surface into a solid mono-layer. The reacting of the second reactant gas reacts the second reactant gas with the solid mono-layer in the reactor to convert the solid mono-layer into a gaseous compound. The evacuating of the second reactant gas also evacuates the gaseous compound from the reactor.

Description

200427858 玖 发明, invention description related applications This application claims U.S. Provisional Application No. 60 / 396,723 filed on July 19, 2002 and U.S. Provisional Application No. 60 filed on July 19, 2002 / 3 96,745 benefits and priority, both of which are incorporated herein by reference in their entirety. This application is about PCT Patent Application Proceeding No. PCTUS03, filed under the title of Method and System for Atomic Layer Removal and Atomic Layer Exchange on June 23, 2003 / 1 99 82 (Acting Case No. FP-7 1 606-PC / MSS), which claims the benefit of US Provisional Application No. 60/3 9 1,011, filed on June 23, 2002, will The full text of this disclosure is hereby incorporated by reference; and PCT Patent Application Serial No. PCTUS03 / 1 9984 (Acting Case No. FP-7 1 606-1-PC / MSS) filed on June 23, 2003. , Which claims the benefit of US Provisional Application No. 60 / 391,012, filed on June 23, 2002, the disclosure of which is incorporated herein by reference in its entirety. [Technical Field to which the Invention belongs] The present invention relates to the field of semiconductors. More specifically, the present invention relates to a method for forming a high dielectric constant box and a capacitor insulator using an atomic layer exchange and removal method. (2) (2) 200427858 Future generations of semiconductor devices will require thin dielectric films for metal oxide stone (MOS) conductors and capacitor dielectrics. When the oxide film shrinks, the tunneling leakage becomes noticeable and limits the useful box oxide range to about 1.8 nanometers or more. High-dielectric-constant ("high-k 氧化物") metal oxides have been considered as possible alternative materials for silicon oxide (with a dielectric constant k of about 3.9), providing box electrodes with high capacitance but without compromise in leakage Dielectric material. Reports of metal oxides have been proposed, such as oxidation donations (Hf02) with a dielectric constant of about 20, oxidation pins (Zr02) with a dielectric constant of about 20, and silicic acid Hf and Zr. However, the manufacturing techniques of the prior art (such as chemical vapor deposition (CVD)) are gradually unable to meet the requirements for forming these advanced films. Although the CVD method can be adapted to provide a conformal film with improved step coverage, the CVD method often requires high processing temperatures, resulting in the incorporation of high impurity concentrates and poor precursor or reactant application efficiency. For example, one of the obstacles in manufacturing high-k- box dielectrics is the interface silicon oxide layer formation during C V D processing, as shown in Figure 1. The problem of interfacial oxide growth for cartridge and capacitor dielectric applications has been widely raised in the industry. This problem has become one of the major obstacles to the provision of high-k materials in the manufacture of advanced devices. Another hindrance is the limitation of the prior art CV: D method for depositing ultra-thin films (typically 10 angstroms or less) for high-k 値 box dielectrics on crystalline silicon substrates. Atomic layer deposition (ALD) is an alternative to the traditional CVD method to deposit very thin films. ALD has many advantages over traditional C V D technology. A L D can be performed at a lower temperature, which is compatible with the industrial trend of (3) (3) 200427858 low temperature, has high precursor application efficiency, and can produce homomorphic thin film layers. More advantageous is that ALD can control the film thickness of the atomic size, and can be used in "nano engineering" composite films. Therefore, further development in ALD is highly hoped. SUMMARY OF THE INVENTION Therefore, the object of the present invention is to provide a method and a system for manufacturing a transistor with improved performance, which are formed on a semiconductor device and a wafer by an atomic layer deposition method and a removal method. membrane. In one aspect of the present invention, a method for forming a high-k 値 dielectric film on a substrate surface is provided, which comprises reacting a first reaction gas with an exposed semiconductor substrate surface in a reactor to convert the exposed surface into A solid single-layer 'evacuated reactor's first reaction gas, reacting the second reaction gas with the solid monolayer in the reactor to convert the solid monolayer into a gaseous compound, and evacuating the reactor's second reaction gas and Gaseous compounds. The exposed surface of the semiconductor substrate is a compound composed of a metal, silicon, germanium, and an oxide of any one of the two-element semiconductors formed from the group II and the group v. In a specific embodiment, a compound of the first reaction gas system is composed of any one of water vapor, methanol, ethanol, propanol and butanol, and a compound of the second reaction gas system, It is composed of any one of C1F3, BF3, BC13, NF3, NCh, HF, HC1 'fluorine and chlorine. In another specific embodiment, the first reaction gas includes a radical-containing compound and the second (4) (4) 200427858 reaction gas includes a halogen-containing compound. In still another specific embodiment, the first reaction gas includes trimethylamine (A1 (CH: 5) 3) and the second reaction gas system ozone (〇3). Additional suitable gaseous reactants include MP A (methylpyrrolidine alane), modified TMA (methylpyrrolidine TMA, ethylhexahydropyridine TMA), DMAH (dimethyl aluminum hydride A1 ((CH3) 2) ) η), modified DMAH (methylpyrrolidine dimethyl aluminum hydride, methyl hexahydropyridine dimethyl aluminum hydride, ethyl hexahydropyridine dimethyl aluminum hydride), TEMAT (Ti [N (CH3) C2H5 ] 4), PEMAT (

Ta [C2H5N (CH3)] 5), TEMAHf (Hf [C2H5N (CH3) 2] 4), TEMAZr (Zr [C2H5N (CH3)] 4), TDMAHf (Hf [N (CH3) 2] 4) 'TDMAZr ( Zr [N (CH3) 2] 4), TDEAHf (Hf [N (C2H5) 2] 4), TDMAZr (Zr [N (C2H5) 2] 4), cocktail-type BST source (Ba (heptanedione acid tetra) Methyl ester) 2, Sr ((heptane diketo tetramethyl ester) 2) and cocktail STO sources (Sr (heptane diketo tetramethyl ester) 2, Ti (i-OPr) 2 (heptane di Tetramethyl keto acid) 2). In another aspect of the present invention, the structure includes a deoxidized substrate formed by removing at least one oxide monolayer using an atomic layer and using atomic layer deposition on the deoxidized substrate to form at least one dielectric A dielectric film formed by a single layer of a dielectric substance. In an aspect of the present invention, a transistor device is provided, which is composed of an emission region and a source region formed in a substrate, and is limited between the emission region and the source region. A deoxidation channel formed by removing at least one oxide monolayer using an atomic layer in a substrate, and a box dielectric formed by depositing at least one dielectric monolayer using an atomic layer on the deoxidation channel Mass thereof. Cartridge electrode may include a dielectric layer of a dielectric single number, wherein each dielectric layer (5) 200 427 858

The single layer contains a compound, which is A1203, Ti02, Hf02, Ce02, Zr〇2, Ta205 and Li, Be, N &, Mg, K, Ca, Sc, V, Cr, Mn, Fe, C0, Ni, Cu, Ga, Ge, Rb, Sr, Y, Nb, Mo, Tc, Pd, Ag, Cd, In, Sn, Sb 'Cs, Ba, La, W, Re, Pt, Au, Hg, T1, Pb, One of the oxides of Bi, Po, Fr, Ra, Ac, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Th. The transistor may further include a barrier metal film formed on the box dielectric.

In another aspect of the present invention, a capacitor device is provided, which is formed by a trench formed in a substrate and a deoxidized surface of a stack formed on the substrate, and using an atomic layer to remove at least one oxide monolayer And a capacitor dielectric formed by depositing at least one dielectric monolayer on the deoxidized surface using an atomic layer. The capacitor may include a barrier metal layer formed on the capacitor dielectric. The barrier metal film includes several metal film single layers formed by an atomic layer deposition method, and each metal film single layer is a compound, which is composed of titanium nitride, giant nitride, tungsten nitride, and titanium tungsten nitride. Consisting of giant tungsten nitride, tungsten aluminum nitride, titanium silicon nitride, giant nitride silicon nitride, giant nitride sand, tungsten nitride sand, and one of the conductive oxides of Ru, Rh, Os, and Ir. [Embodiment] The present invention provides a novel method and system for forming a dielectric insulator for a semiconductor transistor and a capacitor using an atomic layer deposition method and a removal method. Future increases in transistor performance will require increasing the dielectric constant of the box insulator (6) 200427858 and possibly improved box electrode materials. In one embodiment, the conventional Si02 insulator is made of nitride (for example, an advanced metal insulator or nitride · oxide advanced insulator number insulator (such as Al203, Ce02, Hf02 and Zr02, and Zr silicate ( Hf, Y, and Zr plus SiOx), and aluminates of La and Zr (Hf, Y, La, and Zr plus StriP3 instead of the box electrode device. Will be used for box electrode electrode doped (more) or more Si-Ge is covered with a metal sand (such as Cozy; in another specific embodiment, a multilayer or Sage metal box electrode (such as tin, giant, WIN and W) and an electrode (such as Pt, Ru, Rue) , Ire, Ni, Ti, Mo, and Ti. Because the size of the circuit features is reduced, the thickness of the box insulator insulator must also be reduced. In various thin insulators, it is desirable to directly tunnel. In addition to tunneling, current may be Leakage current through the body or capacitor insulator. In order to avoid this phenomenon, the equivalent oxide thickness (EAT) of the material is maintained greater than 20 △ constant is greater than 3.9-8. It is necessary to have a low leakage current (amperes per square ampere) and a high voltage collapse strength Dielectrics. The boundary between insulating materials It should have a low-density trap for electrons. High-performance transistors and capacitors need a box insulator with a dielectric constant EAT of less than 15 △. The box leakage current across the dielectric potential should be maintained at less than ] r-9-In the examples, S, i3N4) and oxygen and high dielectric constant or Hf, Y, such as Hf, Y, Aloex) and impurity polycrystalline pan Nisei) plus multiple layers are similar to a single bimetal box Dielectrics and capacitors may never occur without the insulation of the box pole. The dielectric is less than 1 centimeter and other recharge holes or 1 volt ampere greater than 10 and i quality. (7) 200427858 with Gap energy Egg is greater than 5eve. Many candidate dielectrics are listed in Table 1.

^ 10 ~ (8) 200427858 Table 1-Dielectric candidate list Dielectric constant A 1 2 〇3 8-12 (Ba, Sr) Ti03 * 200-300 B ea 1 2 〇4 8.3-9.4 C e 0 2 16.6-26 C hef 4 10-20 E qu al 3 22.5 Hf02 26-30 H f- S i 1 icate 11 L a2 〇3 18-20.8 L ea 1 3 23-28 L asso 3 30 M ea 1 2 〇3 8.3-9.4 N oda 13 22.5 Palo3 25 Si3N4 7 S ma 113 19 S trip 3 * 1 5 0-25 0 Ti02 86-95 Y2O3 1 4 Y203-Zr02 30 Zr02 22.2-28 Zr-Al-0 12 -18 Zr-S i1i c at e 11-12.6 (Zr, Sn) Ti04 40-60

* Indicates that with BST, Strip3 reacts with Si at temperatures greater than 800 ° C. It also indicates that Ta205 is incompatible with Si and therefore requires a Si3N4 barrier layer. (9) (9) 200427858 Preferred dielectric materials include Al203, Hf02, Hf-silicate, Zr02, Zr-silicate, Hf-aluminate, and Zr-aluminate . A fixed, electrical hole, and electron trap is formed in alumina ai2o3. During sedimentation, water-based alumina ai2o3 films (for example, formed by water vapor and TMA, A1 (CH3) 3) exhibit two types of pores and electron replenishment P wells. However, after a nitrogen annealing cycle of 80CTC for 30 minutes, the electron recovery trap almost disappeared. Residual pores make up the well. The exposed Si surface tends to oxidize itself in the air and form a thin film called a halide oxide. The silicon oxide surface is called a hydrophilic surface. From the perspective of leakage and other electrical characteristics, the inferior oxide is a poor quality insulator, so it is usually removed. In order to remove oxides, HF is typically processed on the film, and this processing leaves the Si surface terminated with hydrogen atoms and forms a surface called a hydrophobic surface. It is not easy to form a water-based alumina A 12 0 3 film on the hydrophobic S i surface for growth. This growth must be completed by incubation, or begun with an incubation period before the deposition of oxidized deposits begins. For example, using the ALD method described below, about 15 ALD cycles are required before the aluminum oxide Al203 film begins to grow. H2O-based alumina ai2o3 film is usually

Si + Al (CH3) 3 + H20—Si + Al + 0 + 0H- + CH4 (1) —Si (0H) + Al (0H) + A10 + ··· (2) Provides reaction chemistry. Such an AD deposit of 10 angstroms or less of an alumina film is not possible because the deposit during the incubation period has grown to this thickness before the actual alumina begins to grow. In addition, an aluminum oxide film thicker than 40 angstroms has a tendency to leak electricity. -12- (10) 200427858 Once the incubation period is completed, the chemical properties of alumina growth are as follows: 2A1 (CH3) b + 3 H20 ~ > AI2O3 + 3 CH4 (3) For example, 'at about 3 0 0 ° C In the temperature range, monolayer formation is performed using trimethylaluminum a 1 <) 3 (also referred to as TMA) and water vapor as a precursor, for example, 'the atomic layer deposition method ADL as discussed below). Each ALD cycle adds about 0.85 delta dielectric material. But in the ALD method with tmA (Geming) plus water as the precursor, the reaction basically also occurs: A1 (CH3) 3 + 3H20- > Al (OH) 3 + 3 CH4 (4) left to include some ai (oh3) 3 dielectric film. Al (OH3) tends to weaken the dielectric film characteristics. H2O-doped alumina ai2o3 film peeled off, probably due to pinhole defects in the surface. Alumina films grown using TMA and ozone have more specific advantages than water-based alumina films. At the time of sedimentation, the Al 2 O 3 film, which is dominated by 0 3, is a pure oxide, does not have 0 η-bond and is not subject to any warranty. There is little or no hysteresis in the C-V curve and less carbon is produced in the membrane. These films exhibit improved leakage current characteristics and produce an oxygen-deficient A1203 layer. The same alumina α2ο3 film can be used on different materials and structures. Usually 2Α1 (CH3) 3 + 〇3 — ΑΙΟ203 + 3C2H6 (5) provides the reaction chemistry of the aluminum oxide A12〇3 film, which is mainly composed of 〇3. Aluminate (including A1203), Hf02 and silicate form a good body. The above-mentioned ozone-based precursor method is used to suppress the ch3 length at the dielectric of the cartridge (at a time, three-dimension below three-three-degrees may be the main temperature of oxidation, and does not cause the formation of 〇 ΗΓ of 13 (11) 200427858 in the insulator. The layer-by-layer atomic layer deposition growth method provides excellent coverage over a large area and provides excellent step coverage. The main atomic layer deposition method uses a layer with a low thermal budget (for diffusion in the structure formed first) ) And build a body layer by introducing a small amount of impurities. Low thermal budget minimizes the growth of interface oxides, further discussion. Introduce the reaction gas into the reaction chamber to evenly distribute the gas via the so-called shower. You can use a variety of In the method known in the art, in the method mainly based on ozone, it is preferable to use a shower head type reactor to drive the object. In US Patent Nos. 6,5 7 9,3 72 and 6,5 73,184, two kinds are suitable. Examples of carrying out the reaction chamber and system of the present invention. In explaining the methods and structures described herein, ALD is often used to illustrate the atomic layer deposition viewpoint of the method. In explaining the atomic viewpoint of the method, The ALR abbreviation is used, and the ALR abbreviation is often used when explaining the original idea of this method. An interface between the residual dielectric and the underlying semiconductor surface when a high-performance and very thin dielectric film is reached The possible source of this oxide of oxygen may be from the interfacial oxide formed during the deposition of the unremoved dysprosium oxide electrical film. If the dysprosium oxygen is removed (eg 'removed with HF just before the dielectric film is deposited) The electrical film method has its own source of oxygen to form interfacial oxidation such as' in the ALD method to produce an A: h03 film, from water or odor drive gas) to combine with the Si surface to form SiO 2. Interfacial oxides must be suppressed to achieve low EOT. The substrate of ozone is reduced in the structural insulation such as the following. Introduce the previous description Abbreviation layer removal sublayer intersection problem system. Or deposit the dielectric. Example oxygen (previously in order to minimize -14-(12) 200427858 interfacial oxides, so before depositing dielectrics, almost leaving less than 4 layers of oxide monolayer, preferably a single monolayer) or Complete removal of phyto-oxidants. In addition, the temperature is minimized in the method of depositing dielectric materials. However, this interface sand is completely inevitable, and tends to grow EOT 5 to 9 angstroms or thicker, and often grows on the thicker side. Reasons why it is not easy to grow high dielectric constant materials on the surface. The thickness of the formed halide oxide cannot be controlled, and it is not closely related to the history and processing of the semiconductor wafer of the present invention. Remove the hafnium oxide and replace it with an oxide of controlled thickness. Crystalline silicon that reacts with vapor or ozone at a predetermined temperature for a predetermined time will produce oxides with a controlled thickness. But this thickness is often too thick for high-performance dielectric applications. Therefore, it is applied by repeating the atomic layer removal (ALR) method described above, until almost all of the oxide monolayer is removed (leaving less than 4 layers, preferably one layer) or the thickness is completely removed before the dielectric deposition. The controlled oxide makes the thickness of the controlled oxide layer thinner. After removing or almost removing the halide oxide, an oxide layer is formed on the substrate. In a specific embodiment, the use of ozone and metals (for example, Hf amine or Hf (Ot-Bu) 4 in which Ot-Bu butoxy anion) as a precursor is performed at a temperature of about 3 50 ° C law. In this embodiment, the Hf02 layer is grown to about 80 angstroms, which has a very low leakage phenomenon. If 80 Angstroms is thicker than the target application, then the atomic layer removal method (ALR) described herein is used to remove it by a predetermined division. The thickness of gold-based organic ALD is too many times 15 * (13) (13) 200427858 Repeatedly applied to the HfO2 dielectric layer until a predetermined thickness is obtained. Although the oxidizing effect (with water or ozone) forms 5 to 9 Angstrom thickness of the interfacial oxide, but the formation of H 〇 2 A LD will not form the same thickness of the interfacial oxide of aluminum oxide. Therefore, by using the atomic layer removal method (ALR) ) Thinning or removing the oxide and replacing it with a controlled oxide, followed by thinning using atomic layer removal (ALR) as discussed herein, can be made thinner High-performance dielectrics are formed on the oxides. When forming high-performance box insulators or capacitor insulators, they have a high k 値 (representing a dielectric of about 10 or greater) with an EOT of less than 12 angstroms (that is, u nanometers). Dielectric constant) dielectric materials are preferred. Dielectric, so it is customary to form a thin hydrophobic SiO2 interface layer of less than 5 Angstroms (ie, 0.5 nm) on the surface of hydrophobic SiO2 that has been conditioned or HF-conditioned. Then use ALD technology to make The electrical material is grown on a thin SiO2 interface layer. As discussed herein, the present invention provides an atomic layer removal (ALR) method and system. The ALR method follows a continuous ALD step. It will have on the substrate surface The substrate of the membrane (such as oxidized oxide or oxide with controlled thickness) is placed in the reactor. The first reaction gas is introduced into the reactor and reacts with the first layer of the membrane to convert the first layer into a single layer Solid compounds. The second reaction gas is then introduced into the reactor to react with a single layer of solid compounds to form a gaseous compound and remove it from the reactor. It is best to use the present invention to remove one or more atoms on the surface of a wafer. In particular, this method can be used to remove oxidized oxides or oxides with controlled thickness, where the oxidized oxides or oxides with controlled thickness are any of the -16-(14) (14) 200427858 metals, silicon, germanium And from ΠI family The oxide of two-element semiconductors formed by Group V. In addition, the atomic layer removal method is the atomic layer removal method that terminates the sequence by itself.-This method can be used to remove the surface of crystalline silicon or other semiconductors before the deposition method. Any oxide on the surface. The present invention can be further used to reduce the thickness of the deposited conductive or dielectric film to the desired final film thickness. These are just some of the applications of the present invention. Many methods used to deposit dielectrics by ALD Uses an oxide that causes the precursor to react on it. Therefore, it is not desirable to remove all the oxides before depositing the dielectric. In this case, it is best to remove the halide oxide and control the thickness by Oxide instead. However, such controlled thickness oxides can be thicker than expected. Therefore, the oxide with a controlled thickness is almost removed by repeating the atomic layer removal step a predetermined number of times (leaves less than 4 oxide monolayers, preferably a single monolayer). The number of Alr repetitions depends on the thickness of the controlled oxide. A dielectric film is then deposited by ALD or other means. φ When a specific dielectric is required, such as a dielectric containing Ta205, it is desirable to insert a nitride film between the semiconductor material and the dielectric. In this case, the HF treatment or repeating the atomic layer removal step a sufficient number of times to remove all oxides completely removes the oxidized oxide or the oxide having a controlled thickness. The exposed semiconductor surface is then reacted with ammonia to form a nitride film with a controlled thickness. The nitride film can also be thicker than expected here. In order to make the nitride film thin, the controlled thickness of the nitride film is almost removed by repeating the atomic layer removal step a predetermined number of times (leaving less than 4 layers of nitride (15) 200427858 single layer, one or Two single layers are preferred, sufficient to act as a barrier layer. The number of repetitions depends on the thickness of the controlled oxide. The nitride surface reacts with a halogen-containing gas (such as fluorine). This reaction with (nitride film) will produce NF3 and SiF4 series gases' which become products, which can be removed from the reaction chamber). Control the reaction time ‘UV activation pulse time) and other factors (for example, temperature,)’ so that only a predetermined nitride thickness is removed per cycle (preferably with a layer). Those skilled in the art can routinely experiment with these variables. The number of repetitions of the ALR depends on the thickness of the controlled nitriding. Next, a dielectric film (such as a film of Ta205) is deposited by ALD or other methods. When forming a metal insulator metal (MIM) capacitor, the first metal system is directly deposited on a barrier metal film that can be formed of any metal, silicon, germanium, and a two-element semiconductor formed of a group V and a group V. The semiconductor substrate also includes any metal, silicon doped forms of two-element semiconductors formed in Groups II and V (often referred to as polycrystalline). In this case, atomic layer removal (ALR) treated with HF a sufficient number of times to remove all oxides completely removes any oxidized oxides or oxides with controlled thickness. A barrier metal film is deposited by ALD on the exposed semiconductor surface. The barrier film includes a compound consisting of titanium nitride, molybdenum nitride, titanium aluminum nitride, giant aluminum nitride, tungsten aluminum nitride, titanium nitride silicon, nitrided tungsten silicon, and Ru, Rh, Os. Among them, one of Ir and Ir is preferable. Then ALD or other on the barrier metal film. ALR is preferably Si3N4 (both (for example, pressure, 1 layer, etc.) to determine the thickness of this object, including a type III deposit, germanium and polycrystals, or repeating the steps followed by the barrier metal tungsten, nitrogen stone, nitrogen and other Method Shen-18-(16) (16) 200427858 accumulated dielectric film. Because the barrier metal film provides good electrical contact with the underlying semiconductor, it is treated as an electrode of a MIM (or MIS) capacitor; the same A dielectric film having a controlled thickness can be deposited in any manner on the substrate to be waited for. The film is then thinned to a predetermined thickness by the ALR method described below. In a specific embodiment of the present invention, it is more particularly to provide a A method for depositing a thin dielectric film on a substrate using atomic layer removal (ALR). According to the present invention, a substrate having a film deposited on the surface of the substrate is placed in a reactor. The film is typically composed of multiple atomic layers The first reaction gas is introduced into the reactor and reacts with the first layer of the membrane to convert the first layer into a single layer of solid compounds. The inert flushing gas is used to evacuate the excess of the first reaction gas from the reactor. The second reaction gas is then introduced into the reactor to react with a single layer of solid compounds to form a gaseous compound. Then the gaseous compound and excess second reaction gas are removed from the reactor. The second reaction gas is selected so that Chemical reaction with the original film. In this way, only one atomic layer will be removed. Repeat the above steps to remove the second, third and more layers of the film until the expected number of layers remains on the substrate The reaction gas is usually introduced into the reactor for a time sufficient to react with a single layer of the membrane (ie, the atomic layer). The ALR method of the present invention will now be described in more detail with reference to FIGS. 1-3. On June 23, 2003 PCT Patent Application Proceeding No. PCTUS 03/1 99 8 2 (Acting Case No. FP- 7 1 6 06-PC / MSS) filed in Japan on June 22, 2002 For the benefit of US Provisional Application No. 60/3 9 1; 01 1 filed on the date of Japan, the full disclosure of both (17) (17) 200427858 is incorporated herein for reference. Figure 1 is shown in .schema Base with film A deposited on substrate surface Although the three layers of film A are shown in FIG. 1 for the purpose of illustration, the number of layers pre-deposited on the substrate surface can vary widely depending on the particular application. The film A to be removed can have Any film type used, such as any box dielectric or capacitor dielectric or ceramic, including metal oxides, aluminates' silicates, nitrides, pure metals or silicon, germanium or group III and V An oxide of any one of the two-element semiconductors formed by the group. In FIG. 2, the first reaction gas B is reacted with the top layer of the film A to convert the top layer into a single-layer solid compound D. The first reaction gas B is a chemical reagent that converts the atomic layer of the film A into an early solid compound D, and this compound can be further reacted with the second reaction gas C, as described below. The selection of the first reaction gas B depends on the molecular composition of the membrane A. The first selected reaction gas B is preferably such that the formed single-layer solid compound D requires less energy than the next layer A below the single-layer solid compound D and the second reaction gas C (as shown below) (Described) further reaction to β. The reaction of the second reaction gas C with the solid monolayer D preferably requires less activation energy than that required for the second reaction gas C to react with the surface A below the solid monolayer D. Examples of the first reactive gas B precursor that can be used include, but are not limited to, ozone and ammonia. In Fig. 3, a single-layer solid compound D is then reacted with a second reaction gas C to form a gaseous compound E. The gaseous compound E formed is removed from the reactor in any suitable manner, such as by pumping with the aid of a flushing gas. In one example, the second reaction gas C corresponding to the converted single-layer solid compound D can be a halogen-containing compound. Examples of halogen-containing compounds include, but are not limited to, C1 F 3, B F 3, B C13 ·, N F 3,: N Cl3, HF, HC1, fluorine, and chlorine. · The above steps of this specific embodiment of the ALR method of the present invention can be summarized in the following equation: A (solid state) + B (gaseous state)-d (solid state) (6) D (solid state) + C (gaseous state) —E (Gaseous) 丨 (7) Steps (6) and (7) can be repeated until any desired number of layers of film A or the total number of layers is removed from the substrate. 4-6 illustrate another specific embodiment of the present invention. In FIG. 4 of the specific embodiment, the film or wafer surface is composed of a compound of two elements AB. For example, the wafer surface may include a film, or may include only crystalline silicon with or terminated with hydrogen (i.e., a hydrophilic surface) or a formed oxide (i.e., a hydrophobic surface) formed thereon. In this example, an atomic layer exchange method occurs. In Figure 5, the wafer is exposed to a gaseous precursor CD. Surface reactions and species exchange occur on the top layer of the wafer. In this example, the top layer is converted into a single-layer solid compound AD (see Fig. 6) with a surface reaction, and a gaseous compound CB is formed, which is removed or rinsed from the reaction chamber. The steps of this specific embodiment can be summarized in the following equations: AB (solid state) + CD (gaseous state)-> AD (solid state) + CB (gaseous state) (8) The method of the present invention can use many types of gaseous states Precursor or reactor, and part of the choice is based on the chemical composition of the membrane. Examples of additional gaseous precursors include (but are not limited to): MPA (methylpyrrole (19) (19) 200427858 alane), modified TMA (methylpyrrolidine tmA, ethylhexahydropyridine TMA), DMAH ( Dimethyl aluminum hydride A1 ((CH3〇2) Η), modified DMA Η (methylpyrrolidine dimethyl aluminum hydride, methyl hexahydropyridine dimethyl aluminum hydride, ethyl hexahydropyridine dimethyl aluminum hydride ), TEMAT (Ti [N (CH3) C2H5] 4), PEMAT (Ta [C2H5N (CH3)] 5), TEMAHf (Hf [C2H5N (CH3) 2] 4), TEMAZ r (Z r [C 2 Η 5 N (CH3)] 4), TDMAHf (Hf [N (CH3) 2] a), TDMAZr (

Zr [N (CH3) 2] 4), TDEAHf (Hf [N (C2H5) 2] 4), TDMAZr (Zr [N (C2H5) 2] 4), Cocktail BST source (Ba (heptanedione acid tetra) Methyl ester) 2, Sr ((heptane diketo tetramethyl ester) 2) and cocktail STO sources (Sr (heptane diketo tetramethyl ester) 2, Ti (i-ΟΡΟ 2 (heptane diketo acid) Tetramethyl ester) 2). As mentioned above, the atomic layer exchange method occurs between free radicals or molecules in the gas phase and molecules on the surface of the wafer. Many gaseous precursors can be diffused through the surface of the wafer by controlling many parameters. These parameters include temperature (e.g., for alumina, it is best to change between 200-400 ° C), pulse time (e.g., the time interval between reactions defined by the activation source (such as UV irradiation), It can be changed between 1 and 10 seconds), the chamber pressure (which can be less than 10 Torr is the best), the molecular size of the reaction gas, and the molecular selectivity during the reaction, all in order to avoid the multilayer atom exchange method. In another specific embodiment of the present invention, with reference to Figures 4-6, the atomic layer exchange method (ALR) is used to follow the atomic layer exchange discussed above. (ALEx). As discussed above with regard to Figure 4_6, according to the following equation 'Advanced (20) (20) The precursor can be modified in the manner shown in Figure 6 when the chamber under the AD drive in Figure 6 is proposed. Temporary r ~ [~ j 円 Uncover reaction of main δ 円 10) 200427858 Atomic layer exchange method was used to modify the chemical properties of the membrane surface: AB (solid state) + CD (gaseous state)-AD (solid state) + CB (gaseous state) (The gaseous precursor CD is first delivered to the reaction chamber. Once the gaseous substance is in the reaction chamber, the precursor is activated. As discussed above, activation occurs in various ways, such as with temperature, energy pulses, and the like Once activated, an atomic layer exchange process with the top layer of the membrane occurs, as shown, and the reaction chamber is flushed, so the gaseous product C Β formed is removed from the reaction chamber. The top layer of the membrane has now been converted to the compound AD, As shown in the figure, then the atomic layer removal method is performed to remove the single layer disposed on the film, as shown in Figures 7 and 8. In Figure 7 of this example, the gaseous front XY is selected, and the single layers AD and XY are selected. React and keep membrane AB (layer of AD membrane) from reacting with XY. When gas The state precursor XY enters the reaction, so that the precursor is activated. As discussed above, the precursor can be activated by energy pulses or other methods. PCTUS03 / 1, PCT Patent Application Proceeding, filed on June 23, 2003 No. 99 84 (Substitute No. FP- 7 1 60 6-Bu PC / MSS) explains the energy-assisted method. It claims that US Application No. 60 / 391,012, filed on June 23, 2002, and The entire benefit of US Provisional Application No. 60/3 96,743, filed July 19, 2002, is incorporated herein by reference in its entirety. In this example, the product system in the gas phase: 'AD (solid) + XY (gaseous)-DX (gaseous) + AY (gaseous) (reactions and formation of products DX and A Υ, and removed from the reaction chamber (21) 200427858 As shown in Figure 8. Therefore, the original atomic layer of the film is removed. Therefore, these steps can be repeated as previously provided in the exemplified example. The method and system for nitriding the giant layer are achieved to achieve the desired thickness. The material of the barrier electrode barrier layer. In order to pre-deposit on the surface of the barrier dielectric according to this embodiment of the present invention, the top atomic layer is converted into a single layer of molybdenum dioxide Ti02 layer and hydrogen fluoride ( (HF) Steam is fed into a giant (TiF) and water vapor, and its self-reaction method can be removed from the reactor to achieve or "deposit" a layer of TiN atomic crystalline silicon substrate. It is expected that the atomic layer removal method of the present invention can be removed. In another specific embodiment of pre-depositing or otherwise forming a film, a pre-deposited silicon dioxide (SiO 2) film can be formed on the top surface of the substrate to form a single layer of hydrogen 4 using hydrogen fluoride (HF) as the Forms gaseous state with solid hydrogen / oxygen Silicon silicon (SiF4) and evacuation. The method of the present invention can be used as an in-process method. For example, a dielectric film with a thick thickness (such as the thickness of 3 △) of the prior art has a sub-layer. The same is true to remove more period Many times t (TiN), and according to the present invention: The nitrided giant (TiN) is a TiN film that is relatively thicker than the TiN film deposited on the substrate. The introduction of ozone makes the TiN film (Ti02). Then the solid step The reaction forms a gaseous fluorinator to evacuate. This layer is cycled once. This method can be repeated to produce ultra-thin TiN films with a thickness. The number of non-T i N layers with any limit is limited to the crystalline silicon diodes that generate oxides. And the first reaction gas on the substrate. In silicon silicon (SiOH). The second reaction water vapor that can make VII silicon react, and it is deposited from the reaction chamber substrate by the square product technology. Thin limitation. With the method of the present invention-2a-(22) 200427858, a thicker dielectric film can be deposited on the surface of the substrate first (for example. Then, the layer of the electrical film can be removed using the atomic layer removal method described above). .Nothing about the number of layers that can be removed When a dielectric film with a thickness of 3 △ is required, the dielectric film layer with a thickness of 7 △ can be removed by repeating the steps, and the film with a thickness of 3 △ is displayed on the substrate. The atomic layer deposition method and the method of the present invention The division method has a wide range. For example, in other applications, the etching material of the present invention can be used to produce a photolithographic etching mask and improve the liquid crystal display. Before forming the box electrode, the original film thickness of the present invention can be used to reduce the final film thickness. And / or remove unexpected rough surface atomic layer exchange methods together with low temperature ALD high-k 値 to control the crystalline silicon-high & 高 dielectric interface. There is additional high-k 値 dielectric The application and benefits of high-quality nano-layers with multilayer films and inner surfaces of the film make the box insulator edge have more opportunities for unexpected interface replenishment wells. Therefore, the application form of the film after the atomic layer removal method is used. Another embodiment of the present invention provides an ultra-thin, for example, a silicon dioxide layer having a thickness of 9 angstroms. This is a considerable portion of the total thickness of advanced insulator dielectrics. When the final thickness is only 12 angstroms, then the allowable thickness of the dioxin of the 9 angstroms is 75%, leaving only a high dielectric permittivity. However, in this specific embodiment, the use of atomic silicon dioxide thickness reduction to allow only] · 2 angstroms or] 0% allowable (for example, 10 △) substrate removal media. Therefore, the general application of δ as described above is left. Analysis of metals and dielectrics. In addition, the sublayer removes the normal. Can this dielectric method. For example, it is best to use ultra-thin films for bulk and capacitors. Oxide layer. It can be configured that if the dielectric silicon film can be 25% thicker, the thickness can be reduced by the layer removal method. 25 (23) (23) 200427858 This ultra-thin silicon dioxide film is used to control the movement at the interface. A very high JI electric insulator is deposited on the ultra-thin oxide film by atomic deposition. Therefore, the total dielectric material fits within the allowable thickness of 12 angstroms, and is reduced by 10. /. It is composed of silicon dioxide and 90% A 12 0 3, T i 〇 2, H f Ο 2, C e 〇 2 'ZΓ〇2, or whether or not a high-k dielectric is used. For example, the performance trends of integrated circuit capacitors used in dynamic random access memory (DRAMs) are following from flat cells with silicon dioxide insulators to trench-type capacitors (deeply etched into semiconductor surfaces) and stacked capacitors (Stacked on semiconductor surface) Both grow. Future increases in capacitor performance will depend on the ability to reduce the size of these capacitors and transfer to capacitor technology, such as MIM (Metal-Insulator-Metal) and MIS (Metal-Insulator-Crystalline). In the stack type and trench type capacitors, the transfer to MIM technology can significantly reduce the physical size of SIS (crystalline silicon-insulator-crystalline silicon) capacitors and MIS capacitors, and also produce the same capacitance. However, the smaller the size obtained, the thinner the insulator dielectric must be. For example, the equivalent oxide thickness (EOT) of a SIS or MIS capacitor is relatively large for approximately 25 femtofarads, but for advanced capacitors (e.g., stack height> 1 micron or trench depth greater than 0.1 micron) May have to be 30 or 35 angstroms. However, advanced MIS or MIM capacitors with advanced dielectrics may require E0T in the range of 5 to 10 Angstroms. These dielectric insulators can be obtained by processing advanced dielectrics with nano-layers, such as Si3N4, Al203, Ta205, Hf02, Zr02, Ti02, La, and Y aluminates, other nano-layers (such as ATO / AHO, S but O) and perovskite (such as BST / PZT). The use of advanced electrode technology can (24) (24) 200427858 to enhance capacitor performance, such as HSG (hemispherical granulation) polycrystalline silicon, TiN / TaN with or without polycrystalline silicon, ternary compounds (such as JiAIN or

TaSiN), precious metals (such as Ru or RuO2), or perovskites (such as sr0 / LSC0). Example-Capacitor Device In an example of a method of forming a trench-type capacitor 100 having a trench depth of less than 100 nanometers, a trench 10 02 is formed in a conventional manner (for example, by reactive ion etching) followed by a trench The top of the groove forms the customary collar 104. Refer to Figure 9. The trench under the collar is doped at a temperature known as "seeding" to produce a doped polycrystalline silicon with particles between amorphous silicon and polycrystalline silicon (commonly CVD). Crystal silicon deposition method coating. The trench is then annealed under ultra-high vacuum. The "inoculation and annealing" method is typically based on UHV C V D. Amorphous silicon surface exposed to silicon source gas at low temperature and isothermally, and then annealed, tends to roughen the lower electrode to increase surface area and capacitance relative to a smooth surface in a trench capacitor. These increased surface areas can be up to 2: 1. Annealing leaves electrodes with microscopic "bumps" or pleats in the surface. The pleats have a size of about 20 nanometers. These methods are called HSG (hemispherical granulation) crystalline silicon. See Figure 10. An atomic layer deposition method (ALD) stacked into a layer with an EOT of less than 3.6 nm is deposited on a rough surface on an advanced dielectric with an increased surface area] 0 8 (such as A 12 0 3). Steps of the method This may include removing 07 (25) (25) 200427858 any oxidizing oxide and replacing it with a controlled thickness oxide and then removing the oxide with ALR until a very thin oxide is reached (eg, less than 4 layers Oxide single layer, preferably a single layer). Then "ALD" is used to deposit advanced dielectrics. Finally, multilayer 110 is deposited on the advanced dielectrics to serve as upper capacitor electrodes and complete SIS capacitors. Refer to Figure 11. This capacitor can achieve a capacitance of 25 fly farads and has a leakage current of less than 1 fly amp per battery cell. The A12 0 3 insulator in the SIS capacitor forms a semiconductor device at no more than 3 5 0 ° C temperature The lower exposure does not exceed 4 minutes. During this exposure, a minimal amount of interfacial silicon dioxide is formed between the HSG crystal silicon and the advanced dielectric, because some of the oxygen transfer in A 1 2 03 is the same as that in the lower layer. Crystalline silicon bonding. However, because of maintaining a low temperature budget, very thin interfacial oxides are maintained. In Figure 12, a barrier metal film U2 is deposited on an advanced dielectric before depositing multiple layers. The metal film 1 1 2 is consistent with the rough surface of the trench. Then, the barrier metal film is covered with metal, and a metal film 114 is formed on the barrier metal film. Refer to FIG. 12. Finally, doped polycrystalline silicon 1 1 6 塡Fill any gaps left in the trenches, and then chemical-mechanically polish the wafer to remove excess covering material. Refer to Figure 13. In this method, one electrode system of the capacitor forms the metal of the SIM capacitor. It is crystallized by HSG. Stacked capacitors with a height of less than 130 nanometers and 25 fly farads are formed on the surface of silicon. They use advanced dielectrics with thicknesses (EOT) less than 3.6 nanometers ai203, and then use multiple deposition methods to form SIS capacitors. ... or HSG crystal The surface forming height is less than (26) (26) 200427858 130 nanometers 25 flying fara stacked capacitors, which use a thickness (EOT) of less than 3.7 nanometers T a? 〇5 advanced dielectrics' followed by Multi-deposition method to form MiS capacitors. The formation of A 1 203 insulator in the SIS trough device exposes the semiconductor device to a temperature of not more than 350 ° C for 4 minutes, and it is a Ta205 insulator in the MIS capacitor. The formation effect allows the semiconductor device to be exposed at a temperature of not more than 750C for not more than 30 minutes. Among the variables of the above-mentioned 25-Farad stacked capacitors (formed with H2O3 advanced dielectric on the surface of HSG crystals) of less than 130 nanometers, the EOT used in this article is stacked to less than 2 · 8 A nano-layer (replacement of less than 3.6 nanometers) atomic layer deposition (ALD) method forms a dielectric, and after this method, a TiN deposition method is used to form an electrode for a MIS capacitor. This capacitor can reach a capacitance of 25 femtofarads and has a leakage current of less than 1 femtoampere per capacitor battery with an operating voltage of up to 1.5 volts. As discussed above, during this exposure, interfacial silicon dioxide is formed between the HSG crystalline silicon and the advanced dielectric. However, because a low temperature budget is maintained, a thin interfacial oxide (about 8 to 9 angstroms) is maintained. ). TiN is formed using a pseudo ALD method. The conventional c V D method using TiCl4 as a precursor to deposit TiN tends to have poor step coverage (about 25%). This tendency is particularly problematic when the capacitor dielectric is formed on the surface of H S G crystal silicon. The use of the ALD method (instead of CVD) has excellent step coverage 'but has a low growth rate. Mixing the two methods with the false A L D method, achieving a better 90% step coverage and a low chlorine content (^ 29 '^ (27) (27) 200427858 atom from the precursor). Furthermore, capacitors with improved capacitance and leakage characteristics are produced by the ALD and pseudo-ALD methods. '' Ternary barrier metal can be used to achieve high crystallization temperature, smooth morphology # due to the amorphous nature of the film, good diffusion barrier and good oxidation resistance. Finally, the advanced dielectrics (layers stacked in layers by the ALD method) can be replaced by alternating nano-layered dielectrics. For example, a Ti02 film with 15 angstroms (eg, 15-20 ALD cycles), followed by an Al203 film with 20 angstroms (eg, 20-25 ALD cycles), followed by a Ti02 with 15 angstroms A film (eg, 15-20 ALD cycles) can form a dielectric. These alternate nano stacks can be custom designed to meet EOT requirements, dielectric constant requirements, and leakage requirements. The two types of nano-perceived nano-layers can be stacked and stacked, or the mixed layers that rely on more than two types of nano-layers can be formed into a stack of any desired thickness. A stacked capacitor structure can be formed using the above-described insulator formation method for a trench capacitor, and vice versa. Φ Example-Cassette pole device The formation method of the cassette pole 200 is started in FIG. 14. In a discharge zone and source with a passage defined between the discharge zone and the source zone! A box electrode 200 is formed in a substrate 202 of g204. The insulator material 206 is deposited on the substrate, imaged, and etched in the recess on the channel to form an insulator 208 and a multi-cassette electrode 210. Figure 15 is a cross-section diagram of the cartridge pole 20.0 after the oxide film 220 (typically the conventional C VD method of 30 (28) (28) 200427858) is grown on the wafer. Figure 16 shows a cross-section of a wafer after it has been polished (for example, chemical mechanical polishing). FIG. 17 shows the box electrode 2 0 after the imitation box electrode 2 10 and the insulator 2 8 are removed (for example, by etching). Figure 18 is a cross-sectional view of the box pole 200 after the advanced dielectric 222 (as discussed above) has been grown on the box pole. FIG. 19 is a cross-sectional view of a cartridge 200 after a barrier metal 224 (eg, WN or N) has been formed on an advanced dielectric 222. FIG. 20 is a cross-sectional view of the box electrode 200 after the barrier metal 224 has been covered with the metal 226. FIG. 21 is a cross-sectional view of a cartridge pole 200 after it has been polished (for example, chemical mechanical polishing). Preferred specific embodiments and examples of novel methods and systems for forming semiconductor transistors and capacitors using atomic layer deposition methods and removal methods (hopefully to be exemplified, but not limited) have been described. Those skilled in the art can complete modifications and changes in accordance with the above guidance. It should therefore be understood that changes may be made in the specific embodiments of the invention disclosed within the scope of the invention as defined by the scope of the appended patent application. For example, ozone and or (tert-butanol) 4 can be used as a precursor to grow dioxin to monoamidine. Therefore, the present invention has been described in terms of the legal requirements of the patent, and the details and features of the patent protection application and requirements in the scope of the attached patent application. [Brief description of the drawings] The following description of the present invention will be described in detail with reference to the following figures. (29) (29) 200427858 Figures 1-3 illustrate the basic steps of the atomic layer removal method according to a specific embodiment of the present invention. Scheme. 4-6 are diagrams illustrating the steps of an atomic layer exchange method according to another embodiment of the present invention. 7 and 8 are diagrams illustrating basic steps of the atomic layer removal method after the atomic layer exchange method illustrated in FIGS. 4 to 6 according to another embodiment of the present invention. Figs. 9 to 13 are sectional views showing the steps of forming a trench capacitor according to the present invention. 14-21 are cross-sectional views showing a step of forming a transistor box according to the present invention. Table of comparisons 100: trench capacitor 102: trench 104: neck collar 106: microscopic bump 108: advanced dielectric 1 1 0: multilayer Π 2: barrier metal film 1 1 4: metal Film 1 1 6: Doped polycrystalline silicon 2 00: Box electrode (30) 200427858 202: Substrate

2 0 4: Emission area and source area 2 0 6: Insulator material 2 0 8: Insulator 2 1 0: Multi-cassette electrode 2 2 0: Oxide film 2 2 2: Advanced dielectric 2 2 4: Barrier Metal 226: Metal A: Film B: First reaction gas C: Second reaction gas D: Solid compound E: Gaseous compound X, Y: Elements in the gas

Claims (1)

200427858 拾 Pickup, patent application scope 1 · A method for processing a semiconductor substrate, comprising: reacting a first reaction gas with an exposed semiconductor substrate surface in a reactor to convert the exposed surface into a solid single layer; evacuating the reactor The first reaction gas; reacting the second reaction gas with the solid monolayer in the reactor to convert the solid monolayer into a gaseous compound; and evacuating the second reaction gas and the gaseous compound in the reactor. 2. The method according to item 1 of the scope of patent application, which comprises repeating the reaction of the first reaction gas a predetermined number of times, evacuating the reaction of the first reaction gas, the reaction of the second reaction gas, and evacuating the second reaction gas and Gaseous compounds. 3. The method according to item 1 of the patent application range, wherein the reaction of the second reaction gas with the solid monolayer requires less activation energy than the activation energy required for the reaction of the second reaction gas with the surface below the solid monolayer. energy. 4 · The method according to item 1 of the scope of patent application, wherein at least one process selected from the group consisting of temperature, irradiation pulse time, chamber pressure, molecular size of the first and second reactive gases, and molecular formation heat during the reaction Factors control the depth to which at least one of the first reactive gas and the second reactive gas diffuses into the exposed surface to avoid multilayer atomic exchange. 5. The method of claim 1, wherein the exposed surface comprises a compound of a metal, an oxide of germanium, and an oxide of one of the two-element semiconductors of Group 111 and Group V. (2) (2) 200427858 6 · The method according to item 1 of the patent application range, wherein the first reaction gas contains a compound including a hydroxyl group. 7. The method of claim 1 in which the first reaction gas comprises a compound which is one of water vapor, methanol, ethanol, propanol, and butanol. 8. The method of claim 1 in which the second reaction gas comprises a halogen-containing compound. 9. The method of claim 1 in which the second reaction gas contains a compound which is one of C1F3, BF3, BC13, NF3, NC13, HF, HC1, fluorine and chlorine. 10. The method according to item 8 of the patent application, wherein the first reaction gas comprises a compound including a radical. 1 1. The method according to item 1 of the scope of patent application, wherein the exposed surface comprises a compound of a metal, silicon, germanium, and an oxide of one of the two-element semiconductors formed by Groups II and V, which Method 尙 includes: repeating the reaction of the first reaction gas, evacuating the reaction of the first reaction gas, the reaction of the second reaction gas, and evacuating the second reaction gas and gaseous compounds until all oxides on the exposed surface are removed Until the substrate is exposed, the substrate includes one of metal, silicon, germanium, and two-element semiconductors shaped in groups III and V; and a nitride film is formed on the substrate by an atomic layer deposition method. 12. The method according to item 11 of the patent application scope, which comprises: reacting a third reaction gas with the surface of the exposed nitride film in the reactor (3) (3) 200427858 to convert the exposed surface into a gaseous state Compounds; and a third reaction gas and gaseous compounds in the evacuated reactor. 13. The method according to item 12 of the scope of patent application, which comprises repeating a reaction of a third reaction gas for a predetermined number of times, and evacuating the third reaction gas and a gaseous compound. 14. The method according to item 13 of the scope of patent application, wherein at least one selected from the group consisting of temperature, irradiation pulse time, chamber pressure, molecular size of the first and second reactive gases, and molecular formation heat during the reaction Processing factors control the depth to which the third reactive gas diffuses into the exposed surface to avoid multilayer atom exchange. 15 · The method according to item 13 of the patent application scope, wherein the third reaction gas contains a halogen-containing compound. 16. The method of claim 1, wherein the exposed surface comprises a compound of a metal, silicon, germanium, and an oxide of one of the two-element semiconductors of group III and group V. The method尙 Contains: repeating the reaction of the first reaction gas, evacuating the reaction of the first reaction gas, the reaction of the second reaction gas, and evacuating the second reaction gas and gaseous compounds until all oxides on the exposed surface and Until the substrate is exposed, the substrate includes one of metal, silicon, germanium, and two-element semiconductors shaped in groups III and V; and a barrier metal film is formed on the substrate by an atomic layer deposition method. 17. The method according to item 16 of the scope of patent application, wherein the barrier metal film comprises a compound, which is titanium nitride, giant nitride, tungsten nitride, 36 (4) (4) 200427858 Nitrid nitride, nitrogen One of the conductive oxides of Aluminium, Tungsten Aluminum Nitride, Titanium Silicon Nitride, Titanium Nitride, Titanium Nitride, and Ru, Rh, OS, and Ir. · 1 8. If you apply for a patent: Method 16 around item 5 which includes the formation of a dielectric monolayer by atomic layer deposition, where: The dielectric monolayer contains ---- compounds, which are A 1 2 〇3 丨, Ti02, HfO: > Λ C e 0 2, Zr02, Ta 2 0 5 and Li, Be, Na, Mg, K, Ca, Sc, V, Cr, Μη Fe X Co, Ni , Cu, Zn, G a, Ge, Rb, Sr, Y, Nb, Mo Tc X Pd, Ag, Cd, In, Sn, Sb, Cs, B a, La, W, Re X Pt A u, Hg , ΤΙ, Pb, Bi ,: Po, Fr, Ra, Ac, Pr, Nd% Pm, Sm, Eu, Gd, Tb, Dy, Ho, 'Er, Tm, Yb, L One of the oxides of one of u and Th-► 〇19. A structure comprising: a deoxidized substrate formed by removing at least one oxide monolayer using an atomic layer; and used on the deoxidized substrate A dielectric layer formed by atomic layer deposition of at least one dielectric monolayer. 20. The structure according to item 19 of the scope of patent application, wherein the deoxidized substrate comprises: a substrate including one of metal, silicon, germanium, and one of the two-element semiconductors of the III and V groups; and less than 4 A layer of an oxide monolayer disposed on a substrate. 2 1 · The structure according to item 19 of the scope of patent application, wherein: the dielectric film includes several layers of dielectric single layer; and -37-· (5) (5) 200427858 Each layer of dielectric single layer contains a compound , Its system A] 203, Ti 0 2, Hf02, C e 0 2, Zr 0 2, D a 2 05 and Li, Be, Na ·, Mg, KNC a, Sc, V, C r, Mn , F e, Co, Ni, Cu, Zn, G a, G e Rb, Sr, Y, Nb, Mo, Tc, Pd, Ag, Cd, In, Sn, Sb Cs, B a, La, W, Re, Pt, Au, Hg, Tl, Pb, Bi, Po Fr, Ra, Ac, Pr, Nd, Pm, S] m, Eu, Gd, Tb, Dy, Ho, Er, Tm, One of the oxides of Yb, Lu, and Th-22. As in the structure of the scope of patent application No. 19, which includes a barrier metal film formed on the dielectric film 2 3. The structure of the scope of application for patent No. 22, wherein: the barrier metal film includes several metal film single layers formed by an atomic layer deposition method; and each metal film single layer includes a compound, which is titanium nitride, nitride huge, Tungsten nitride, titanium aluminum nitride, giant aluminum nitride, tungsten aluminum nitride, titanium nitride silicon, molybdenum silicon nitride, tungsten nitride silicon, and conductive oxides of one of RU, Rh, Os, and Ir one of them. 24. The structure of item 22 of the patent scope of claim g, which includes a metal film formed by covering the barrier metal film with a metal. 25. The structure according to item 9 of the scope of the patent application, wherein the deoxidized substrate comprises: a substrate including one of metal, silicon, germanium, and one of the two-element semiconductors shaped in groups III and V; and in After the reaction between the substrate and ammonia removes all the oxide monolayers -38-^ (6) (6) 200427858 A silicon nitride film formed on the substrate. At least one silicon nitride monolayer is removed with an atomic layer to make it into A thin layer of less than four nitride single layers. 2.6. The structure according to item 25 of the scope of patent application, wherein: the dielectric film includes several layers of dielectric single layer; and each layer of dielectric layer includes Ta205. 27. A structure comprising: a deoxidized substrate formed when an oxide layer is repeatedly removed using an atomic layer until no oxide monolayer remains; and at least one metal film is deposited using the atomic layer on the deoxidized substrate A first barrier metal film formed by a single layer; and a dielectric film formed by depositing at least one dielectric single layer on the first barrier metal film using an atomic layer. 28. The structure of claim 27, wherein the deoxidized substrate includes a substrate including one of metal, silicon, germanium, and two-element semiconductors shaped in groups III and V. 2 9. The structure according to item 27 of the scope of patent application, wherein: I the barrier metal film includes a plurality of metal film single layers formed by an atomic layer deposition method; and each metal film single layer includes a compound, which is Titanium Nitride, Giant Nitride, Tungsten Nitride, Titanium Aluminum Nitride, Titanium Nitride, Titanium Nitride, Titanium Nitride Silicon, Titanium Nitride 'Tungsten Nitride Silicon and Ru, Rh, Os, and lr One of the conductive oxides. 30. The structure according to item 27 of the scope of patent application, wherein: the dielectric film includes several layers of dielectric single layer; and _39 (8) (8) 200427858 uses atomic layer to deposit at least one layer on the defluorination channel Cassette dielectric formed by a single dielectric layer. 35. The transistor of claim 34, for example, which includes a barrier metal film formed on the box dielectric. 36. The transistor as claimed in claim 35, wherein: the barrier metal film includes a plurality of metal film single layers formed by an atomic layer deposition method; and each metal film single layer includes a compound, which is nitrogen Titanium nitride, molybdenum nitride, tungsten nitride, titanium aluminum nitride, giant aluminum nitride, tungsten aluminum nitride, titanium silicon nitride, molybdenum silicon nitride, tungsten nitride silicon, and among Ru, Rh, Os, and Ir One of the conductive oxides. 37. For example, the transistor of claim 35 includes a metal box formed by covering a barrier metal film with a metal. 38. For example, the transistor of the scope of application for patent No. 34, wherein: the cassette dielectric includes several layers of dielectric single layer; and each layer of dielectric single layer contains a plurality of compounds, which are Al203, Ti 〇2, Hf02, Ce02, Zr〇2, Ta205 and Li, Be, Na, Mg, KX Ca, Sc, V, Cr, Mn, F e, Co, Ni, Cu, Zn, Ga, Ge N Rb, Sr, Y, Nb, Mo, Tc, Pd, Ag, Cd, In, Sn, Sb, Cs, B a, La, W, Re, Pt, Au, Hg, Tl, Pb, Bi, Po \ Fr, Ra, Ac, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy > Ho, Er, Tni, Yb, Lu, and Th Among them--Among the oxides- O 39. For example, the transistor in the 38th scope of the patent application, which includes 200427858 0) barrier metal film formed on the box dielectric, wherein: the barrier metal film includes several layers with atomic layers 4 metal film single layers formed by the deposition method; and each metal film single layer contains a compound that is a titanium nitride, a nitride nitride, a tungsten nitride, a titanium aluminum nitride, a nitride nitride , Wherein the conductive oxide is one of one of aluminum, tungsten nitride, titanium silicon nitride, silicon nitride, molybdenum, tungsten and silicon nitride, Ru, Rh, Os and Ir. 40 · A capacitor comprising: a deoxidized surface of one of a groove formed in a substrate and a stack formed on the substrate, wherein the deoxidation formed by removing at least one oxide monolayer using an atomic layer An oxidized surface; and a capacitor dielectric formed by depositing at least one dielectric monolayer using an atomic layer on a deoxidized surface. 4 1 · The capacitor according to item 40 of the patent application scope, which includes a barrier metal film formed on the capacitor dielectric. 4 2 · The capacitor according to item 41 of the scope of patent application, wherein: _ the barrier metal film includes several metal film single layers formed by an atomic layer deposition method; and each metal film single layer contains a compound, which is a Titanium nitride, molybdenum nitride, tungsten nitride, titanium aluminum nitride, giant aluminum nitride, tungsten aluminum nitride, titanium silicon nitride, giant nitride silicon, tungsten nitride silicon, and Ru, Rh, Os, and Ir One of the conductive oxides. 4 3 · The capacitor according to item 41 of the patent application scope, which includes a metal box electrode formed by covering the barrier metal film with a metal. A1 (7) (7) 200427858 Each dielectric single layer contains a compound, which is A120 3, Ti Ο 2, Hf02, Ce02, Zr〇2, Ta205, and Li, Be, Na, Mg, K , Ca, Sc, V, Cr, Mη ', Fe, Cο, Ni, Cu, Zn, Ga, Ge Rb, Sr, Y, Nb, M0, Tc, Pd, Ag'Cd, In, Sn, Sb, Cs, Ba, La, W, Re, Pt, Au, Hg, Ti, Pb, Bi, Po Fr, Ra, A c, Pr, Nd, Pm, S m, Eu, Gd , Tb, Dy Ho, Er, Tm, Yb, Lu, and Th Among them--Among the oxides-o 3 1. As the structure of the scope of the patent application No. 19, its 尙 is included in the reference A second barrier metal film formed on the electrical film. 3 2. The structure of item 31 in the scope of patent application, where: The second layer of barrier gold: the metal film includes several layers of metal film single layer formed by atomic layer deposition method and each metal film single layer & gt Contains a compound which is 1N, 1N, 1N, tungsten nitride, titanium aluminum nitride, aluminum molybdenum nitride, tungsten aluminum nitride, titanium nitride silicon, silicon nitride giant silicon, tungsten nitride silicon, and One of the conductive oxides of Ru, Rh, Os, and Ir. 33. The structure according to item 31 of the scope of patent application, which comprises a metal film formed by covering the barrier metal film with a metal. 3 4. —A transistor comprising: an emission region and a source region formed in a substrate; formed by limiting the substrate between the emission region and the source region and removing at least one oxide monolayer using an atomic layer Deoxidation channels; and (10) (10) 200427858 44 · If the capacitor in the scope of patent application No. 40, where: the capacitor dielectric includes several layers of dielectric single layer; and each-layer of dielectric single layer The layer contains a compound that is Al2O3, Ti0, 2 Hf02, Ce 0 2 'Z r 0 2, D0 5 and Li, Be, Na, Mg, KN Ca, Sc, V, C r, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge X Rb, Sr, Y, Nb, Mo, Tc, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, W, Re, Pt, Au, Hg, T1, Pb, Bi, Po X Fr Ra, A c, Pr, Nd, Pm, S m, Eu, Gd, Tb, Dy Λ Ho, Er, T m, Yb One of the oxides of-, Lu, and Th-45. As for the capacitor in the scope of patent application No. 44, its 尙 is included in the capacitor dielectric Barrier metal film, wherein: the early P metal film includes a plurality of single metal film layers formed by an atomic layer deposition method; and each single metal film single layer contains a compound , Tungsten nitride, titanium aluminum nitride, giant aluminum nitride, tungsten aluminum nitride, silicon nitride, gasification fun sand, tungsten nitride sand, and one of RX !, rh, 0s, and Ir One of the conductive oxides. -43-