TW200414212A - Method to test a memory device having USB interface and the memory device - Google Patents
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200414212 五、發明說明（1) 發明所屬之技術領域 本發明係關於測試具有半導體記憶體的記憶裝置的測試 方法及其記憶裝置，其特別係關於一種測試具萬用序列匯流 排（U S B - U n i v e r s a 1 S e r i a 1 B u s )介面之記憶裝置的測試方法， 以及一種具自我測試之萬用序列匯流排介面之記憶裝置。 先前技術 習知具有體快閃記憶體的記憶裝置，例如為大姆哥的記 憶裝置，其測試的方式係為由主機送出測試資料（t e s t pattern)，經由USB匯流排讀寫快閃記憶體，其寫入測試資料 至快閃記憶體，然後讀取快閃記憶體，比對測試資料及讀取 資料係在主機進行，此習知方式所需完成測試的時間相當耗 時，尤其記憶容量愈大的記憶裝置之測試更為耗時。 癱 發明内容 本發明目的係提供一種測試具萬用序列匯流排（USB)介面 之記憶裝置的測試方法，使得能夠快速完成記憶裝置的測 試。 本發明另一目的係提供一種具自我測試之萬用序列匯流 排（USB )介面之記憶裝置，其能夠接收測試命令後能夠自我快 速完成測試。 為達成本發明的目的，本發明提供一種測試具萬用序列200414212 V. Description of the invention (1) Technical field of the invention The present invention relates to a test method and a memory device for testing a memory device having a semiconductor memory, and particularly relates to a universal serial bus (USB-U niversa) for a test device. 1 Seria 1 B us) interface memory device testing method, and a self-testing universal serial bus interface memory device. A memory device with a body flash memory is known in the prior art. For example, the memory device is a big brother. The test method is to send a test pattern from the host and read and write the flash memory through a USB bus. It writes test data to the flash memory, and then reads the flash memory. The comparison of test data and read data is performed on the host. The time required to complete the test in this conventional method is quite time-consuming, especially as the memory capacity increases. Testing of large memory devices is more time consuming. SUMMARY OF THE INVENTION The object of the present invention is to provide a method for testing a memory device with a universal serial bus (USB) interface, so that the test of the memory device can be completed quickly. Another object of the present invention is to provide a memory device with a self-testing universal serial bus (USB) interface, which is capable of quickly completing a test by itself after receiving a test command. In order to achieve the purpose of the present invention, the present invention provides a test tool universal sequence
200414212 五、發明說明（2) 匯流排（USB )介面之記憶裝置的測試方法，其應用於一記憶裝 置，其中記憶裝置至少包含有一 USB介面、一個連接USB介面 的USB控制器、至少一個連接制器的半導體記憶體，該 測試方法包括下列步驟：USB控制器經由USB介面接收由一主機 所傳送之一測試命令；當USB控制器接收測試命令後，USB控 制器對半導體記憶體進行寫入及讀出，並比對寫入及讀出兩 者之資料是否相同，以測試半導體記憶體是否良莠；當USB控 制器完成半導體記憶體之讀寫測試後，USB控制器經由USB介 面對主機傳送一測試結果資料。 再者，為達成本發明的另一目的，本發明提供一種具自 我測試之萬用序列匯流排（USB )介面之記憶裝置，包括： 一 US’B介面；一個連接USB介面的USB控制器；至少一個連接 USB控制器的半導體記憶體；一程式碼，其用以提供USB控制 器執行，以進行：接收由一主機經由USB介面所傳送之一測試 命令；對半導體記憶體進行寫入及讀出，並比對寫入及讀出 兩者之資料是否相同，以測試半導體記憶體是否良莠；當完 成半導體記憶體之讀寫測試後，經由USB介面傳送一測試結果 資料。 為使熟悉該項技藝人士瞭解本發明之目的、特徵及功 效，茲藉由下述具體實施例，並配合所附之圖式，對本發明 詳加說明，說明如后：200414212 V. Description of the invention (2) Test method for a memory device of a bus (USB) interface, which is applied to a memory device, where the memory device includes at least a USB interface, a USB controller connected to the USB interface, and at least one connection system The semiconductor memory of the device includes the following steps: the USB controller receives a test command transmitted by a host through the USB interface; after the USB controller receives the test command, the USB controller writes the semiconductor memory and Read and compare whether the data written and read are the same to test whether the semiconductor memory is good or bad; after the USB controller completes the read and write test of the semiconductor memory, the USB controller transmits to the host via the USB interface A test result data. Furthermore, in order to achieve another object of the present invention, the present invention provides a memory device with a self-testing universal serial bus (USB) interface, including: a US'B interface; a USB controller connected to the USB interface; At least one semiconductor memory connected to the USB controller; a code for providing the USB controller to execute: receiving a test command transmitted by a host through a USB interface; and writing and reading the semiconductor memory To test whether the semiconductor memory is good or bad; after the semiconductor memory read-write test is completed, a test result data is transmitted through the USB interface. In order to make those skilled in the art understand the purpose, features and functions of the present invention, the following specific embodiments are used in conjunction with the accompanying drawings to explain the present invention in detail, as described later:
200414212 五、發明說明（3) 實施方式 第一圖顯示依據本發明原理所實施之記憶裝置的結構 圖。記憶裝置10包括有USB介面103，其用來連接主機12，或 是再經由USB集線器1 4連接主機1 2。至少一個連接USB控制器 1 0 1的半導體記憶體1 0 5，其用來作為資料之儲存，而半導體 記憶體1 0 5的記憶容量並無限制，例如可以依據實際需求而配 置為321^、64以6、128^^...等等，半導體記憶體10 5之具體實 施態樣可以係為快閃記憶體。程式碼1 0 7以及USB控制器，其 中程式碼1 0 7係用以提供USB控制器1 0 1執行第二圖所顯示之流 程，據此，程式碼1 0 7係為第二圖所顯示之流程的具體實施方 式，而程式碼1 0 7可以為軔體（f i r m w a r e )型態實施於記憶裝置 1 0。主機1 2可以係為個人電腦或是用以測試記憶裝置1 0的治 具。， 第二圖顯示本發明之測試方法之流程圖。第二圖之測試 方法係應用於如第一圖所顯示的記憶裝置1 0，步驟（2 0 )係US3 控制器1 0 1經由USB介面1 0 3接收由主機1 2所傳送之測試命令。 步驟（2 2 )係當USB控制器1 0 1接收測試命令後，USB控制器1 0 1 對半導體記憶體1 0 5進行寫入及讀出，並比對寫入及讀出兩者 之資料是否相同，以測試半導體記憶體1 〇 5是否良莠。步驟 (26)係USB控制器101完成半導體記憶體105之讀寫測試後， usm$制器1 0 1經由USB介面1 0 3對主機1 2傳送測試結果資料。 第三A圖及第三B圖顯示依據第二圖之精神而具體實施於200414212 V. Description of the invention (3) Implementation The first figure shows the structure of a memory device implemented in accordance with the principles of the present invention. The memory device 10 includes a USB interface 103, which is used to connect to the host 12, or connect to the host 12 via a USB hub 14. At least one semiconductor memory 105 connected to the USB controller 101 is used for data storage, and the memory capacity of the semiconductor memory 105 is not limited. For example, it can be configured as 321 ^, 64, 6, 128 ^^, etc., the specific implementation of the semiconductor memory 105 can be a flash memory. Code 1 0 7 and USB controller, of which code 10 7 is used to provide USB controller 1 0 1 to execute the process shown in the second figure, according to this, code 1 0 7 is shown in the second figure The specific implementation of the process, and the code 107 can be implemented in the memory device 10 in a firmware type. The host 12 may be a personal computer or a jig for testing the memory device 10. The second figure shows a flowchart of the test method of the present invention. The test method in the second figure is applied to the memory device 10 shown in the first figure, and the step (20) is that the US3 controller 110 receives the test command transmitted by the host 12 through the USB interface 103. Step (2 2) is after the USB controller 101 receives the test command, the USB controller 101 writes and reads the semiconductor memory 105, and compares the data written and read It is the same to test whether the semiconductor memory 105 is good. Step (26) After the USB controller 101 completes the reading and writing test of the semiconductor memory 105, the usm $ controller 101 sends the test result data to the host 12 via the USB interface 103. Figures 3A and 3B show the specific implementation in accordance with the spirit of the second figure
200414212 五、發明說明（4) 兄憶装置内之程式碼的流程圖，而主機丨2與記憶裝置丨〇彼此 間之測，方式及測試命令可以遵循SCSI命令（c〇mmand)格式作 為具體貫現手段。步驟（3 〇 )係記憶裝置丨〇接收主機丨2所傳送 之命令。步驟（3 2 )係判斷命令之類型，依據命令類型分別進 入所屬之下一個步驟。步驟（34)係處理測試命令（tes1： command )，其提供半導體記憶體1 〇 5是否良筹的測試回報，而 j试命令之具體手段可以係主機1 2傳送出測試命令，USB控制 =胃1 〇 1接收到測試命令後，分別對半導體記憶體1 〇 5設定不同 ，壓條件’例如為3· 0V低電壓、3· 3V正常電壓、3· 6V高電壓 等’在每一種電壓條件下完成測試命令的測試。然後對主機 1 2所指定的半導體記憶體1 〇 5欲測試的那一個晶片，將該晶片 第0個區塊（block)的每個位址寫入” ααπ，隨後讀取該區塊的 内谷判斷疋否為n A Aπ並記錄發生錯誤的位址，並抹除 (erase)該區塊，再對該區塊寫入” 55 ”到每個位址，讀取該區 塊的内谷’判斷是否為” 5 5 "並記錄發生錯誤的位址，重複上 述的動作直到該晶片最後一個區塊，最後將測試結果資料傳 回主機。 步驟（3 6 )係處理控制移轉transfer )命令，其 要係將§己fe裝置1 〇的裝置描述（d e v i c e d e s c r i p t 〇 r)、設置描 述（c ο n f i g u r a t i ο n d e s c r i p t o r )、字串描述（s t r i n g descriptor)等回報給主機12。 步驟（38)係判斷SCSI命令類型以進入處理8(：81命令之處200414212 V. Description of the invention (4) The flow chart of the code in the brother memory device, and the measurement, methods and test commands of the host 丨 2 and the memory device 丨 0 can follow the SCSI command (common) format Present means. Step (30) is that the memory device 丨 〇 receives the command transmitted from the host ②. Step (3 2) is to judge the type of command, and proceed to the next step according to the type of command. Step (34) is processing a test command (tes1: command), which provides a test report of whether the semiconductor memory 105 is good, and the specific means of the j test command can be a test command transmitted by the host 12, USB control = stomach 1 〇1 After receiving the test command, the semiconductor memory 1 〇5 is set differently, and the voltage conditions 'for example, 3 · 0V low voltage, 3 · 3V normal voltage, 3 · 6V high voltage, etc.' under each voltage condition Complete the test command test. Then, for the chip to be tested by the semiconductor memory 1 105 designated by the host 12, write each address of the 0th block of the chip to "ααπ", and then read the contents of the block. The valley judges whether it is n A Aπ and records the address where the error occurred, and erases the block, and then writes "55" to each address to read the inner valley of the block. 'Judge whether it is 5 5' and record the address where the error occurred, repeat the above actions until the last block of the chip, and finally send the test result data back to the host. Step (36) is to process the control transfer command, which is to describe the device description (devicedescriptor), the setting description (c ο nfigurati ο ndescriptor), and the string descriptor (string descriptor) of the device 1 〇 Wait to return to the host 12. Step (38) is to judge the type of the SCSI command to enter the processing 8 (: 81 command place)
200414212 五、發明說明（5) 理步驟。步驟（4 0 )係處理讀取命令（read command)，其提供_ 取半導體記憶體1 0 5的資料内容，而讀取命令之具體手段可以 係USB控制器1 〇 1檢查LUT(look-up-table)是否已建立，若無則 先建立LUT’接著讀取LUT(此為physical block address)，無 將 LBA(logical block address)的 5個 LSB bits加到 physica block address的LSB，以形成半導體記憶體1 〇5的起始讀取位 址，隨後開始度取半導體記憶體1 〇 5的資料。步驟（4 2 )係處理 寫入命令（write command)，其提供將資料内容寫入至半導體 記憶體1 0 5，而寫入命令之具體手段可以係USB控制器1 0 1先檢 查LBA是否已存在半導體記憶體1 〇5，若無則搜尋空的 physical b 1 ock (起始位址的設定則如同讀取命令），隨後開 始程式化（program)半導體記憶體1 〇5，若LBA已存在半導體記 憶體Ί 05内，步驟與上述相同，但需將舊的lbA的資料copy到新 的LBA以達到覆蓋的目的。步驟（44)係處理狀態回報命令 (status transport command)，其提供寫入命令、讀取命令& 理後之結果狀態之回報，記憶體裝置1 〇的其它狀態之回報。 本發明進一步揭露上述之測試命令之實施手段，其主要 係遵循SCSI命令格式，因此有Command Block Wrappe r ( CBW )挺4 Command Status Wrapper (CSW)。當主機u發出測試命令的 CBW，USB控制器1 0 1解碼主機1 2所發出的CBW，發現此CBW所具 之命令是通知USB控制器1 0 1測試半導體記憶體1 〇 5，據此， USB控制|§ 1 0 1對半導體記憶體1 〇 5寫入及讀出比對測試資料 (Test Pattern)” AA”以及”55’，，當測試完畢，USB控制器1〇1向200414212 V. Description of the invention (5) Physical steps. Step (40) is processing a read command, which provides _ fetching the data content of the semiconductor memory 105, and the specific means of the read command may be the USB controller 1 〇1 checking the LUT (look-up) -table) has been established, if not, create LUT 'first and then read LUT (this is the physical block address), without adding the 5 LSB bits of LBA (logical block address) to the LSB of the physical block address to form a semiconductor The initial read address of the memory 105 is then taken to retrieve the data of the semiconductor memory 105. Step (4 2) is processing a write command, which provides writing of data content to the semiconductor memory 105, and the specific method of the writing command may be the USB controller 1 01 to check whether the LBA has been There is semiconductor memory 1 05, if not, search for empty physical b 1 ock (the setting of the starting address is like a read command), and then start to program semiconductor memory 1 05, if LBA already exists In semiconductor memory Ί 05, the steps are the same as above, but the data of the old lbA needs to be copied to the new LBA to achieve the purpose of overwriting. Step (44) is processing a status transport command, which provides a status report of the write command, a read command & the processing result, and other status reports of the memory device 100. The present invention further discloses the implementation method of the above test command, which mainly follows the SCSI command format, so there is a Command Block Wrapper (CBW) and 4 Command Status Wrapper (CSW). When the host u sends the CBW of the test command, the USB controller 1 0 1 decodes the CBW issued by the host 12 and finds that the command of the CBW is to notify the USB controller 1 0 1 to test the semiconductor memory 1 05. USB control | § 1 0 1 write and read comparison test data (Test Pattern) "AA" and "55 'to semiconductor memory 1 0, when the test is completed, USB controller 10 1 to
第9頁 200414212 五、發明說明（6) 主機1 2回報測試結果資料，例如為測試失敗之晶片那一個區 塊的回報測試結果資料給主機1 2。然後，USB控制器1 〇 1回覆 狀i% C S W給主機1 2 ’以破認測試命令執行的狀況。 上述的CBW其格式係為π 5 5 5 3 42 43 74 0 7 F8 DB 00 〇 04 00 01 00 03 F0 00 00 00 00 〇〇 〇〇 〇〇 〇〇 〇〇 〇〇 〇〇 〇 00 00 00 ”。其中第0個至第三個位元組（byte)’，55 53 42 43 為bCBWSignature，代表此封包為CBW。其中第四個至第七個 位元組’’ 7 4 0 7 F 8 D Βπ為d C B W T a g，U S B控制器1 0 1在C S W中需回 覆相同的dCBWTag。其中第八個至第十一個位元組π〇〇 〇〇 〇〇 00 丨丨為 dCBWDataTransferLength，為主機 12預期由 Data-In，} 讀取的b y t e數，其長度不固定，因半導體記憶體1 〇 5的大小而 異。例如半導體記憶體105的大小為128M Bytes即共有819 2個 b 1 〇 c k s (區塊）’我們以一個b i t代表一個block( 0代表此b 1 〇 c 為 good; 1代表此 block為 bad)，共需回覆 l〇24bytes(8192 b i t s )給主機1 2。同理，6 4 Μ B y t e s的半導體記憶體1 〇 5則需回 覆5 1 2 b y t e s給主機1 2。其中第十二個位元組” 〇 1 ”代表資料由 記憶裝置1 0送到主機1 2。其中第十三個位元組” 〇 〇 ”代表 LUN(Logic Unit Number)。其中第十四個位元組”〇3”代表 CBWCB的有效長度，其表示共有3個bytes有效。其中第十五個 位元組n F 0 π為C B W C B的第0個b y t e，代表這是一個測試命令。 其中第十六個位元組π 0 0 π為C B W C B的第1個byte，代表主機12 要求USB控制器1 0 1測試半導體記憶體i 〇 5的第〇顆晶片。其中 第十七個位元組π 〇 〇 n為C B W C B的第2個b y t e，代表主機1 2要求Page 9 200414212 V. Description of the invention (6) The host 12 reports the test result data, for example, returns the test result data to the host 12 for the block where the test failed. Then, the USB controller 101 responds to the host 1 2 ′ with the status of the execution of the test command. The format of the above CBW is π 5 5 5 3 42 43 74 0 7 F8 DB 00 〇04 00 01 00 03 F0 00 00 00 00 〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇00 00 00 00 ” . Among them, the 0th to the 3rd byte (byte) ', 55 53 42 43 is bCBWSignature, which represents the packet is CBW. The 4th to 7th byte is'' 7 4 0 7 F 8 D Βπ is d CBWT ag, USB controller 1 01 needs to reply the same dCBWTag in CSW. The eighth to eleventh bytes π 〇〇〇〇〇〇 00 丨 丨 dCBWDataTransferLength, as expected by host 12 The number of bytes read by Data-In,}, its length is not fixed, and varies depending on the size of semiconductor memory 105. For example, the size of semiconductor memory 105 is 128M Bytes, which means there are 819 2 b 1 cks (area (Block) 'We use a bit to represent a block (0 represents this b 1 oc is good; 1 represents this block is bad), a total of 1024 bytes (8192 bits) need to be returned to the host 12. Similarly, 6 4 Μ Byy ’s semiconductor memory 1 0 05 needs to reply 5 1 2 bytes to the host 1 2. The twelfth byte " 〇1 "represents the data sent from the memory device 10 to the host 12. Among them, the thirteenth byte" 〇〇 "represents a LUN (Logic Unit Number). Among them, the fourteenth byte" 〇3 "represents CBWCB Effective length, which means that a total of 3 bytes are valid. The fifteenth byte n F 0 π is the 0th byte of CBWCB, which represents this is a test command. The sixteenth byte π 0 0 π is the first byte of CBWCB, which represents that host 12 requires the USB controller 101 to test the 0th chip of semiconductor memory 〇05. The seventeenth byte π 〇〇n is the second of CBWCB byte, representing host 1 2 requirements
200414212 五、發明說明（7) USB控制器1 0 1設定測試的電壓條件，π 0 0 ”表示正常電壓， π 0 Γ表示高電壓，π 1 0 π表示低電壓。其中第十八個至第三十 個位元組皆設為π 00π。上述之Data-In部份係為USB控制器10 回覆給主機1 2的資料，如第八個至第十一個位元組所述。 上述的CSW其格式係為π 5 5 5 3 4 2 5 3 74 0 7 F8 DB 00 〇b 0 0 0 0 0 0 π。其中第0個至第三個位元組1’ 5 5 5 3 4 2 5 3 π為 dCSW Signature，代表此為CSW。其中第四個至第七個位元組 "74 0 7 F8 DB"為dCSWTag，此值需與dCBWTag相同。其中第八 個至第十一個位元組” 00 00 00 00 "為dCSWDataResidue，其代 表U S B控制器1 0 1回覆給主機1 2的b y t e數與主機1 2所預期b y t e後 的差值。其中第十二個位元組π 0 0n代表命令已通過執行。 第四圖及第五圖的測試記憶裝置1 0的連接方式，能夠達 到大量測試記憶裝置1 0的目的。第四圖顯示主機測試複數個 記憶裝置的第一連接方式之結構圖。主機1 2經由在USB集線器 14的每個埠（port)連接一個待測記憶裝置10，而主機12連接 USB集線器1 4。測試人員可依序測試記憶裝置1 0，若記憶裝置 1 0發生錯誤時，馬上得知記憶裝置1 0有問題，待測試完畢 後，再插上另一個待測記憶裝置1 0。另外，也可將所有的待 測記憶裝置1 0插上USB集線器1 4，由主機1 2執行軟體來判斷發 生錯誤的記憶裝置1 0。 第五圖顯示主機測試複數個記憶裝置的第二連接方式之200414212 V. Description of the invention (7) The USB controller 1 0 1 sets the test voltage conditions. Π 0 0 ”indicates a normal voltage, π 0 Γ indicates a high voltage, and π 1 0 π indicates a low voltage. Eighteenth to eighth The thirty bytes are all set to π 00π. The above Data-In part is the data that the USB controller 10 responds to the host 12 as described in the eighth to eleventh bytes. The format of CSW is π 5 5 5 3 4 2 5 3 74 0 7 F8 DB 00 〇b 0 0 0 0 0 0 π. Among them, the 0th to the third byte 1 '5 5 5 3 4 2 5 3 π is dCSW Signature, which means that it is CSW. The fourth to seventh bytes " 74 0 7 F8 DB " is dCSWTag, which must be the same as dCBWTag. The eighth to eleventh bits The "tuple" 00 00 00 00 " is dCSWDataResidue, which represents the difference between the number of bytes that the USB controller 1101 replies to the host 12 and the bytes expected by the host 12. The twelfth byte π 0 0n indicates that the command has been executed. The connection manners of the test memory devices 10 in the fourth and fifth figures can achieve the purpose of a large number of test memory devices 10. The fourth figure shows a structure diagram of the first connection mode of the plurality of memory devices tested by the host. The host 12 is connected to a memory device 10 under test through each port of the USB hub 14, and the host 12 is connected to the USB hub 14. The tester can sequentially test the memory device 10, and if an error occurs in the memory device 10, it is immediately known that there is a problem with the memory device 10. After the test is completed, insert another memory device 10 to be tested. In addition, all the memory devices 10 to be tested can also be plugged into the USB hub 14 and the host computer 12 executes software to determine which memory device 10 has caused the error. The fifth figure shows the second connection method of the host testing a plurality of memory devices.
第11頁 200414212 五、發明說明（8) 結構圖。第五圖的切換開關用以代替第四圖的USB集線器，在 測試某一個記憶裝置1 0時，則連通上對應的開關1 6，其餘則 斷路。第五圖的訊號D+及訊號D-係表示為USB訊號。 第六圖顯示本發明與習知測試方式之效率比較圖。從第 六圖明顯看出本發明之效率優於習知技藝之測試方式，尤其 半導體記憶體1 0 5的容量愈大時，本發明所具之效率愈彰顯 著。 雖然本發明已以較佳實施例揭露如上，然其並非用以限 定本發明，任何熟悉此技藝者，在不脫離本發明之精神和範 圍内，當可作各種之更動與潤飾，凡所做之各種更動與潤飾 皆在本發明後附之申請專利範圍内。Page 11 200414212 V. Description of the invention (8) Structure diagram. The changeover switch in the fifth figure is used instead of the USB hub in the fourth figure. When a certain memory device 10 is tested, the corresponding switch 16 is connected, and the rest are disconnected. The signals D + and D- in the fifth figure are shown as USB signals. The sixth figure shows the efficiency comparison between the present invention and the conventional test method. From the sixth figure, it is obvious that the efficiency of the present invention is better than that of the conventional technique. Especially, the larger the capacity of the semiconductor memory 105 is, the more significant the efficiency of the present invention is. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. Various modifications and retouching are within the scope of the patent application attached to the present invention.
第12頁 200414212 圖式簡單說明 第一圖顯示依據本發明原理所實施之記憶裝置的結構圖。 第二圖顯示本發明之測試方法之流程圖。 第三A圖至第三B圖顯示依據第二圖之精神而具體實施於記憶 裝置内之程式碼的流程圖。 第四圖顯示主機測試複數個記憶裝置的第一連接方式之結構 圖。 第五圖顯示主機測試複數個記憶裝置的第二連接方式之結構 圖。 第六圖顯示本發明與習知測試方式之效率比較圖。 10 記憶裝置 101 USB控制器 103 ' USB介面 105 半導體記憶體 107 程式碼 12 主機 14 USB集線器 16 開關Page 12 200414212 Brief description of the drawings The first diagram shows the structure of a memory device implemented in accordance with the principles of the present invention. The second figure shows a flowchart of the test method of the present invention. Figures 3A to 3B show the flowcharts of the codes implemented in the memory device according to the spirit of the second figure. The fourth figure shows a structure diagram of the first connection mode of the plurality of memory devices tested by the host. The fifth figure shows a structure diagram of the second connection mode of the plurality of memory devices tested by the host. The sixth figure shows the efficiency comparison between the present invention and the conventional test method. 10 Memory device 101 USB controller 103 'USB interface 105 Semiconductor memory 107 Code 12 Host 14 USB hub 16 Switch
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