SU984001A1 - Generator of pseudorandom pulse trains - Google Patents

Description

(54) GENERATOR OF ALIASER SEQUENCES

PULSES

The invention relates to a pulse technique and can be used to create control code generators and to simulate various random processes.

A pseudo-random sequence generator is known that contains a shift register with a modulo two adder, the register outputs are connected to the input of a decoder (multi-input element. And), whose outputs are connected to the inputs of two keys through a trigger with a counting input, the second input of the first key is connected to the output of the shift register, the second input of the second key is connected to the output of the shift register through the inverter, and the outputs of the keys through the OR element are connected to the output of the device. In this device, each cycle of a pseudo-random sequence (PSP) is registered by a decoder (configured, for example, to all units), which switches the keys passing to the output direct or inverted sequence 1 via the counting trigger input.

The disadvantage of the device is low reliability, since the sensor does not work when turned on and not in the register of units. In addition, the alignment of the structure of ones and zeros of such a SRP is performed over two periods of its operation, i.e. with long caps - for a long time; Phasing such a memory bandwidth on reception is quite difficult.

The closest in technical essence is a pseudo-10 random pulse generator containing a shift register consisting of n serially connected flip-flops, the second inputs of which are connected to the output

15 clock generator, modulo two, the first input of which is connected to the first output of the p-th shift register trigger, and the second input of the modulo adder

20 two connected to the first output (n-l) -ro trigger shift register, multi-input element And, the inputs of which, except the last, are connected to the second outputs (n-1)

25 triggers shift register, the element OR, the inputs of which are respectively connected to the outputs of the modulo two and multi-input element AND, the last input of which

30 is connected to the second output of the nth

register trigger, and the output of the OR element is connected to the first input of the first register trigger 2 3.

A disadvantage of the known device is that it does not provide a uniform structure of ones and zeros.

The aim of the invention is to enhance the functionality by forming a uniform structure of ones and zeros in the sequence. .

The goal is achieved by VeM that a pseudo-random pulse sequence generator comprising a clock pulse generator, the output of which is connected to the clock inputs of the shift register, the kth and nth bit outputs of which are connected to the first and second inputs of the modulo adder, OR, additionally entered a modulo-two adder and a pulse counter, the first input of which is connected, to the output of the clock generator; the second input of the pulse counter is connected to the input of the shift register and to the output of the additional modulo two, the first input of which is connected to the output of the modulo two adder, and the second input is connected to the output of the pulse counter and to the first input of the OR element, the second input of which is connected to the output ( nl) -th bit output of the shift register, and the output of the element OR is connected to the input of the n-th bit of the shift register. The drawing shows a functional diagram of a generator of pseudo-random pulse sequences.

The generator contains. Reg. 1 sdvga on triggers, adders 2 and 3 modulo two, generator 4 clock pulses, counter 5 pulses, element OR 6.

The generator works as follows.

The shift register 1, the output (n-1) of the trigger of which is connected to the n-trigger via the element OR 6, and the outputs of the k-ro and n-th trigger are connected via adders 2 and 3 to the input of the register 1, form a pseudo-random sequence sensor. The input of the counter 5 receives the clock pulses from the generator 4 clock pulses. Single pulses from the output of the adder 4 modulo two set the counter 5 to the zero state.

If from the output of adder 4 modulo two to the input of register 1 post- / pit (n-1) zeros, then in all bits of register 1, except the last one, zeros will be written (in the last one) and counter 5 will form on

the output pulse, which does not pass through the adder 3 modulo two, since the output of the adder 2 modulo two will also be one, therefore, in the register 1 will be written zero. At the same time, the back edge of the pulse from the output of counter 5 to the nth digit of the shift register I will be recorded through the element OR b, which by the next clock through the adders 2 and 3 modulo two will go to the input of the shift register 1 to form the next period of a pseudo-random sequence.

If in register 1 shift when

- when the device was turned on, not a single unit was recorded, then after (n-1) a beat at the output of counter 5, a unit is formed, which through modulator 4 is written to the register

0 1 and restore normal operation.

Thus, in the proposed generator, in comparison with the known, a pseudo-random sequence is formed with a uniform structure of units and zeros (to create a Gaussian pseudo noise) and automatic recording of the unit when it is turned on and off.

0 increases the reliability of the generator when turned on.

Claims (2)

1.Patent of France No. 2304222, cl. H 03 K 3/84, 1976. 2. The author's certificate of the USSR 5 in 752768, cl. H 03 K 3/84, 1979.