SU945814A2 - Device for complex signal optimal processing - Google Patents

Description

(54) OPTIMAL PROCESSING DEVICE

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The invention relates to radio engineering and can be used in communication systems with complex signals.

According to the main author. St. N9 361445 a device is known which contains two multiple-side delay lines, taps. which are connected through weighing elements that form a matrix with vertical and horizontal tires. The input of the processing device is connected to the input Q of the first multi-split delay line, the output with the output of the second multi-split delay line 1.

The disadvantage of the known device is 5, the fact that for each concrete set of weighing elements it allows to process only one specific complex signal of a certain forzma, with readings of which 20 indicated weighting elements of the matrix are matched.

The purpose of the invention is to expand the range of the waveform of the processed signals. DIFFERENT SIGNALS

The goal is achieved in that the device for optimal processing of complex signals, containing two multi-branch delay lines and a matrix of weighed elements, in which the outputs of the first multi-branch delay line are connected to the vertical buses of the matrix of weighted elements, and the horizontal buses of the weighting elements are connected to the corresponding branches of the second multi-branch delay lines, a clock generator, a control signal generator, a control signal distributor, memory elements and a control signal chronizer, where the clock generator output is connected to the control signal generator input, the first input of the control signal distributor and the first input of the control signal recording chronizer, the first control signal generator output is connected to the second control input of the control signal signals, the second output of the control signal controller is connected to the 39th second input of the control recording recorder, the control input of each weighing element is connected to the output of the corresponding lementa memory, the first inputs of memory elements connected to the distributor outputs control signals, second inputs of memory elements connected to the outputs chro trainer of recording the control signals. In addition, the memory elements can form a control matrix, structurally combined with a matrix of weighted elements, with the first inputs of the memory elements connected to the horizontal buses of the steering matrix, the second inputs of the memory elements connected to the vertical tires of the steering matrix so that of each memory element, the numbers of the horizontal and vertical tires of the control matrix connected to it coincide with the numbers of the corresponding tires of the weighing matrix, the elements associated with the connected to this element entom memory element weighting. The drawing shows the scheme of the proposed device. The device contains the first 1 multi-branch delay line, the second 2 multi-branch delay line, the weighing elements 3, which form the matrix of the weighing elements, the memory elements 4, the control signal distributor 5, the control signal generator 6, the control signal recording clock 7 and the clock generator 8 The connections of the multi-drop lines 1 and 2 of the delay and the matrix of the weighing elements 3 are similar to the prototype. The weighting elements 3 are also connected to the elements 4 of the memory. Each memory element has two inputs, with one input connected to the distributor 5 of control signals, the other to the chroniser 7 of control signals. The input of distributor 5 is connected to the first output of the generator 6 of control signals, the other output of which is connected to the input of the chroniser 7 of the control signals. The generator 6 of the control signals, the distributor 5 of the control signals and the chronizer 7 of the control signals are also connected to the clock generator 8. The device operates in the following ways. The complex signal being processed is fed to the first multi-drop line 1 delay. While advancing along it, the signal is sequentially allocated to its outlets 144. Through the vertical tires of the matrix of weighing elements, through these weighing elements 3, the responses of the delay lines arrive on the horizontal tires of the said matrix. The transmission coefficients of the weighing elements 3 of the control are L5pot the elements of the memory 4 so that these coefficients turn out to be consistent with the corresponding counts of the processed signal that the device is currently configured to receive. Signal signals from several weighing elements are sent to each horizontal bus of the matrix of predictive elements. Therefore, partial sums of mutually time-weighted responses of the first multi-split delay line are formed on these buses. The indicated partial sums from the horizontal tires of the matrix of the weighing elements arrive at the corresponding inputs of the second multi-drop line 2 delays. As these partial sums move along the second multi-tap delay line (in the direction of its exit), the individual partial sums are added to it. As a result, the output of the second multi-split delay line yields the result of adding all partial sums so that after the last sample of the processed signal arrives at the first multi-split delay line, the output of the second multi-split delay line is convolved, which is fed to the output of the device. The fact that the weighing elements 3 are configured to be controlled by the corresponding memory elements 4 allows the processing device to be configured to receive any complex signal whose sample information is previously recorded in the corresponding memory elements 4. The device is configured to receive complex, 1x signals of various forms, which are dried by means of additionally inserted elements 4 of memory, distributor 5 of control signals, generator 6 of control signals, chronizer 7, recording of control signals and clock generator 8, as well as performing weighing elements 3 managed. The processing device is configured to receive a particular signal as follows. The clock; the generator 8 generates the clock pulses at time intervals l-tjy, which are fed to the generator 6 of control signals, the distributor 5 of control signals and the chronizer 7 of control signal recording. The generator 6 of the control signals generates control signals corresponding to the readings of the signal being processed, following each other at a clock interval, as well as pulses (at a different output) corresponding to a certain phase of the pulse repetition of the control signals generated by it, for example at the time of generating the first control signal. The control signals from the first output of the control signal generator 6 are fed to the input of the control signal distributor 5, in which, using pulses of the clock generator 8, the incoming control signals are arranged at different outputs connected to the corresponding memory elements 4. Thus, the corresponding control signal arrives at the first input of each memory element 4. The pulses of the phase of the chip from the second output of the generator 6 control signals are fed to the synchronizer 7 recording control signals, which c. using clock pulses from the clock generator 8, the write commands issued to the second inputs of the memory 4 elements are generated at the corresponding times at each output. At each memory element 4, at the time of arrival of the command from the corresponding output of the synchronizer 7, a control signal is received. It is at this point in time at the first input of this memory element from the distributor 5 control signals. This control to the next signal (until the next entry into the memory) constantly from the output of the data memory element is fed to the control the third input of the corresponding transmitter element 3. The control signals, the signal recorded earlier in the memory element {if it was recorded), when a new control signal is recorded, it is erased, which ensures that the memory is updated when the same complex signal is continuously received and the device switches to processing another complex signal when such a need arises. Updating the memory while continuously receiving the same complex signal is necessary to protect against the accidental loss of information entered into the device (for example, from interruptions of power supply). Thus, by switching the control signal generator 6 to the generation of various sequences of control signals, the device is tuned to receive (process) complex signals of the corresponding forms. The clock interval of the generator of control signals D t fy is arbitrary and independent of the size of the interval of readings of the received signal D – t. The hardware implementation of the proposed device is made easier when the control signal distributor is executed in the form of a shift register with the number of outputs ui, equal to the number of horizontal matrixes of the casing elements, and the chronizator of the recording of control signals is equal to the number of ticks of the specified matrix. In this case, the write signal of the control signals is executed as a device issuing successively one pulse (command) in each control cycle, first on its last (right), then on the penultimate, and so on, outputs up to the first output, inclusive the output of the first pulse (at the last output) must correspond to the arrival of the first control signal at the last (lower) output of the distributor - the shift register, and the remaining pulses (at the other outputs) must follow through s time and Luu-,. Such a chronizer can easily be realized, for example, by connecting two counters in series, respectively to vn and and pulses, and the shift register with ift outputs, and these counters should be started and reset from the phase generator of control signals. In such an implementation, the memory elements are connected to the control matrix with vertical and horizontal tires (as well as the casing element matrix), and each memory element of this control matrix should be placed constructively directly at the location of the corresponding element of the control matrix. this memory element (as shown in the drawing). Such a technical solution makes it possible to impose a matrix on each other and to combine it in a constructive manner in the form of a single controlled matrix.

In the case when the processed complex signal is obtained by phase manipulation of the carrier oscillations according to the pseudo-random sequence, the control signal generator can be executed similarly to the transmitter generator, the control signal distributor - in the form of a conventional binary shift register, memory elements triggers, and controllable weighting elements, as combinations of phase splitters with resistors and controllable keys.

In the particular case, each vertical bus of the matrix of the weighing elements may consist of two wires fed in antiphase (from the corresponding tap of the first delay line), then the need for phase splitters in the compositions of the weighing elements disappears.

The proposed device can be used when receiving broadband signals in those cases where at present, due to the absence of switchable filter-type devices, mainly correlation devices are used.

Claims (2)

1. The device optimal processing of complex signals on the author. St. No. 361445, characterized in that, in order to expand the range of the waveform of the signals being processed, a clock generator, a control signal generator, a control signal distributor, memory elements and a control signal recording clock are inputted to it, the clock generator output is connected Mb with. the Ipireparopa input of the upstream snnplov, the first input of the rag: prsedelit (l control S1 signals and the first input of the control signal recording chronizer; the second entrance of the chronizator control signal records, the control input of each weighing element is connected to the output of the corresponding memory element, the first inputs of the memory elements are connected to the outputs of the distributor of control signals, the second inputs of the memory elements are connected to the outputs of the control recording recorder. 2. The device according to claim 1, about tl and one that the elements of The cells form a control matrix, structurally aligned with the matrix of weighing elements, the first inputs of the memory elements are connected to the horizontal blades of the control matrix, the second inputs of the memory elements are connected to the vertical tires of the steering matrix so that for each memory element horizontal and vertical tires connected to it the control matrix coincide with the numbers of the corresponding buses of the matrix of the weighing elements associated with the weighing element connected to the memory element. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 361445, cl. GO1R 19/02, 25.06.70.