SU938282A1 - Device for binary number multiplication - Google Patents

Description

(54) DEVICE FOR MULTIPLICATION OF BINARY NUMBERS

t. .

The invention relates to computing and can be found at. change in electronic computational masses and high-speed data processing processors.

A device is known that contains three stages of logical cells, on the basis of which it is possible to build multipliers of any size 111.

The drawback of the device is the wide range of modules for building multipliers with extended factor multipliers, as well as a low degree of module integration, which makes them inefficient in the form of large integrated circuits (VIS).

The closest to the invention according to the technical solution is a device containing a matrix of N x (N-1) full one-bit adders (where N is the operand width), a matrix of NxN elements, And 2N-bit adder, and the output of the full one-bit adder The j-ro column of the i-th row is connected to the transfer input of the full one-bit adder (j + l) -ro of the steel column (| +1) -th row, where, ..., Ml,

 (N-1), the output of the aum, a, b-th full one-digit adder is connected to the input of the summ (a + 1) of the b-th full one-digit adder (where, ..., N-1,, ..., M-1), the output of the full one-bit adder (N-1) output and rows from the ith column is connected to the transfer input of the full one-bit row adder

, 5 (s + 1) -th column, where, ..., M-1, the first inputs of the elements And are connected respectively to the bit input buses of the multiplicable device, the second inputs of the elements And connected)

20 responsibly with the device input multiplier bus widths, the outputs of the elements AND (+1) diagonal of the matrix of elements AND (where, ... 2N-2) are connected respectively from the input of a {first K to the full one-bit SUNmatr of the U-th column ( where,.,., .. j M), where% iJTL: h is the coolest whole less than or equal to the weight of the product, the 2H-bit totalizer moves are with the t21 device codes. The disadvantages of this device include: - Excessive number of main and additional terminals of the device - Insufficient performance and the inability to remove the waTopa from the 2M-capacity bag as an external autonomous node, which allows saving the number of terminals in the device. The purpose of the invention is to expand the functionality by performing the operation of summing the 2M-bit term, increasing the speed. The goal is achieved by introducing 2N memory elements into the device, with the transfer output of the full one-bit adder (H-2) -th row of the d-th column connected to the transfer input of the full one-bit adder (M-1) -th row (d + l) -ro column {where d M / 2-1, ..., M-2), the transfer output of the full one-bit adder (H – 3) of the row of the e-th column is connected to the input cyMhbi of the full one-bit adder (Nl) -u row (е + 1) -th column (where, ..., М-3), the outputs of the output full one-bit adders are connected respectively to the inputs (2N-1) of the senior elements of the pa The mi, the output of the element And the first diagonal of the matrix elements And are connected to the input of the lowest memory element, the outputs of the 2N memory elements are connected respectively to the inputs of the first group of the 2M-bit adder, the inputs of the second group of which are the summation inputs of the device, the transfer input of the full one-bit This totalizer of the last row (M / 2 + 1) of the column is the input to round the device. FIG. Figure 1 shows a functional diagram of an eight-bit device for multiplying binary numbers by 4 mg. 2 - the same, the matrix multiply, in FIG. 3 - structural scheme,. illustrating the operation of the device. The device contains elements AND 1, a matrix 2 full single-digit adders 3, 2M-bit adder 4, multiplicative tires 5, multiplier tires 6, control input 7, summation inputs 8, rounding input 9, device outputs 10, memory elements 11. The device for multiplying sixteen-digit numbers consists of four modules of multipliers 12-15 eight-bit chips: each of which contains a matrix 16, including AND elements, registers 17, a sixteen-digit adder 4, output register 18, transfer output 19 and control input 20 . Matrix 16, register 17 and adder 4 are divided, dotted into the older and younger parts. In the device, the transfer output of the full one-bit adder of the 3j-th column of the i-th row is connected to the transfer input of the full one-bit adder 3 (j + l) -ro of the column (1 + 1) -th Row where j 1, ..., M- 1, (N-1), ..., N the output of the sum of a, b of the full one-bit adder 3 is connected to the input of the sum (a + 1), of the b of the full adder 3 (where, ..., N -1, ..., M-1), the transfer output of the full one-bit adder 3 (N-1) -th row of the Cth column is connected to the transfer input of the full one-bit adder 3 of the Nth row (s + 1) -th column where, ..., M-1 are the first inputs of the elements AND 1 are connected respectively with p As complex inputs 5 of the device multiplier 5 buses, the second inputs of the And 1 elements are connected respectively to the input input buses 6 of the device multiplier, the outputs of the And I elements (q-fl) are the diagonal of the matrix of the And 1 elements (where, ..., 2N -2) are connected respectively to the inputs of the first K full one-bit adders 3 V-ro columns (where ..., M), where K liiLr nr 1 “. ..lUl is the nearest integer less than or equal to p / 2, an is the weight of the product's discharge, the outputs of the 2M-bit adder 4 are the device outputs 10, the transfer output of the full one-bit adder 3 (M-2) -th row d-ro column connected to

the transfer input of the full one-bit C5matter 3 (M-1) -th row (column (where d: M / 2-1, ..., M-2), the output of the transfer of the full one-bit adder 3 (M-3) -th , the rows of the e-th column are connected to the input of the sum of the full one-bit adder 3 (M-1) -th row (e + 1) -th stop (where, ..., M-3), the outputs of the output full one-bit adders 3 connected respectively to the inputs (2N-1) of the higher memory elements 11, the output of the And 1 element of the first diagonal of the matrix of the And 1 elements is connected to the input of the lower memory element 11, w 1 inputs 2N of the memory elements 11 are connected respectively to the inputs of the first group of the 2M-bit adder 4, the inputs 8 of the second group of which are the summing inputs of the device, the transfer input of the full one-bit adder of the last row (M / 2 + t) -ro of the column is the input 9 of the rounding device.

The implementation of the device can be implemented as a module. In matrix 2 of full one-bit adders 3, two N-bit numbers are multiplied directly, which can be allocated as an autonomous device, and a 2Y-bit adder 4 can be either included in the multiplication device when it is implemented as an LSI with in order to exclude additional equipment when modules are combined, or derived from an LSI in order to save conclusions.

The introduction of memory elements 11 in combination with the placement of additional entrances along the edges of matrix 1 makes it possible to easily implement a conveyor multiplication mode when combining modules in order to expand the discharge grid of factors.

The operation of the device is illustrated with examples of performing the multiplication of sixteen-digit numbers in a conveyor mode.

The input of module 12 is X-J.Q and the bits of the factors, the input of module 13 X-j.QH Yvg.g, the input of module 14 and Y, and the input of module 15 and Y | g-. In each matrix 16, on the elements of AND, a logical multiplication of the factors factors is performed, after which directly in the matrix 2 complete single-digit

adders 3 performs a bitwise addition of logical products and propagation of a transfer signal along matrix 2 in a time equal to 2 (N-1) f where f r is the signal propagation time in a full one-bit adder 3.

For bits, this will amount to 14. In the first beat, which enters input 7-1, the products obtained are P ,, Pg. , P; 5to Pif-o z n ° are minimized in registers 17. From the outputs of registers 17, the products are fed to the corresponding inputs of adders

4 with a shift to the left of the partial products due to the multiplication algorithm. When adding partial products in adders 4, the transfer signal from output 19 is formed only in adder 4 of module 14. The transfer signal at output 19 of module 13 is absent, because it adds the highest part of the product formed by module 12 and the lower part of the product formed by module 13.

In this case, in the output adder 4 of the device, when forming the product, the transfer signal is absent

em. In the device, a transfer signal occurs at the output. adder 4 only at the moment of addition of partial products when modules are combined, and the transfer signal from output 19 of module 14 is fed to input 8 of module 15.

In the second clock cycle at the input 20, the result of the addition in the form of a thirty-two-bit product is stored in register 18. When new operands arrive with a rate equal to one device operation cycle, the full cycle of operation is repeated.

The module combines by connecting the outputs 10 of the highest production bits of module 12 to the inputs 8 of module 13, while the outputs 10 of module 13 are connected to inputs 8 of module 14, etc.

Unlike what is known in the proposed device, there is a direction of data transmission of intermediate calculations when combining modules and there is no feedback between the modules, which makes it easy to organize the conveyor principle of calculation.

Claims (2)

The conveyor structure of a sixteen-bit multiplier made up of eight-bit modules requires equal time ratios in the steps of the conveyor. Therefore, in order to align the transition process in the steps, summation 4 can be performed according to a scheme with a rough transfer 4. Thus, as a result of the new organization of links in the matrix of single-digit adders, the introduction of additional inputs into the 2M-bit the rummator, the total number of outputs and inputs becomes two less than in the known device, the time of multiplication by the delay time of a single-bit adder is reduced, the conveyor principle of multiplication is implemented when modules are combined, the possibility of additional th adding in an M-bit multiplier bottom 2M-bit weakly with 2N-pa3r dnym product. When modules are combined, the possibility of reducing multiplication is obtained. The modular structure of the multiplier allows orienting the implementation of the device in the form of a hang; : Claims An apparatus for multiplying binary numbers containing a matrix NX x (Nl) of full one-bit adders (where N is the size of operands), a matrix of NxMJ elements I, 2N bit d | & 1 adder, match the transfer output of the full one-bit sum The j-ro column is connected to the transfer input of the full one-bit adder (j + 1) -th column, where, ..., M-1, M-2 (N-1), the output of the sum of the ab-th full one-bit adder is connected with the input of the sum (a + 1) of the Lth full one-bit adder (where ae1 ,, .., N-1,, .. М-1), the output of the transfer of the full one-bit summat pa (M-1) -th row of the th column is connected to the input of the transfer of a full one-bit sum-, torus of the N-th row (c + 1) of the th column, where, ..., M-1), the first the inputs of the elements I are connected respectively to the discharge input buses of the myogee device, the second inputs of the elements AND are connected respectively to the input input buses of the device multiplier, the outputs of the elements AND (q + 1) -th diagonal of the matrix of elements AND (where, ..., 2N +1) are connected respectively to the inputs of the first K full one-bit adders of the V-ro column (where, ..., nsi М), where K ,, is the tiniest integer less than or equal to n / 2, An output weight, outputs of a 2K-discharge adder, are outputs of the device, characterized in that, in order to expand the functionality by performing a 2H-discharge summation operation, a 2N memory elements are inserted into the device, the transfer output of a full one-bit adder (N-2) -and column rows is connected to the transfer input of a full one-digit adder (M-1) -th row (d + 1) -ro column (where d M / 2-1,. ., M-2), the output of the transfer of the full one-bit cy cytopa (N-3) -th line of the e-th st The Album is connected to the input of the sum of a full one-bit adder (N-1) -th row (e + 1) -th column (where ,, .., М-3), the output of the output one-digit adders connect with the inputs (2N- I) the highest memory elements, the output of the element And the first diagonal of the matrix of elements And are connected to the input of the junior memory element, the outputs of the 2N memory elements are connected respectively to the inputs of the first group of a 2H-bit adder, the inputs of the second group of which are the summing inputs of the device, transfer input of a full one-bit adder The last row (M / 2 + 1) of the column is the input rounding the device. Sources of information taken into account in the examination of U Patent OPA No. 3914589, cl. G 06 F 7/39, published. 1975. 2. US Patent B 3752971, cl. G 06 F 7/39, published. 1975 (prototype). "about, . " ZR i-s 5) 38282 t: Ж К