SU860109A1 - Remote signalling system with channel time-sharing - Google Patents

Description

(54) TELESIGNALIZATION SYSTEM WITH TEMPORARY DIVISION

one

The invention relates to automation and telemechanics and can be used to monitor the states of dispersed objects.

Known telemechanical system The radius in which the receiving device and a group of peripheral devices are contained, the receiving device comprising a synchronization unit, a sync driver, a clock generator, a reception unit and a completed conversion unit. Each peripheral device rotssr-zhit, in turn, is a generator of pulses, a synchronization receiving unit, a clock pulse receiving unit, a distributor and a response generator GO

Peripheral devices in the system are polled cyclically. Each cycle is started by transmitting from the receiver to the communication line ;, connecting it with peripheral devices, a clock pulse, after the co-channels

Secondly, there is a transmission of a series of clock pulses, each of which defines an information transmission interval for one of the peripheral devices. In the tele-alarm mode, each of the peripheral devices responds with a pulse transmitted to them within the interval allocated to it.

The disadvantage of such a system is its complexity, associated with the presence of a distributor in each peripheral device, which ensures the corresponding clock pulse from the overall sequence to bind to this peripheral device of a certain time interval for transmitting information. This deficiency is most pronounced in cases when peripheral devices are connected to the communication line in a strictly sequential manner, i.e., the communication line has the same structure, without branches.

Closest in technical grip to the proposed tele-ignalization system with time separation of canals, containing N serially connected peripheral devices, j each of which contains a pulse receiving unit and a clock receiving unit, the inputs of which are connected to the first input of the peripheral device, the second input of which IQ is connected with the first input of the shift register, the signal inputs of the peripheral device are connected to the corresponding second inputs of the shift register, the third input of which is connected to you hjj house of the clock receiving unit; the shift register input is connected to the first input of the peripheral device; the receiving device, the input of which is connected to the communication line, contains a synchronization unit, a clock generator and a clock pulse generator; the shift register, the output of which is connected to the first input And, the output of the element And is connected to the input of the terminal transform block 27.

The disadvantage of this system is its complexity and a large number of different types of functional blocks. 30

The purpose of the invention is to simplify the system.

The goal is achieved t & that a selective element and an inverter are entered on each peripheral device, the input and output of the selective element are connected to the first and second inputs of the peripheral device, respectively, the first output of the sync pulse reception unit is connected to the third 40 shift register input, and the second output the sync pulse reception unit is connected via an inverter, to the fourth input of the shift register; nhroimpulsov and through clock generator to the input of the receiver and a first input of a shift regist1, vy per- 50 output synchronization unit connected to the second input element I.

FIG. 1 shows a system diagram; ni fig. 2 time diagrams of her work.55

The system contains a group of peripheral devices I, connecting via the communication line 2 with the receiving device 4.

Each peripheral device 1 contains blocks for receiving clock pulses 4 and clock pulses 5, shift register 6, selective element 7 and inverter 8, device inputs 9.

The receiving device 3 comprises a synchronization unit 10, clock drivers 11 and sync pulses 12, a shift register 13, a terminal conversion unit 14 and an AND 15 element.

The system works in the following way.

During the operation of the system by the synchronization unit 10, a sequence of clock pulses (diagram II in FIG. 2) and sync pulses 17 (diagram III in FIG. 2) is continuously generated at its output 16 (the diagram in FIG. 2 operates cyclically, the cycle being set between alternate sync pulses

The system is convenient to consider from the moment when the sync pulse and the clock pulse are simultaneously output to the communication line 2, and the clock pulse generators 11 and the sync pulse 12 provide, when outputting to the link 2, such a representation of these pulses that allows them to be separated safely. in peripheral devices 1 (for example, using 4M with different carriers).

When the reception unit 5 receives the sync pulses of each of the peripheral devices 1 of the sync pulse, a signal is generated at the output of this block that arrives at the resolution input of the shift register 6.

The same signal through the inverter 8 is fed to the input of the resolution of the shift of the e register, causing the prohibition of the shift. A clock pulse, simultaneously inserted by the clock receiving unit 4, is fed to the clock input of the shift register 6, thereby recording the signals from the device inputs 9, which reflect the current state of the control objects connected to this peripheral device.

Claims (2)

Later, within the cycle, only clock pulses continue to arrive at the inputs of the peripheral devices, and at the moment of entering each of them. At the output I of the synchro pulses receiving unit 5, there is a signal prohibiting writing to the shift register 6, and, due to the presence of an inverter 8, allowing shift in this register. The signal from the output of the shift register 6 of one peripheral device 1 is fed to the input of the shift register 6 of the peripheral device 1 closest to the first in the direction of the receiving device 3. The signal from the output of the shift register 6 of the peripheral device 1 nearest to the receiving device 3 through link 2 to the input of the shift register 13 of the receiving device (see diagram D in Fig. 2), to the clock input of which the clock pulses go from the output 16 of the synchronization unit 10, so that the shift register 13 during the cycle kazyvaets recorded in a positional state of all control objects connected to the system. The diagram in FIG. 2 shows for five peripheral devices in the system, to each of them, 3 KOHT rotated objects are connected, with object No. 2 of peripheral device No. 2 and No. 3 of peripheral device No. 4 being in state I, and the rest in state O. The arrival of signals from the input of any of the shift registers 6 to its own input and to the inputs of other shift registers 6, besides the shift register of the nearest subsequent peripheral device 1, is excluded due to the presence of selective elements 7 that prohibit the passage of potential signals and allow passage of modular-modulated signals. When the block 10 forms a synchronization at its output 17 of the next sync pulse, the AND element is unlocked and the data from the shift register 13 is written into the block 14 of the terminal transformation. The system works again according to the cycle described earlier. Thus, a significant reduction in the equipment used is achieved in the system. Thanks to the absence of the need for the receiver to access each of the peripheral devices in order to receive information. 9 The claims of the TV remote signaling system with time channels, containing N serially connected peripheral devices, each of which contains a clock receiving unit and a clock receiving unit, the inputs of which are connected to the first input of the peripheral device, the second input of which is connected to the first input of the shift register, signal the inputs of the peripheral device are connected to the corresponding second inputs of the shift register, the third input of which is connected to the output of the BLS: and receiving clock pulses pulses, the output of the shift register is connected to the first input of the peripheral device, the receiving device whose input is connected to the communication line containing the synchronization unit, the driver of clock pulses and the driver of clock pulses, the shift register whose output is connected to the first input of the I element, the output of the I element is connected with an input of a terminal transformation unit, characterized in that, in order to simplify the system, a selective element and an inverter, an input and an output of a selective element are introduced on each peripheral device The first output of the sync pulse receiving unit is connected to the third input of the shift register, respectively; the second output of the sync pulse receiving unit is connected via an inverter to the fourth input of the shift register; in the receiving device, the first and second outputs of the synchronization unit are connected respectively via a sync pulse generator to through the driver of clock pulses with the input of the receiving device and with the first input of the shift register, the first output of the synchronization unit and is connected to the second input, element I. Sources of information, received during the examination 1. Review V.N. Telemechanics. M., 1973, p. 324. 2. USSR author's certificate 478346 cells. G 08 C 19/28, 1974 prototype). five Jjl FIG. one