SU841125A1 - Impulse counter with error control - Google Patents

Description

The invention relates to computational techniques and automatic control systems and can be used to continuously monitor the operation of various types of counters. A device for controlling counters is known, which contains a pulse generator, a level distributor, AND, OR elements and decoders 1. The drawbacks of the device are its complexity and the impossibility of checking the operation of the counter during its main work, which leads to time overhead. The closest to the proposed technical essence is a pulse counter with error control containing the main and controlling counters, the elements OR, AND, the expander of the transfer signal from the older one. the additional counter, the control signal output bus, the counting pulse supply bus and the transfer signal pickup bus 2. However, the device has low control reliability, as if one of the low bits of the counter being monitored is faulty and there is a single the signal, this signal is constantly compared with the transfer signals of the controlling counter, resulting in the result of the comparison falsely indicates that the supervised counter works correctly. A similar result is obtained when a similar fault occurs in any of the higher bits of the counter being monitored. In addition, this device does not allow the detection of meter faults, which are expressed by the presence of jumpers between the bits. The purpose of the invention is the behavior of the monitoring content. The goal is achieved by the fact that the pulse counter with error control, which contains a main counter and a low-resolution controlled counter, the inputs of which are connected to the reference counting pulses, two AND elements, the outputs of which are connected to the inputs of the OR element, and a signal expander, one of the outputs of which connected to the first inputs of the elements And, additionally introduced decoders for n and m outputs and (p-2) elements And, the main and additional elements And combined into groups of m elements.

and the first inputs of elements AND of each group are connected to the corresponding outputs of the signal expander, whose input is connected to the last output of the decoder for m outputs, the second inputs of elements AND via a decoder for n outputs are connected to the outputs of the main counter, the third inputs of the corresponding elements AND of each group are connected to the corresponding the outputs of the decoder to m outputs, the inputs of which are connected to the outputs of a small-size monitoring counter, and the outputs of additional elements AND are connected to the corresponding inputs of an elec- ment or. The drawing shows the functional scheme of the device.

The pulse counter with 1 error control contains the main counter 1, a low-level controlling counter 2, combined into groups of m elements IZ, element OR 4, expander 5 signals with controlled outputs, decoders b and 7, respectively. Pit outputs, bus 8 counting pulses and bus 9 issuing a control signal.

Monitoring counter 2 is a ring counter.

The expander 5 signals with controlled outputs in the general case can have K outputs (j, j + 1, .., K). The number of outputs in it corresponds to the number of groups combining elements of AND 3. In the initial state, there is a single signal on its J-OM output, and a zero signal on all others. Upon receipt of the first signal from the last, t-th output of the decoder 7, a zero signal is set at the J-OM output of the signal expander 5, and at its next j + 1, the output is a single signal, so that at the K-output of the signal expander 5 a single signal was established, K pulses should be sent to its input.

The decoders b and 7 on the p and m outputs are rectangular decoders, the outputs of each of which alternately appear signals.

The proposed counter works as follows.

Before starting operation, the main counter 1, the controlling counter 2, and the signal expander 5 are set to their original, zero state (not shown).

On the bus 8 to the inputs of the main counter 1 and the controlling counter 2 receives the counting pulses. The filling of the counters starts at the same time, and the same combinations of signals are sent to the inputs of the decoders B and 7, as a result of which signals appear at their identical outputs. Since the signal expander

is in the initial state, at its J-OM output there is a single signal allowing the comparison of the signals from the outputs of the decoders b and 7 in the corresponding group of elements 3. The bit-wise comparison on the elements 3 of this group takes place until The signal at the last, m-th output of the decoder 7, which is fed to the input of the signal expander 5, and at its J-OM output sets a zero signal covering all elements AND 3 of the corresponding group, and at j + 1-th output appears single signal opening all element s I 3 next group, which compares the signals from the output of the main, counter 1 and the resetting control counter 2 through the appropriate decoders b and 7,

After the next checkout counter 2 is filled, the signal appears at the last, m-th output of the decoder 7, which sets a zero signal at the j + 1st output of the signal expander 5, and a single signal at its j + 2 output. Now the comparison of the signals from the outputs of the decoders b and 7 is conducted on the elements of the H of the next group, and t, d. After the comparison of the signals from the outputs of the decoders b and 7 on the elements of the AND 3 K group is completed, the monitoring process of the main counter 1 ends, and with the counter working correctly, the output of the OR 4 element appears pulses with a counting pulse frequency.

If the main counter 1 is faulty and a single signal is constantly present at the output of one of its bits, the combinations of input signals arriving at the inputs of each of the decoders b and 7 will be different, and therefore the output signals will appear at different OUTPUTs of decoders b and 7 Therefore, not all the And 3 elements coincide with the outputs of the decoder 6 and 7, and therefore the pulse frequency at the output of the OR 4 element changes, indicating that the main counter 1 is malfunctioning. In type 1, a jumper between the bits of the fault signal of the main counter 1 is formed in a similar way;

Thus, the proposed set of features makes it possible to detect faults in meters of the type of constant potential at the outputs. its bits and also jumper type faults between bits.

Claims (2)

Invention Formula A pulse counter with error control, containing a main counter and a low-level controlling counter, the inputs of which are connected to the bus of counting pulses, two AND elements, the outputs of which are connected to the inputs of the OR element, and a signal expander, one of the outputs of which is connected to the first inputs of the AND elements, characterized in that, in order to increase the reliability of the control, it additionally introduces the decoders for the pit outputs and (p-2) elements AND, the main and additional elements being combined into groups of m elements, and the first inputs The elements of the AND elements of each group are connected to the corresponding outputs of the signal expander, the input of which is connected to the last output of the decoder for m outputs, the second inputs of the elements I and through the decoder for n outputs are connected to the outputs of the main counter, the third inputs of the corresponding elements AND of each group are connected to the corresponding outputs of the decoder m outputs, the inputs of which are connected to the outputs of the small-size monitoring counter, and the outputs of the additional AND elements are connected to the corresponding inputs of the OR element. Sources of information taken into account during the examination 1. USSR author's certificate No. 518774, cl. G 06 F 11/10. 2. USSR author's certificate number 356793, cl. H 03 K 21 / 34,28.07.69 (prototype).