SU833076A2 - Block-multiplexing channel - Google Patents

Abstract

UNIT MULTIPLEX Yu \ NAL. on auth. № 7'62591, about t l and. This is so that, in order to increase the integrated performance in the block mode, new multiplexing, it contains a queue memory and interrupt register, the first and second inputs of which are connected respectively to the first output of the external device address register and the fourth output of the local memory control node, the first and second outputs of the interrupt register are connected respectively to the output bus of communication with the central processor and with the fifth input of the local memory control node connected two-way with the memory Before, yield 'which is connected to a ninth input channel control node 1 ^ "0 (g (Ac -ch00iOOICOO ^ < 1 °:. > &

Description

The invention relates to the field of computer technology and is intended to organize the exchange of information between RAM and high-speed external devices. .

According to the main auth. No. 762591 is known a block-to-line multiplex channel containing the register of information, the register of markers, the register of the protection key, the register of the result indicator, the register of the address of external devices, the register of the byte of the channel, the register of the command code, the register of the operational memory, the register of flags, the register accounts, comparison circuit, channel control node, local memory node, address modification and data counting node, data buffering unit, local memory management node, subchannel state register, interface unit with external devices, dynamic unit for its purpose, with the first inputs of external device address registers, result indication, security key, markers, information, byte of channel status, command code, memory address, checkboxes, account, address modification node and data account and fourth inputs of the block (Data serialization, interface unit with external devices are connected to the third output of the control unit. The second input and output of the external address register are connected respectively to the second output. | And the input of the interface unit with external devices. , the third input of the external device address register, the first input of the comparison circuit and the first input of the channel control node are connected to the input interface bus with the central processor, the first output of the result status register, the fourth output of the external device address register and the second output of the channel control node are connected to the output bus connection with the central processor, the second output of the result feature register is connected to the eighth input of the local memory node, the first outputs of the information registers, addresses of the main memory, markers, cells The protection and control node of the channel are connected to the output bus of the main memory management, the second input of the registrar key register is connected to the third output of the local memory node, the third input of the protection key register and the second input of the local memory node are connected to the first output of the code register commands, the second inputs of the register of markers and the information register are connected to the first output of the data buffering unit, the third inputs of the information register and the memory address register are connected to the second output of the local memory node.

the fourth input of the information register, the second inputs of the command code register, the address of the operating memory, flags, data counting and the sixth input of the channel control node are connected to the input communication bus with the main memory management, the fifth input and the second output of the information register are connected respectively to the second the output and input of the data buffering unit, the first output of the channel status byte register is connected to the first input of the local memory node, the second output of the status byte register is the channel connected to the fifth input of the channel control node, the second the output of the command code register is connected to the third input of the interface unit with external devices and to the fourth input of the channel control node, the third output of the memory address register is connected to the third input of the local memory node, the second output of the memory address register is connected to the first input of the block data buffering, the first output of the register of flags is connected to the third input of the channel control node, the first output of the account register is connected to the fourth input of the local memory, the first output of the comparison circuit is connected to v eye input node control channel, Thu .verty control channel output node coupled to a second control input node local memory, a seventh control channel input node coupled to the first output state register subchannels, the eighth control channel is connected to the input node. the third output of the interface unit with external devices, the first output and the seventh input of the local memory node are connected respectively to the second input and output of the subchannel status register, the sixth input of the local memory node is connected to the first output of the local memory management node, the ninth input the local memory node and the third input of the data buffering block are connected to the fifth output of the interface unit with external devices; the fourth output and the fifth input of the local memory node are connected respectively to the third input and the second output of the modified module Addressing and data billing, the first output and the second input of the address modification node and the data counting are connected to the fourth output and the fifth input of the buffering unit respectively; the third output of the data buffering block is connected to the fifth input of the interface; external device; control local memory is connected to the first input of the register of a subchannel, the first input and output of the interface block with external devices are connected respectively to the output and input buses. The connection to external devices, the third

the input and the third output of the local memory control node are connected respectively to the output and the input of the dynamic assignment unit P.

In the specified channel the condition arises in the external device (WU) at the end of the channel program. the interrupt is not accepted for storage in the subchannel, but is stored in the slave. This does not allow, firstly, the release of the VU immediately after the end of the channel program and thus reduces the integral performance of the system in cases where the VU is used in multichannel mode of operation. Abnormal mode of operation of high-speed VU), especially for multiprocessor systems having a common field external memory, secondly, the time-consuming execution of the current channel program and the recording of interrupted channel programs to free the subchannels and thereby reduces the integrated performance l channel.

The aim of the invention is to increase the integrated performance in the block multiplexing mode by releasing the WU in multichannel mode and increasing the integral channel performance by freeing the subchannels of the terminating channel programs during the execution of the current channel program.

This is achieved by entering into the block-multiplex channel the memory of the queue-and the interrupt register, the first and second inputs of which are connected respectively to the first output of the address register of external devices and the fourth output of the local memory management node, the first and second outputs of the interrupt register are connected with the output bus with the central processor and the fifth input of the local memory control node connected by two-way communication with the queue memory, the output of which is connected to the ninth input of the control channel node scarlet.

Due to the introduction of the queue memory and the interrupt register, it is possible to free the slave immediately after the end of channel programs, form a queue of devices within the channel whose subchannels store the breaks, and combine the time of the interrupt channel programs with the execution of current channel programs.

Fig. 1 shows the block-multiplex channel block diagram; Fig. 2 shows the block diagram of the local memory management node.

The device contains a register 1 with external devices, a result indication register 2, a protection key register 3, a register 4 mlrcorp, an information register 5, a byte register, a channel status, a command code register 7, a register 8 memory address, a register of 9 flags , register 1.0 Accounts, comparison circuit 11, channel control node 12, local memory node 13, data modification and data counting node 14, data buffering unit 15, local memory control node 16, forward channel status register 17, interface block 18 with external devices, interrupt register 19 j, memory 20 of the queue (devices whose subchannels store interrupts), dynamic assignment unit 21, interface bus 22 interface with the central processor, output link 23 of the communication with the central processor, input bus 24 communication with the memory management, communication output bus 25 with memory management, output bus 26 for communication with external devices, input 27 for communication with external devices.

The local memory management node (see FIG. 2) contains: OR elements 28 for generating local local memory addresses, OR elements 29 for controlling the determination of the destination memory address, OR elements 30 for managing the definition of a queue memory address subchannels, OR 31 elements to control the reception of the subchannel state to the subchannel state register, trigger 32 for interrupt register information, local address memory address generator 33, local address memory address generator 34, memory address 35 address generator and tron devices, subchannels are stored Prairie Vani, bus 36 control signals from. Channel control button, bus 37 from the memory of a queue of subchannels storing interrupts, bus 38 of the sub-channel number from the dynamic allocation unit, bus 39 of the address from the address register. Sa external devices, address bus 40 from interrupt register, bus 41 address of access and control to a local memory node, address bus 42, and control of a queue of devices whose subchannels store an interrupt, address and control bus 43 to a dynamic assignment unit , subchannel status register bus 44, bus 45

5. control the interrupt register.

The queue memory 20 (UCH) is intended to record the correspondence between the addresses of the slave and the corresponding binary signs of the states. For each possible value of the address of the slave, there is one single-bit cell in the memory whose physical address is the same as the address of the slave, and it stores states for the corresponding WU.

The single value of the state sign means that for the corresponding WU there is an assigned subchannel that is in the interrupt storage state. A zero value of the state sign means that there is no assigned subchannel for the corresponding VL or it. no nahs / deels in interrupt storage state.

The interrupt register (RP) is a counter that can operate in the counting mode and in the address storage mode ...

To determine the mode of the register, use the trigger for the register of interruptions in the local memory management element 16. A single trigger state means that the register is in storage mode, i.e. busy

The address of the slave, for which an interrupt is required, can either be received from register 1 of the address of external devices, or formed on register 19 of interrupts as a result of viewing c. counting mode, the queue of subchannels that store the interrupt. The queue of subchannels stored by the interrupt is viewed all the time when the interrupt register of the OS is cleared, since the busy trigger is in the zero state. The single state of the trigger register of the interrupt register is pointers. that the address of the slave is set to interrupt the lib1e as a result of receiving the slave address from register 1, or by a signal from the memory of queue 20 (subchannels storing interrupts), os starting that as a result of viewing the queue, the subchannel storing interrupt.

The busy trigger retains a single state until the interrupt record finishes, and then is reset by a signal from the channel control node.

Before the operation of the block-multiplex channel, the start is made on installation by signals. CHANNEL INITIAL INSTALLATION (NUK) AND INITIAL CHANNEL INSTALLATION (SHORT-TERMINAL).

NUK .. „

NUCC - - - 1

On a short signal, the interrupt register 19, and the trigger 32 are set in O. On the register 19, the address search starts, starting with zero. At the same time, zeros are written to the values in all digits of the signs of assignment, 0 is fed to one input, 0 to the other inputs, and zeros are written to all the memory addresses being enumerated.

During operation of the channel to the register 19, the search of addresses continues.

After completion of the channel prog grams appropriate conditions nj eryvani arising slave, prinimayus in the subchannel, subchannel is transferred state RETAINS interrupt signal INSTALL subchannel still stored PRERtANIE (USPKvHP) and wherein a PM be 20 recorded 1 adpecy Nachod schemus in register 1 The external device operating with the channel is released.

Since the channel operates in multiplexed mode, after the completion of a single channel program and prior to taking into account processor interrupts, several more channel programs can be started and completed on the channel results. Since the signal CHANNEL FOR ACCOUNT OF INTERRUPTION IS SET (PUPRU), the interrupt request to the processor remains during the operational state of the channel, and the address of the device causing the interrupt is saved to register 18.

Upon receipt of the signal ACCOUNT OF THE INTERRUPTION from the processor, the channel control node 12 is configured to write to the operational memory of the channel state word. If the channel performs data transfer via another channel program at the moment of recording the interruption, the information from the assignment memory at the address formed from the register address 19 is selected into the dynamic assignment block by the VYURAT signal to the assignment block (VBN). nor kan, ala. Upon completion of the interrupt recording procedure, a signal is received from the Kanaet control unit 12 to cancel the APPLICATION CANNING / ONPK /, which is recorded in the destination memory at the address on register 19 of the O sign. The memory 20 at the address on the register 19 is recorded O.

Following the signal of the ONPK, a signal is released to RELEASE the TOR of the FER of the FPSA, at which the trigger register 19 is reset. As soon as the trigger 32 is reset, the register 19 starts operating in the counting mode. One of the triggers of register 19 is set to 1, and a queue memory is allowed. Each tick is added to the contents of register 19, and from memory 20, the contents are still selected on register 19. If 0 is selected from memory 20, the trigger .32 remains in the zero state and the counting mode continues. If 1 is selected from the URN 20, the address of the device remains on register 19 for which 1 is written to the URN 20.

The CAM signal arrives at channel 12 control. If the channel at the time the CUP is installed is in the working state, an interrupt request is set to the processor and the interrupt waiting is awaited. If the channel is not in a working state at the time of installation of the PND, the channel status and interrupt request to the processor is established. Prior to the introduction into memory channel 20 of register 19, at the time of completion of the channel program, the channel was not able to remember which of the sub-channels. He finished the work, and therefore no conditions were received in the subchannel of the channel program, but remained in the device. The subchannel remained operational until the interrupt from the processor was taken into account. Interrupting accounting for the conditions of the termination of the channel program could be performed only in the presence of an idle switch state. B. The channel operation time in the channel can be freed from the termination conditions of the subchannel and device, i.e. accept the termination condition in the subchannel and perform interrupt mapping. However, it is not possible to do this without additional memory of devices that have completed work, since the subchannels are passive and work only when they are accessed. In order to make the subchannels hard interrupt active with respect to the channel, a queue memory and a counter are needed that would constantly promatrimat it. If the memory of the queue is inserted into the channel (DEVICES whose subchannels store the interrupt, immediately after the end of the channel program. The termination conditions are received into the channel, the subchannel is set to the STORE INTERRUPTED state and is queued for accounting of the interrupt, and the device is released to work on another direction... Thus, the waiting time of a device is practically minimized. By reducing the unproductive waiting time of a device, we thereby increase the integrated performance of the system, since In the I / O Supervisor queue, 10 programs and the need for faster device release always exist. Releasing subchannels in parallel with channel program execution is of particular importance in channel saturation mode when all subchannels are occupied. Thus, the introduced equipment increases the integral performance in block multiplexing mode. in the case of using external devices in multi-channel mode, increases the integral performance of the channel due to Time tim performing the current channel program and interruption IO for previously zavershivshihs channel programs.

Claims (1)

BLOCK MULTIPLEX CHANNEL. by auto No. 762591, therefore, in order to increase the integrated performance in block multiplexing mode, it contains a queue memory and an interrupt register, the first and second inputs of which are connected respectively to the first output of the external address register devices and the fourth output of the local memory control unit, the first and second outputs of the interrupt register are connected respectively to the communication output bus with the central processor and to the fifth input of the local memory control unit, connected by two-way communication with queue memory, output ^{1 of} which is connected to the ninth input of the channel control node. $ e SU ,,. 833076