SU809306A2 - Device for preventing errors in transmission system with feedback - Google Patents

Description

A disadvantage of the known device is the inadequate reliability of information transfer.

The purpose of the invention is to simplify the device.

To achieve this goal, the coding and decoding blocks consist of a register, clock frequency sensors, an AND element and an OR element, the information input of the register being the second input of each encoding and the "First input of each decoding unit", the register output is connected to the input of the AND element the output of which is the output of each coding and decoding blocks, the clock input of the register is connected to the output of the OR element, the first input of which is connected to the output of the first clock frequency sensor the output of the second date The clock tick is connected to the second input of the OR element.

The drawing is a structural diagram of the proposed device.

The device contains encoding blocks 1 and 2, decoding blocks 3 and 4, the first control block 5, second control block 6, elements OR 7-10 switch 11, request signal sensor 12, request signal receiver 13. The coding and decoding blocks contain registers (with feedback) 14-17, elements AND 18-21, the first sensors 2225 of the clock frequency, the second sensors 26-29 of the clock frequency, and elements OR-30-33, respectively.

The proposed device works as follows.

Information to be transmitted from the input 34 of the device through the elements OR 7 and 8 is fed to the inputs of the registers (with feedback) of the coding blocks 1 and 2 and through the element OR 9 to the output 35 of the device.

The first control unit 5 controls the control signals to the coding units in such a way that only one frequency sensor works in each code pattern in each coding unit. F or p F, and they are switched at the end of each code combination, while the first sensor 22 (F) of the clock frequency is connected to the coding block 1 in the coding block 2 the second sensor 27 (pR) of the clock frequency is connected, and vice versa , when sensor 2b is connected, sensor 23 is connected. Signals from frequency sensors 22 and 26 are connected via OR element 30 to a clock input register (with feedback), whose information output is connected to information input And 18 of the sensor signals 23 and 27 through the element OR 31 are connected clock input of the register (reverse

connection) 15, the information output of which is connected to the information input of the And 19 element. The elements 18 and 19 are controlled by signals from the first control block, the NIN so that after the end of the arrival of the information symbols, an element of that of the encoding blocks 1 or 2 opens, a register (with feedback) of which is currently running at the frequency F of the information input. From the output of the elements 18 and 19, the check characters through the element OR 9 are fed to the output 35 of the device, and through the elements 7 and 8 to the input of the register (with feedback),

5 which is currently operating on the p-Fa frequency. The output of test symbols to the transmitting communication channel is carried out in a strictly defined sequence of encoding

0 blocks 1, 2, ... m. After the end of the output of check symbols for each code block, before the arrival of information symbols, the clock frequency sensors are switched.

At the reception, the order of the output of the check characters from the decoding blocks 1, 2, ... t and, respectively, is set to be transmitted, respectively,

 the symbols of each code combination switch clock sensors.

From the input 36 of the device, information and check symbols received from the .1C.LASI channel are fed to the input of the switch 11 and the inputs of the registers (with feedback) 16 and 17 of the decoding units 3 and 4. Registers

(with feedback) 16 and 17 decoding blocks work in an analogous way to the registers (with feedback) of the coding blocks, while at the time of outputting the test characters the input of the corresponding register is disconnected from the output of the receiving communication channel,

The second control unit 6 provides control signals similarly to the unit

5 controls in such a way that

Each code combination through the elements OR 32 and 33 to the clock inputs of the registers (feedback) are connected to the sensor 26 of the frequency F and, accordingly, the sensor 29 of the frequency p -F

or sensor 28 frequency p-F and, accordingly, sensor 25 frequency F. In the output mode of the verification symbols, the decoding blocks operate at the frequency G. , with

Claims (1)

SUMMARY OF THE INVENTION A device for error protection in a transmission system with decisive feedback by auth. No. 728153, which is characterized by the fact that, with 5, for the sake of simplicity, the coding and decoding blocks consist of a register, clock sensors, an AND element, and an OR element, while the information input of the register is the second · 1Q input of each encoding unit and the first input of each decoding unit, the register output is connected to the input of the And element , the output of which is the output of each encoding and decoding blocks, the clock input of the register is connected to the output of the OR element, the first input of which is connected to the output of the first clock sensor, the output of the second clock sensor Toty 20 is connected to the second input of the OR gate.