SU807258A1 - Device for interfacing computing system modules with check - Google Patents

Description

. . -.G IoBreGenie ognosigs to the computer technology can be used ;. designed by computational methods, . ; A device is known that contains a set of passive wires connected by two-way communications with modules of the deactivating system, control blocks of buses, and a communication unit with bus 0. A disadvantage of this device is that the combined tires are message transfer period between the pair. which reduces the bandwidth M "N. Doules. It is also known that the device is an eq-holding set of passive wiring s01 | a | 1, control 1env ,, connected to the “first two | They are connected with the modules of the computing system of the system, - with the atom transferring information between the modules are performed in the time division mode | 2. The disadvantage of the device is an increase in the time of the lagging process, as paouttrei computational from the system. The most common thing offered by technical dryness is a communication device that connects two-way information and command links to computer system modules. Roderch Jashee first reception registers, first transmitting registers, the first set of passive data buses, addresses in the control of the synchronization block and, the controller vl reira pixels, the valve nodes, the first nodes of the analysis registers afes, uthavfuu (Vestry, the first buffer registers I first elements OR, the first information inputs of which (x, through the first reception registers, are connected to the corresponding synchronization control output, first control of the pulse distributors, the first outputs of which are connected to the valve nodes The first control CC moves of the valve nodes are connected to the control inputs of the first transmitting registers, the information & outputs of which are connected via the first set of pass data buses, the control addresses are connected in accordance with the first receive registers and through the first buffer registers connected by double-sided information communications with the computer system modules, the control outputs of which are connected to the first control inputs of the control registers, the second control inputs of which are connected to the nodes in The vents, the information outputs of the control registers are connected to the first information inputs of the bridges, the gates, the second control outputs of which are connected to the control inputs of the first analysis nodes, the first information inputs of which are connected to the address registers and the first buffer registers, the first control inputs which are connected to the third control outputs of the valve assemblies, the fourth pilot outputs of which are connected to the control inputs of the modules of the computer system However, despite the fact that this device allows you to increase proiaa: the water system, maintains its regularity, it has the only way to transfer information, which does not allow to ensure high reliability. The latter is very important for a number of applications, especially for a real-time system. The aim of the invention is to increase the reliability of the device. The goal is achieved by the fact that the device for interfacing the computer system modules with the control, which contains the first group of receiving registers, sends the transmitting registers, a synchronization unit, a group of pulse distributors, the first group of address comparison blocks, a group of address registers, a control register group, the first the buffer register group, the first group of elements OR. The control unit has control signals, the first output of the synchronization unit is connected to the first inputs of all pulse distributors of the group, the second output of the synchronization unit is connected to the second inputs of all pulse distributors of the group and to the control inputs of all receiving registers of the first group, the first and second outputs of each distributor the pulses of the group are connected to the first and second synchronizing inputs of the corresponding block of the control signals of the group, the first output of each block of generation of pack Aulus constituent signal group is coupled to a control input of the respective transmitting register of the first group, the output of each transmitting -K-th register of the first group soedi-. It with the first information input of the 1st (-th buffer register of the first group and the information input of the (X + 1) -th receiving register of the first group, the second information input -k-ro of the buffer register of the first group is the first input of the device, the information output of each register the group address is connected to the first information input of the Corresponding block comparing the address of the first group n to the third information input of the corresponding buffer register of the first group, the information output of each receiving register of the first group with single with the first input of the corresponding element OR of the first group and with the second information input of the corresponding block comparing the address of the first group, the output of each element OR of the first group is connected to the first information input of the corresponding block of generating control signals of the group, the second, third, fourth output outputs of each block the generation of the control signals of the group are connected respectively to the control input of the corresponding comparison blocks of the first group, to the first control "cops of the control group register, with the corresponding output ycTpcrftcTBa, with the corresponding input of the corresponding buffer register of the first group, the information output of each control register of the group is co-. With the second information input of the corresponding control signal generation unit, the second control inputs of each control register form a group of control inputs of the device, the line control unit is entered, the second group of reception registers. The group of switching blocks, the second group of transmitting registers j the first, second and third groups of error detection blocks, the VT-ora group of address comparison blocks, the second group of OR elements, the group of fault counters, the decoder group and the second group of buffer registers, the information outputs of the last transmitting registers first and the second group are connected respectively to the first and second informational inputs, the main control unit, the first and second control inputs of which are connected respectively to the first and second terminals a-, m sync block, the first and second

Basar Kotapota’s external information outputs are connected to information inputs of the first direct registers of the first and third groups, the output of each receiving regisgra reps group is connected to the second input of the corresponding element OR of the first group, with the first input of the corresponding block of the BTjjj address address comparison section BTjjj, or the first group, with the first input of the corresponding section OR of the corresponding group of the BTjjpljlvlslvslplgrvsvlrvsrvsrvsvlrvsfxvrstr. The fourth inputs of each switching group are connected respectively to the information inputs of the corresponding, one “many” register of the first group, with the output corresponding to of the receiving group of the first group, with the information input of the corresponding receiving register of the second group, with the output of the corresponding receiving register of the second group, the control inputs of all the receiving registers of the second group are connected to the second output of the synchronization unit, the first and second information outputs of each switching unit are groups from the second, respectively with information inputs of the corresponding transmitting registers of the first second group, inffma K80NNY output of the th transmitting register of the second group of connectors not with the information input (it + l) -ro of the reception register of the second group, with the information input of the fc-ro buffer register of the second group, the information output of each buffer register of the second group is connected with the fifth information input of the corresponding buffer register of the first group, The first, second and sixth outputs of each control signal generation unit of the group are connected respectively to the control input of the corresponding transmitting register, VAS group, to the control input of the corresponding address comparison unit. the group in the control input buffer register of the second group, the information output of each register a; the second group, the output of each element OR of the second group is connected to the control input of the corresponding control register of the group; the seventh output of each unit is the generation of the control sagnalov group connected to the input of the counter groups corresponding failures vyhs Cage (

The second fault counter is connected to the corresponding input of the group decipher, the output of each group decoder is connected to the third input of the corresponding control output unit

groups, information outputs of each transmitting register of the first and second groups are connected respectively to the inputs of the error detection blocks of the first

, and group VSS, the outputs of the error detection units of the first and second groups are connected respectively to the fourth and fifth inputs of the corresponding control signal generation unit, the third

the output and fifth input of each switching unit of the group form respectively the first group of information inputs to the second group of information inputs of the device; the output of each buffer register of the first group is connected to the information input of the corresponding error detection unit of the third group and the third input of the corresponding control unit ,

the output of each error block of the third group is connected to the sixth input of the corresponding block of control signals of the group.

The line control unit contains

first to second receiving registers, first and second error detection nodes, failure correction node, OR element, AND element, counter, AND group of elements, comparison circuit, first and second transmission registers, pulse distributor.

the group of elements OR, the first and the second ones in the mode control node, the first and the second information inputs of the block are connected to the information inputs of the first to the second receiving registers, the control inputs of which are connected to the first output of the distributor vmuls in synchronizing inputs the output of the first one (the fwem register is connected to the input of the first error detection node, with the first terminals of the mode control node, the cms node; 1) the failure condition, with the first input of the OR element at the first input of the first switch torus, the output of the second receiver

the regvstra is connected to the input of the second node of the error detection node, with the input to the mode control node, the OR element, the failure correction node in the second input of the first switch, controlling

Into the dual outputs of the first to the second detection nodes (they are connected to the first and second u respectively the first in the informational |

and the second switch, the first and second, are right; the outputs of which are connected f respectively to the control input of the evil to the erection of failures and to the first control inputs of the elements AND of the group, the output of the node x to the reccni of failures is connected to the first information inputs of the elements I of group 1 the first and The second outputs of the mode control node are connected respectively to the second inputs of elements AND groups, to the first inputs of elements OR groups, the first, second, third, fourth and fifth outputs of the elements AND groups are connected respectively to the first input of elements This AND, with the control input of the counter, with the second inputs of the elements of the OR group, with the control input of the first and second transmission registers, with the information input of the first and second transmission registers, the outputs of which are outputs of the OR element are connected to the input of the element And, the output of which is connected to the counting input of the counter, the information output of the ochechchyk is connected to the input of the comparison circuit and with the second in-circuit inputs of the elements -A group, the output of the comparison circuit is connected to the third inputs of the elements of the group I, the second kmpulsoa distributor output connected to the control BxoiaoM first switch element outputs are connected to the OR group Treg ° m kiformatsionnym and second control inputs Vågå kommutags lane a, tear and which outputs vtorsL seDnneiy soogvegstvenno with vtorymv ngnformaaionnym inputs of said first and second transfer registers.

The error detection block contains a group of convolutions modulo two, a group of the element I, a threshold element in the deshi ({rator, the convolutions for the two groups are connected to the inputs of the block, the outputs of the modulo are two groups, respectively, are connected to the first elements of AND groups, the second inputs of which are connected to the input of the lower order of the ion block, the outputs of the elements and the group are the information outputs of the block connected with ° the corresponding inputs nqjoroBoro of the element in the descrambler, the output of the scraper is the control output one bolshka, the output of the thresholds of the control element, with the control input of the decoder .:

The switching circuit contains the first, second, third, and fourth elements of OR, first, second, third, and fourth. the elements And, with the first, the second.

the third and fourth information inputs, dyes are connected respectively to the first input of the first OR element, to the second input of the first OR element, s.

the first input of the second OR element and the second input of the OR element, the first and second outputs of the first and second OR elements, respectively, are connected to the first inputs of the first, second, third and fourth elements AND, all the inputs of all AND elements are connected to the control input block, third. the inputs of the first and third elements And are connected to the second input

5, the third inputs of the second and fourth elements And are connected to the fourth input of the block, the outputs of the first, second, third to fourth elements AND are connected respectively to the first and eye inputs of the third and fourth elements OR, the outputs of which are the outputs of the block the fourth OR element is connected to the fifth information module by the ion input of the unit.

5 In FIG. 1 shows a block diagram of a device for interfacing modules of a computing System with a 1 control | in fig. 2shema block railway control; in fig. 3 is a schematic of an error detection unit; in fig. 4 - diagram of the switching unit.

The device contains a synchronization block 1, a flea 2 KOHTp nfi trunk, the first group of reception registers 3,1Z .Р, vtf group of reception registers

, 4.1-4. Р, first elements OR 6.1-5. Р, switching group 6,1-6. Р switching, the first group of transmitting registers 7Л-7.Р, the second group of transmitting regist | | 8.1-8, Р set

8 passive lumi address and control data, the second set of 1O.1-1О.Р passive tires Dvvies, vfesa and control, the first group of Vkukov I, 1-11.

j 12.1-12. Р error loading, third group 15.1-13.Р error detection, valve group 14.114, Р impulum first group, bljov 15. l-lSi.P comparison, second

- ipynna le. 1-16.P, address comparisons, second group of elements OR 17.1-17.R, group of registers 18.1-18.R, group of blocks 49.1-19.R failures, the group of decoders 21, .Р, the group of control registers 22.1-22.Р, the first group of reg.isgrov 23.1-23.R, the second group of buffer registers 24.1-24.Р

The modules 25.1-25.F of the computing system .MbliBlock 1 (FIG. I), which contains the generation () of clock pulses, the reset, start-stop nodes and the control panel, are designed to reset the device, start it and synchronize . The unit generates two series of synchronization signals A1 and B1. Seri A1, supplied to the second control output of the synchronization unit 1, is fed to the second control input of the line 2 control unit, the second control inputs of the pulse distributors 14.1-14, P, groups, the control inputs of the receiving registers of the first 3.1Z. 4.1-4iP groups. The distributors 14.1-14.R of the pulses of the group in response to the signal A1 produce the sequence A2, A3, and in response to the signal B1, respectively B2, VZ, B4. The minimum time between signals B4 and A1 depends on the element base used and can now be units of nanoseconds. The first control output of the synchronization unit 1 is connected with the first control of the main control unit 2 and with the fifth control inputs of 6.1-6-6. P group

 Generally registers of the first 3.1-Z.R and second 4.1-4.P. The groups that transfer the registers of the first 7.1-7. P and the second 8.1-8. P groups are associated respectively with the U) with the first 9.1-9. P and the second 1O, 110, P sets of passive women and include

. the nodes of the discharge, recording and issuing information. ,;

Etna registers are preassigned for temporary storage of information dynamically moving from receiving registers 3.1 to 4.1 and transmitting registers 7.P., 8.P. ..

Information inputs and outputs with registers 3.1-З.Р, 4.1-4.Р through blocks 6.1-6.Р. commutations are associated with transmit registers 7.1-7.P, 8.18 .P, Transmit register registers

7, P 8, P are connected to the information inputs of the main line control station 21.

The information outputs of the transmitting registers of the first 7.1-P.P. and VTS 8.18, P groups are connected respectively to the inputs of the detection blocks of the first 11.1-11, P and second 12.1-12. the second is 24.1-24.P groups containing drop nodes, recording and extracting information, and is designed: to receive information from the ma-.

the gistral, its temporary storage, rewriting of new information from the modules 25.1-25. Р and its data through the blocks 6.1-6. Р switching.

Information from receiving registers 3.1-3, P, 4.1-4. P is sent to transmitting registers 7.1-7. P, 8,1-8. - control bits). The information part of the word contains the following gender:

- the sign of the control word about the module, if it is not in this category, then this word of the control module performing diagnostics operations, b, otherwise, are layers of the executive module; - the loop counter given by p. ope is loaded by the active module at the time the word is sent to the trunk; contents of data bits pp. indicates the number of permissible full passes of the given word along the line without detecting a popucha body {, - - sign of the word state - occupied /

/free; aares recipient; -And shipper; - data (this field indicates the module status, or asychus of the memory cell, or the address of the destination register, etc.)} - mode: write, read, i. This is the mode of processing the floor of this mollemepopuchatelek. fail

 The bits of the signs of the word of the utf module module and the signs of the state of the word from the outputs of the elements OR 5.1-5. Р of the first group arrive at the inputs of the blocks 19.119. VTS1 4.1-4. P groups arrive at the inputs of the first address comparison blocks 15.1-15. the second 16.1-16.R groups, containing sets of AND, OR elements, intended for recognizing the module's own addresses, by comparing WIA a; C} of recipients with their own collections stored in address registers 18.118GR, including manual setting circuits addresses. Managing results of bsshx: addressing address percA; 15.115. Р and BTdpoft 16.1-16.Р groups through. the OR elements 17.1-17.P of the second group are associated with the control registers 22.1-22.R groups that are also connected to blocks 19.1-19. P generating control signals for the group and include triggers with write and reset nodes and are used to indicate states and modes of operation of the device. The units 19.1-19.P of generation of control signals of the group are also connected to serially connected counters 20.1-20.P failures of the group and remote controllers 21.1-21.P groups that are jointly intended to register the number of incorrect information transfers from the 25Л-25 modules. P to buffer registers 23.1-23. P of a pei group. The device is connected by two-way information and command links to modules 25.1-25. Р of the computing system, which can be used as central processors, input-output processors, interlocks RAM. . Block 2 co11g line 1, 2) is designed to monitor and recover information circulating on the highway; detection of messages that were not received by the recipients for various reasons (failure in the recipient's address, multiple failures in messages that cannot be eliminated by instrumentation tools, and retransmission of the message or an interrupt to the pack is required; modules, etc.). The line control unit 2 contains the first receiving register 26, the second receiving register 27, the first node 28, error detection, the in-progress error detection node 29, the second switch 3Q, the failure correction block 31, the mode control node 32, the I & D element group, the pulse distributor 34, the element OR 35, the element AND 36, the counter 37, the comparison circuit 3S, the first switchboard 39, the group of elements OR 40, the first transmission register 41, the second transmission register 42. The first 26 and second 27 receiving registers are identical, contain sets of triggers for storing information, a chain of entry, output and reset of information and are designed to store the received information during the time it is processed in block 2 of the main control. The information output of the first receiver b of the register 26 is connected to the first information input of the first switch 39 by all bits, the waves that are a cycle counter to the first information input of the element S 812 OR 35, the bit determining the load of the receiving register 26 and the word sign of the control module is discharged to the first information input of the mode control node 32, the information output, the course of the first receiving register 26, all bits, except for the counter of cycles, occupation signs, word sign control unit, coupled to the data input of the first node 28 and the first error detection informatsisinym input correction unit 31 malfunctions. In a similar way, the second receiving register 27 is connected with the first switch 39, the TLI element 35, the mode control node 32, the second error detection node 29, the fault correction node 31. .The first 28 and second 29 error detection nodes are identical with each other and with the AND blocks, 1-11. Р 12.1-12. Р, 13.113. Р and each of them contains (fig. 3) a group of convolutions 43.1- 43.4 modulo two, AND group 44.1-44.4, nqporo element 45, decimal 46, and prad is intended to detect double and single errors in the message, generate a code to determine the position of the discharge, and then invert with a single error to restore the message code, and outputting these signals to the second switch 30. The information input of the error detection node 29 is connected to the information The ion inputs of the convolutions 43.1-43.4 are modulo two groups, the output of which, respectively, are associated with the first inputs of the elements AND 44.1-44.4 of the group, the secondary inputs of which are respectively connected to the younger H-information will give information about the input Oshkbszh detection unit 29, the outputs of elements AND 44.1-44.4 of the group are connected to the inputs of DF 46, the information output of the error detection node 29 on the input element 4 5 5, which is passed through to the remote 4 output of 29 error detection . Convolutions 43.1-43,4 Modulo two groups are a set of combinational schemes AND, OR, NOT and are intended to check the parity of certain sets of TREATMENT of a message code, for example, the first convolution 43.1 controls all odd code values and outputs the result of the control resolved only if the wider data bit of the code is equal to, in the (fake case, the output of the first. And group 44.1 is set to O). Only one corresponding check bit is supplied to each convolution modulo two. according to the first convolution 43.1, the remaining (h-1) convolutions 43.2-43.H groups were completed. D1Rogovy. Element 45 contains input circuits and a threshold element that includes a multiple-fold signal: if its input is from AND 44.144 elements groups receive more than one signal about the failure of the control groups.The Schmitt trigger, for example, can be used as a threshold element.The decoder 46 contains a set of AND, OR, NOT elements and is intended for issuing control actions based on the results of the message control No failure A single failure Repeated crash w The second switch 30 (fig.2) contains a set of AND, OR, NOT schemes in which it is determined from which receiving register it is necessary to transmit information to the first switch 39, if it is reported {e has no errors in one of the receiving registers, as well as the need for | message code corrections using the fault correction node 31, if there is a one-time error in both receiving registers, or a one-time error in one and multiple in other receiving registers. In the second commutator switch, using the decoder, to which the error position code is supplied from the corresponding error detection node 28 and 29, the decoding code measures the position of the message code that you need to invert in the dSoeB correction node 31. The second switch ZO of the control output is connected to the fault correction node 31, and this output is the output of the error position code decoder on the output outputs, where n is the number of bits in the message, h is the number of redundant check bits. The fault correction node 31 contains a combination logic of AND, OR, H elements identical for each of the n bits of the message, which implements the inversion of one of the bits, subject to the condition of times. address correction code messages from the second switch 30. The first control output of the second switch 30 is connected with the third control input of the group of elements And 33. The group of elements And 33 is designed to work on the posleavlivayasti signals to move the message in directions determined by the outputs of the node 32 the mode control, the comparing modem 33, the second commutator 8 814 pa 30, Hjynna elements 33 and the control inputs are also connected to the mode control unit 32, the comparison circuit 38, the control inputs of the receiving power sources 26 27 and 34-pulse limiter. The communication of the second switch 30 and the group of elements And 33 consists of a series of tires, which send signals to the group of elements 33 and the direction of movement of the message, as well as the need to write a message flag for the control module to the transfer registers 41 and 42. A group of elements And 33 information inputs associated with the information outputs of the node 31 error correction message bits) and information output of the counter 37. The control outputs of a group of elements And 33 associated with the element 36 for control code entry in the counter 37 , counter 37 for subtracting it, if its contents are not zero. The information outputs of the group of elements AND 33 are connected by all bits of the total, through the group of elements OR 4O with the first switch 39 and the code bits of the counter 37, with the first 41 and all 42 of the transmission registers. The distributor 34 pulses identical 14.114, P. The control inputs of the pulse distributor 34 are associated respectively with the control inputs of the line control unit 2, and the second control output of the pulse distributor 34 is connected to the first square switch 39. The mode control node 32 contains a set of AND, OR; control signals stitching the mode of operation of the line 2 control, in particular the message transfer mode for the control module, the zero word mode, the message transfer mode for the non-control module. The OR element 35 contains a set of OR circuits by the number of counter bits and the information output is connected to the AND 36 element and is predicted for assembling the counter of the same name from the first 26 and second 27 receiving registers. The element 36 for transferring the contents of the bits of the counter of the cycles of the receiving registers 26 and 27 to the counter 37 is connected by an information link with the counter 37, which is connected to the comparison circuit 38 by an information output; for determining the zero value of the counter 37. Scheme 5B of the regulation includes a set of schemes I.

irjpynna of the elements OR 40 are intended for transmitting control and information signals to the first communigor 39. G {) the wapa of the elements OR 40 is connected with the first governing input; with control output of node 32 of mode control and control output — with first switch 39. First switch 39 contains sets of OR, AND B circuits for performing message transmission from the first 26 to the second 27 receive registers respectively to the first 41 and second 42 transfer registers, provided there are no errors ;, transferring the contents of the receiving register, in which the correct message to both registers 41, 42 is located; transferring the shipments from the group of elements OR 40 to both the registers 41 and 42 of transmitting the corrected message code, if at least one of the receiving registers had a message with one error and could have been restored, the First switch 39 was first connected to the first information outlet in the upcoming 41 and second 42 regisgrams transfer.

The first 41 and the transfer registers 42 are similar to the receive registers 26, 27 and are designed to store the message at the time of transfer to the subsequent magisgraf receiving registers. The information outputs of the first 41 in the second 42 registers are transferred respectively to the first and second information outputs 2 k (magnetral grill. The control inputs of the transfer registers 41 and 42 are connected to the fourth control of the output of the group of elements And 33, which are used to set an unrecoverable sign in the corresponding bits and messages for the control module.

Blocks 6.1-6. P switching (Fig. 4) are designed to control information and increase its reliability with interregister ropes, which is achieved by automatically sending the correct information from at least one receiving register Z.K. 4.K, IB both transmitting registers 7 .K, 8.K. The .th block 6 .- (with switching includes the first element OR 47.1c, the second element OR 48 ", the first 49, the iLi the second 5О.С, the third 51-К and the quarter 5 2.1 And elements, the third Z.i the fourth 54.teement of OR. Infor- mation; from the output of the receiving register Zi enters the input of the first element OR 47, k where it is checked with the help of the excluding IDN for equality

with the information coming from the input of the receiving-register 3. k to the second information input of the first element OR 47J; Depending on the result of the comparison, the information is sent to the transmitting register 7. k comes either from the receiving register 3. The first group through the first element AND 49.iiH element OR 53ж, or from the receiving register 4.k of the second group through the second element AND SO if. and the element OR 53. The secondary half of the switching unit 6 1c includes the receiving register 4 of the second group, the second element OR 4Sifc the third 5 l.-fc and the fourth 52A elements AND, the fourth element OR 54 R, has the same functionality and the same connections as the first half block.

The device works as follows.

Modules 25.1-25. Computer systems exchange information words & and make decisions on failures.

Functionally, the device for interfacing the modules of the computer system with the control (Fig. 1), excluding block 1 and bluff 2 to 1 track of the main line, can be divided into P identical parts by the number of modules 25.1-25. P of the computing system. The operation of the device will be considered in the example of the work of the ith part of the device together with the synchronization unit 1 and the highway control unit 2.

Upon device start-up, the synchronization unit 1 begins to generate both series of A1 and B1 signals, under the control of which free words begin to circulate in the trunk. With each B1 signal, the contents of the receive registers 3.1-Z.P, 4.1-4.P are transmitted through blocks 6.1-6. P switching to the transfer registers 7.17 .P, b.1-8.P. With each signal A1, the information of the transfer registers 7.1-7.P, 8.1-8. P is sent to the reception registers 3.1-Z.P, 4.1-4.P,

 Each part of the device can operate independently in one of the three modes.

Claims (2)

- Record - Transfer of the word infq information from the computer system module backbone} -read (control mode) - with the word information from the backbone to the control module; - reading (executive mode) receiving information from the trunk by the executive module.  When reading (executive mode ICP) signal Reset control register 22. 1c is set to: Free), Read (Thu), ICP. According to the signal A1, the contents of the transmitting registers 1.  -18. fc. The -l is sent to the receive registers 3Ji, 4, respectively. ;.  The signal A2 and the state of the control register 22. . -k- Sv, Cht, SPI and the absence of the sign of the word of the control module at the output of the first element OR S. ic of the first group is arbitrary polling of address comparison blocks 15 (,.  On the signal Equals, t. e.  comparing the module's own address with the recipient's address, the output of the OR 17L element is set to the corresponding trigger. in the 22fc register. There is no action taken on the signal. No paako.  .  On signal B1, the contents of the registers 3,4s, 4. -k parallel to all bits through the switching unit 6.  enters the thinning registers.  7 -fc, 8k.  Forwarding to receiving registers 3k.  4i: controlled by elements OR 47. 4c and 48. one; in this case, if the information in both registers is correct, then it is sent to the transfer registers 7. 1, 8 k through the elements And 49. S 52jf.  If, for example, the information in the receiving register 3. .  t is incorrect, and in the receiving register 4. ic- correct element OR 47. 11 opens the AND 5Qi element with its control code to the transmitting register 7. c, the correct information will be transmitted from the receiving register 4, and an automatic bypass of the failed receiving register will be performed.  In case of failure of both receiving registers W,, 4. 1c, the information contained therein is sent respectively to the transfer registers 8.  fi, 7L and in the D191st modest is processed in block 2 of the control line. .  , : Information in the Hamming code, received in transmitting registers, 7. 18. 1: controlled by blocks 11. K, 12. k error detection  The control is carried out as follows, i the information from the transmitting register 8 "1 (, is supplied by the potentials of all bits-to the input of the block 12. if error detection.  (FIG.  3), and in each rygku 43. 143. The modulo-group contains all information bits and one corresponding control bit.  Younger information bits are fed to the second inputs of the And 44 elements. 1-44. 4 groups, at the first entrances of the coaches, the results of parity are given, respectively.  relevant test groups.  If there is a failure in one of the h checking groups e. This failure is detected by the decoder 46, which gives the signal a single failure, and the position code of the message bit is sent from all AND 44.1-44 elements. 4 groups per informational output of the error detection unit.  . In case of multiple detection Onibudut sa errors: recorded in several convolutions of the group and at the outputs of the corresponding elements And 44. 1-44. H set the levels of failures that arrive at the porgary element 45, which is triggered by the arrival of more than one sagas.  Nala with elements And 44.1-44. H / group.  Over the threshold.  element 45 through the decimator 46 is fed to the output of block 12, detection of an error in the form of a signal MnS okratny malfunction.  : If there is no failure in one of the transmitting registers 7. 11, 8, c (FIG.  1) or voboih transmitting p and insure 7.  k, 8.  k, then according to the state of the Equivalent Signal B2, the phase transfer of the correct information IJ3 of one of the transmitting registers 7 is performed. 1c, It to the buffer: register 23.  -C of the first group.  Next, both transmitters — p HisGrov 7 are reset. - and 8. - on signal OZ, as well as the transfer of the control register 22. 1 in the Zanto (ZnT) and Record (Zn) states, in module 25. 1cc block 19. The control signal generation is requested to transmit information from the buffer register.  ra 23it.  Upon receipt of the request, module 25 generates data from buffer register 23.  k.  Bleach the result xyzhrol - Multiple tap in one of the transmitting registers 7. , eight.  and a single failure in another transmitting register, then by the signal B2. information from the register, a one-time hit occurred in jcoTopoM, is fed to the buffer register 23.  It and, on signal A3, paraphase is entered through block 6. fc switching in both transmitting regisgra 7.  fc and 8.  k, state Equal.  Ec; jH control result - Multiple failure in both transmitting registers 7. 1c, 8.  i, then by the signal B2 in the bits of the sign of the word of the control module and the failure of both transmitting registers 7. k, 8.  skidding units.  This means that the received faulty information is addressed to the control module for further processing.  When reading (Control mode) on the state of Th, Sv, Control and the presence of T in the word bits of the control module, A 2 signals, the control word trigger (Tue) is set in control register 2i2. 1c Signal B2 transmits the contents of both transmitting registers 7,1s, 8 according to the conditions Tue, Thu, Sv.  1c without control, respectively, in the buffer registers of the first 23.  k, and second 24, It.  groups.  The OT signal of the previous states clears the registers 7Jfe 8.  transfer of control register 22.  K in the ZnT position, development of a request for information transfer in 25L upon receipt of a polling signal of the buffer register 23.  It and the state of the control register 22. To - Th.  Znt, Tue buffer register contents 24.  transferred to buffer register 23. - (s, it is done, the translation of the governing regasgra 22 is effected. -k in the state Sn, a request to transmit is generated, to the module 25 | in the second word of information.   records - request from module 25.  V to transfer information to the trunk usn “fails to trigger: Over the tip in the control registry 22.  k.  Signal A2 on each other with M zp, ZNT, Zapr information from module 25. 1 is transferred to the buffer register 23, it also receives its own aPopQO module 25 at the same time.  {from parksstra 18.  Madras.   By the signal A3, depending on the values of the rvzdov mode (write, read), in apov, received in the buffer register 23. t, processing may be performed. two to   Two mode bits can be simultaneously set only by the control module for the purpose of diagnosing the master,. In this case, the sender's address in the word is set equal to the address of the recipient and equal to his own address.  A word may contain correct or intentionally faulty information, which is necessary for control purposes.  In view of the foregoing, when the mode bits are set, it is required to prohibit the control of information on the recording performed by block 13. 1s.  error detection, the third group.  If the mode bits are set, then according to the signal A3 and the state Zp, Znt, Zapr, the analysis for busy is performed in block 19. 1c generate control signals.  If the word is free, the TSlv trigger is set in control register 22.  fc, using the above states, the signal for polling the result of monitoring information in the buffer register 23.1; is blocked ;.  If the mode bits are not set, then the signal A3 in the states Zp, Znt, Zapr made an analysis of the word for busy and interrogate the result of monitoring information of the buffer register 23. coming in blszh 19, k generation of control signals from 13.  -k detect a card  If the word is occupied, then ft is not missed, on signal 82 no action was taken.  If the word is free and there is no failure, then on signal B2, the contents of the buffer register 23. -k, paraphasic through block 6. -k switching in both transmitting registers 7.  fc ,, 8, -fc.  Next, the TZ signal clears the buffer register 23.  fc and translation of the control register 22.  ".  on Thu and St.  If block 13.  error detection reveals a failure, then the signal B2 in the counter 20, failure is added, Next, if the contents of the counter 2O.  t failures is not equal to the value of f, where f is the permissible number of repeated failed transmissions of information from module 26. fcB buffer register 23, (from, then to. The OT signal is reset to register 23.  To and sent a request to the module 25, -fc to re-receive information.  If a failure is detected and the contents of the counter 20.  k failures equal to the value of f and slsuo freely, then by the signal OZ the contents of the buffer register 23. 1c is transmitted to both transmitting registers 7. C, 8,1, simultaneously establishes the sign of the word of the control module.  This information will be analyzed further. n processed by the control module.  As of Sn, the contents of the counter are 2O. four(.  Failures are equal to φ and the word is freely produced by an RF signal;  t and control register translation 22.  t state is Th.  The module has transmitted information to the highway and is ready for a new information from the highway.  The information transmitted over the trunk is controlled by the control unit 2 of the trunk, (FIG.  1), which works as follows.  The signal A1 transmits information registers 7. R, 8. P is shifted to receive registers 2 and 27.  The outputs of the receive registers 26 and 27 all by bits arrive at the first switch 39, the bits of the word status indicator (occupied, free) and the word of the control module go to the mode control node 32, where the corresponding control signals are generated. 26 and 27 times the counter-cycle rows are sent to the OR 35 element, the remaining bits of the receive registers 26 and 27, covered by the Kohm Hemming1a control, go to the first 28 and second 2Q error detection, respectively, and to the inputs of the fault correction node 31.  The combination schemes of the mode control unit 32, the error detection elves 28 and 29, trigger and send signals to the second switch, TCf 30, the group of elements 33 and the group of elements OR 4O.  Then, the second ZO switch circuit is processed, the KOTopcwo outputs go to the fault correction node 31 and the I 3 group of elements. 3, Thus, the combination schemes are adjusted to the mode corresponding to the content of the received word.  At the same time, three modes of operation of block 2 kshtrol highway are possible.  The first mode is the word transfer mode for the control module. .  The bits of the sign of the word of the control module are analyzed in the node 32 near the board, mode.  EU If these are the words of the control module, the mode control unit 32 prohibits the operation of the group of elements AND 33 and permits the transfer of information through the first switch 39 from the receiving register 26 to the transfer register 41 and from the receiving register 27 to the transfer register 42.  The transmission is carried out by the signal B1 arriving at the first switch 39 ve of the distributor 34 pulses.  The contents of the transfer registers 41 and 42 are transmitted to the receive registers B1, 4.1 by the signal A1. - The second mode is the word transfer mode for the non-controlling module.  In this mode, SLOV9 poppezhit. control for the presence of failures and in case of their detection -: recovery.  The first error detection node 28 controls the contents of the receive register 26, the second error detection node 29 controls the contents of the reception register 27, and the control results are fed to the second AO switch.  At the same time, if there are no errors in any of the receiving registers 26 and 27, then from the second switch AOR, to the group of elements And 33, a signal of direct information transfer from the receiving registers 26 and 27 is supplied through the first switchboard 39.  Transmission registers 41 and 42 and from the mode control node 32 are also included in the AND 33 group of elements. This transfer is performed by the signal B1, similarly to the first mode, the ECU1H one out of the error detection nodes 28 and 29 indicated a failure in corresponding to the receive register, then, from the second switch 30, the group of elements AND 33 is transmitted. signal to open the relevant schemes so that using a group of elements OR 40. ".  the first switch 39 to transfer a message from the receiving register, in which there is no error, to both transmitting registers.  The operation of block 2 occurs in the same way if one of the nodes 28 and 29 of the error detection detected a door (multiple) error in the corresponding receiving register, and there is no error in the other receiving register.  Such control and transmission allows you to remove information from the highway and replace it with the correct one, thus, by the very PS, to identify the accuracy of the game.  If the 2S and 29 error detection nodes have detected faults, and there is a one-time error in one of the receiving registers, then the words are next to | (:: so. recovery.  In this case, the second AOR switch covers the error code osmiBR error that decrypts the appropriate code 28 ipb 29, decrypts the code and gives the code (fowers (1 position number to the corresponding bit B 31 invert the corresponding bit B word.  According to the second alphabet (second output, the second commutator switches the signal to the group EL 33 And to open the corresponding circuits for transmitting the corrected word code through the group of OR 40 and first switch 39 to both 1) register 41 and 42.  Mating is carried out by signal B1.  If the control of receiving registers 26 and 27 by nodes 28 and 29 detecting errors by the AI showed the presence of multiple 1x breaks in the error, showed the presence of multiple cuts in S0 of both the direct registers 26 and 27, then the word is not subject to recovery and is not necessary.  Send it to the control module.  In this case, the second switch; the AOR AOR sends to the group of elements And 33 a control signal about the direct transfer of the word from the receiving registers 26 and 27 through the first switch 39 to the registers 41 and 42 of the transmission by the signal A2 and zapn.  word flag for control and unrecoverable fault sign into corresponding bits of transmission registers 41 and 42 on signal A3.  At the same time, with the control of words for errors and their recovery in the case of single errors in the control unit of the line, each word for the unmanaged module is checked for the number of cycles that the message went through the line, t. e.  how many times the message was forwarded through block 2 of the control line and was not received by the recipient.  This number can be set arbitrarily from O to) where and is the number of bits of the count of 37, If the contents of the loop counter is zero, the word is not accepted by any of the system modules and invalid recipient addresses are possible, therefore, to determine the reason for this word the trait for the control module is written down, thus it is removed from the trunk.  This check is performed as follows :, the value of the bits of the count, the loop of the cycles through the element OR 35 and the element AND 36 of the two receiving registers 26 and 27 are entered into the counter 37 by the signal A2, its contents are anaparated by comparison and, by will, the counter 37 is equal to zero, then the signal A3, through the group of elements And 33, in the transfer register 41 and 42 records the indication of the word for the control module.  If the contents of the counter 37 are not zero, then by the signal 42, the unit 37 is subtracted from the co-press of the counter 37, and.  its Noah content is written into the corresponding bits of registers 41 and 42 transmitted by the signal A3. The third mode is the transmission mode of the zero word, t. e.  In these days, the receiving and moving registers do not store information.  In this case, in the mode control node 32 there is no sign of employment, by which it combines the operation of the element group AND 33 and the group element C OR 4O, then the signal B1 from the distributor 34 pulses to registers 41 and 42 transmit through a solid switch 39 drift ts all zeros.  24 Device For interfacing modules of a computer system with monitoring, it can significantly increase reliability by: applying duplication.  Ha6qpa passive tires and main registers and nodes; introducing element-by-element redundancy in the trunk and hardware units that automatically implement Bbi6op bypassing the failed and elements; the use of a common for the entire highway, hardware of the implemented Xygrol trunk block, which allows control and recovery of information.  Circulating in the highway; the use of one or several control modules with advanced software for the purpose of diagnosing the backbone and implementing repeated transmissions of information.  Formula from b. . Reteni 1.  A device for interfacing computer system modules with a control containing the first group of receiving registers, the first group of transmitting registers, the synchronization unit, the group of pulse distributors, the first group of qpeBHeHK9 logs, the group of address registers, the group of control registers, the first group of buffer registers, the first group of elements OR | a group of control signal generation units, the first output of the synchronizer unit connected to the inputs of all pulse distributors of the group, the second output of the synchronization unit is connected to the second inputs of all the distributing pulses of the control distributors of all the pulses of the first group, R second outputs they are connected to the first and the second with the corresponding hops of the corresponding blos. In the first control signals of the group, the first output of each ((the control signals of the connection group with the control input of the first perftcipa transmitting it (the group, the output of each {: -th transmitting register of the first group is connected with the first information {m.  the input of the nepBt group of the sixth register and the information input of the (1) -th receiver register of the first group; in the first place, the information of the input of the first buffer register of the first group is the first input of the device, the information output of each register of the address of the linking group and the first information input of the corresponding the unit for comparing the address of the first group n with the third information input of the corresponding bu (|) register of the first group, the information output of each receiving register of the first group is connected to the first input The first group of each element OR of the first group is connected to the first information input of the corresponding control terminal block, the second, third, fourth, and fifth outputs of each block. the control signals of the group are connected respectively with the control input of the corresponding blocks comparing the address of the first group, with the first control input of the control register of the group, with the corresponding The device's output, with the control input of the corresponding buffer register of the first group, the information output of each group register, is connected to the second information input of the corresponding control output signal, the second control inputs of each control register form.  The group of control inputs of the device, characterized in that, with the price.  The control unit of the trunk, the second group of receiving registers, the group of switching blocks, the second group of transmitting registers, the first, second and third groups of error detection blocks, the group of comparison blocks, the second group of elements OR, the group of failure counters, the group (| tutors and the second group of buffer registers, with the information outputs of the latter. The transmitting registers of the first and second groups are connected respectively to the first and second information inputs of the main control unit, the first and second (The directors of which are connected respectively to the first and second outputs of the synchronization, the first and the second information codes.   the line control is connected respectively to the information inputs of the first receiving registers of the first and second groups, the code of each receiving register of the second group is connected to the second input of the corresponding element OR of the first group, with the first information input of the corresponding control box (En. the addresses of the second group, the first, second, third and fourth inputs of each switching unit of the group are connected respectively to the information and inputs of the corresponding receiving register of the first group, to the output of the corresponding one.   reception register of the first group, with in-.  The direct inputs of the corresponding second group registration register, with the output of the corresponding second group receive register, the control inputs of all the second group's receive registers are connected to the second output of the synchronization unit, the first and second information outputs of each unit 4y of the group are connected respectively to the information inputs the corresponding transmitting registers of the first and second groups of J are information-based. output of the k-th transmitting register of the second group; connected to the information input (4t + l) ro of the receive register of the duplex, with the information input of the buffer register of the second group, and the information input of each buffer register of the second group is connected with the fifth information input of the corresponding group of the first group, first and the sixth outputs of each control signal generation unit of the group are connected respectively to the control input of the corresponding transmitting register of the second group, to the control input of the corresponding aores comparison unit of the second group ppy and with yn.  equal to the input of the buffer register of the second group, the 4a1 output of each register of the group address is connected to the second information input of the corresponding comparison of the second group, the output of the corresponding comparison first and second addresses (the groups are connected to the first and second inputs of the corresponding OR element of the second group, the output of each element OR of the second group is connected to the control input of the corresponding control register of the group; the seven A output of each block; the generation of control signals of the group of connections With the corresponding group fault counter, the output of each fault counter is connected to the corresponding group decoder input, the output of each group decoder is connected to the third Bhsa of the corresponding block in the control signal of the group, each exhaust register of the first register and the second unit are connected respectively to the first unit and the second group of the corresponding control signal of the group, respectively, the first-party exhaust gases are connected to the first unit and, respectively, the main unit is connected to the corresponding control unit the detection blocks of the first and second groups, the outputs of the error detection blocks of the first and the second groups are connected according to the quarter and the fifth inputs of the corresponding the third output on each input of each switching unit; the groups form the first group of information uvoiono to the second Ypynny device information inputs; the output of each buffer register of the first group is connected to the information input of the corresponding error detection unit of the third group the third input of the corresponding control signal generation unit of the group, the output of each error detection block of the third group is connected to the sixth input of the corresponding control unit Single generation upravlshoschih -group signals.  2  The device according to claim.  1, characterized in that the line monitoring unit contains the first and second reception registers, the first and the second error detection nodes, the fault correction node, the OR element, the AND element, the counter, the AND group of elements, the comparison circuit, the first and second transmission registers, the distributor pulses, a group of elements OR. .  the first and the second service switches and the mode control node, the first and second information inputs of the block are connected to the information inputs of the first and second receiving registers, the control inputs of which are connected to the first output of the pulse distributor to synchronization (ruler of the input elements of the And group, the output of the first receiving the register is connected to the input of the first error detection node, with the first inputs of the mode control node, the failure error node, with the first input of the OR element and the first input of the first switch, the second output first receiving register is connected with the incoming error detection node, with the second inputs of the mode control node, the OR element, the fault correction node and the second input of the first switch, the control to the information outputs of the first second error detection node is connected to the first and second control ports, respectively. the information inputs of the second switch, the first and the second control outputs of which are connected respectively to the control "stroke of the fault correction node and to 1 (the first control inputs of the elements AND group, the output of the fault correction node is connected to the first information inputs of the AND elements of the group, the first and second outputs of the mode control node are connected respectively to the second inputs of the AND elements of the group, with the first inputs of the elements OR of the group, the first, second, third, fourth and fifth outputs of the elements And the groups are connected, respectively, with the first input of the element I, with the control input of the counter with a head.  With the OR elements of the group, with the control input of the first and second transmission registers, with the information inputs of the first and second transmission register, the outputs of which are outputs of the block, the output of the OR element is connected to the second input of the AND element, the output of which is connected to the counter input of the counter, the output of the counter is connected to the input of the comparison circuit and with the second ones; the formation inputs of the AND elements of the group, the output of the comparison circuit is connected to the third inputs of the AND elements of the group, the second output of the pulse distributor is connected to the control input of the first switch, the outputs of the OR elements of the group are connected to the third information and second control inputs of the red switch, the first and second outputs of which interconnected with with qq) ymv Kyfbrk AC bnby the inputs of the first and second transmission registers, the device according to claim.  1, that is, that block C) is external.  errors contain a group of convolutions by means of two, a group of elements I, Threshold; element and decoder, and the inputs of the two modules to the module are connected to the inputs of the module; and connected to the corresponding inputs of the threshold element and the decoder, the output of the decoder is the control output of the block, the output of the pore element cc is the same as the control input of the decoder.  four.  The device according to claim.  1, that is, that the switching unit contains the first, second, third and fourth elements OR, the first second, third and fourth elements AND, with the first, second, third and fourth information inputs of the unit Connected with the first input of the first element OR, with the input of the first element OR, with the first input of the second element OR and with the second input of the second element OR, the first and second output of the first and second elements OR are connected respectively with the first inputs of the first, second, third n - of the correct elements And, torye inputs of all AND elements are combined and connected to the control unit yuschimivhodom, third inputs of first and third elements and connected to the second input unit, third Rin & The second and fourth elements of AND are connected to the fourth input of the block, the outputs of the first, second, third and fourth 80 elements And are connected respectively to the first and second inputs of the third OR element whose outputs are the outputs of the block, the third inputs of the third and fourth elements OR.  connected to the fifth information input unit.  Sources of information taken into account during the examination 1. U.S. Patent No. 3,947,618.  cl.  340-147 d Р, рпплнк.  19716.  .   2. The author's testimony of the USSR on application number 255732О / 18-24, cl. q 06 F 11/00 (prototype). I I .