SU803699A1 - Byte-multiplexing channel - Google Patents

Description

(54) BYTE-MULTIPLEX CHANNEL

The invention relates to computing, in particular, to the system.the exchange of information between peripheral devices and operational memory of a digital computer, and can be used in data exchange systems.

I / O channels are known that are connected to peripheral devices through several I / O interfaces provided by interface units with slow-acting and fast-acting devices. These channels consist of a local memory block, a control shaping unit, oi1, its information, a interface unit with slow-acting peripheral devices, a interface unit with fast 11 peripheral devices, a control information modification unit, a priority distribution unit and a control unit.

However, the known channels due to the hard prioritization of the satisfaction of requests from the interface units with peripheral devices and the exchange of information with RAM do not have the ability to exchange data with the channel buffer in RAM control (but only directly with RAM), the access cycle to which

significantly less cycle time for accessing RAM. Increasing the channel speed in this case is impossible because of the increase in the number of RAM access from the channel and, consequently, the increase in the number of conflict situations between the channel and the central processor in terms of RAM, which leads to a decrease in the performance of the entire computing system as a whole.

The closest in technical essence and the achieved effect to the invention is a byte-multiplex channel, the states of the storage unit control) 1 information, the control information generation unit, the interface unit with slow-acting devices, the interface units with high-speed; units, block of information, control unit, control unit, unit; 1st priority.

Such a channel has an insufficiently high performance, which is caused by the impossibility of .1 exchange during the exchange between the channel and the RAM of the channel buffer in the control, since the cycle of data exchange with the channel buffer in the control of the RAM is much smaller than the cycle of exchange with the RAM. This leads to a decrease in the NPO arrays of 1 Gge; 1 computation of the computational system of the whole system and an increase in conflict situations with the channels liB-j.in-iv water and the ucHTjia-ibUbiM processor IKJ of the O3i processor. as .5aich | 1tel) 11 () military.astaet -iiic.io requests to or; -; aiia, -: a gjoda-you are water. The purpose of the inventor is iuMi; , performance channel performance. Del D Stngaets by the fact that the byte-multi-channel channel containing the control unit, the storage unit un) a15; Я1ои1, и иforformatsiya, P.yuk of the distribution of theory 1, the priority of 15, bl -:) .-: .o, iiiii.i: katsni uirav; 1I gm liiKbopMaiur-i, b ,,:.;.; forl iipOBaiiii) for right; 1 (.: ai1;:, 6.TOKI mate with fast power supply: m devices, b ;; ok ok sop) 1ach111 with honey.K: nodoristey devices, nerve) 1st, second, third and quarters one.(). which are connected .. by association ;; with the first inputs-outputs of the channel, the control unit, the priority-allocation unit, the bstock forv.-mirovani khiravl yu1dey, And | Iformanii, with this m. Torah. the third, the fifth, the fifth, and the first move 1 1 drives of the b.yuk () ormirova control; they are connected according to the second inputs of the i-exits 1 channel, block xiipaB.ieiiiiH, with jiepBBiMn; and conjugation units with a bb1strolist; To) devices, block. Mod.icapia wea r yuy yyayy info ramapia and flea stored. I upra, was 1ON1; to her, the second input-1 output of which is connected to the third .im () m- | vv b B.yuka 1 The fourth, sixth and seventh inlet1-1-EXIT .YU block t1.ravlepi .concluded. ssch) brightness ;; snn to the third} channel input, channel 1 input, the output of the sonr / sep unit from the device, b lying in the modification ;;:. the most recent information, block laciM HpHopiiTciOB, third; cf) e.TH4 (4i with the third and b; yukoz sirozhenii with bk ustromashshmi, che; airt ;;. b; yuk () P conjugate with hstroystvami komod; per st; with damilimhodamn hana.cha, b .., tepie obyomeyom, first j) Oio is connected with: yververt,: mx b.yyuka distribution iRits T); INPUT-15PUT is connected to the .IBM b :: eye. (Normalization unra.nl to; mation and e to the inputs of a-kov eo11r; keni gb; e-: only 10): -; am ;, 1 nei i: H; a: that output of the block tj h. :: 4i ; Kiii .1 klney.; A1ZI 1. V; 1ok ruled by P ;,;: a; :: group of lemetstov I, n:) and.ch1akov,. Teujntpjiaroj) i (ooMeiia,:: p..ai-aa ha) i, Tpnrret) block gauge and jni. 11th) and1-: 13KOD of the block is connected to the first 31V and the inputs of the ile vyiiiiN zlemeitov m. In.nJiiiogo, the second and the third elements of the P.). (.chgga M and P) opp1) 1 e.emenchov I, the output of which is the connection with the first input of the KTpa and trick, BT ()) iiiM input (.) of the subclass-cHHioio to the output (). of the second element of OR, and B1 hod) 1 k hieroh; y (,. that bl (.1ka and hier1.;) 1y ixo. for CH1L frat () raks, chIia obmenmena, () D which is connected with the intruder: m output b, eye and the second is the entrance of the first a, te.eita I. iii.ixo.T of the first eleiteite And is connected to ia, - | Bb M inlet HCjJBOro e.y.me.da OR and echoed; in ertogo And, O:) D koto1) th nodk; :: ochei the first ext. - :) The elements 11LI, 1D, 1IND of the second leMcHia And each with the second inputs perlifjro and BTot) () r (j element 1IL, вь: the course of the third element And connected to the third | went; n iiejJBtJio and the second element OR. Tpeiani block input United with the second; | the inputs of the third element and the deinfrato) a a.) iHU. and with nerve1; 1m input.m trigger block K.aiaa. BTopoii in (;; KOTopoio nod; s.:; OKii to () .ch 1e |) ü: element of the OR, a ;; ü: move connect :; with the second) in the course of the block. FIG. 1 shows a bochochem bytem a1tin. I-xsnogo kana, 1aa, iia of fig. 2 (pen 11) 11a i.ioKa unrav.chenn obm (.ch; Ol. LaGggg -., 1tilexiPy dripped soda) Ж11Т nKiK D1ral5 .. block 2 stored: unranl K.) information, b. (; modifications h: rar..1 k) information 1.1, blo; 4 rarnredg. 1, ndiorite roii, p.iP (p () rmnr1ch5ai1; aipaB. Iifor: ai.1.b.b.choky li li eonr / chs1 ;; c bymetr () real1pch The construction unit, control unit 8; bm1: k) mn has inlets-output 9-12 and elastic tires 13-15. B; ioK un) av; 1 (H) holds |) igger I) 1 ( a) b. 1ka. p) elements 17, rccccmc 8 HpH.iHaKOB, den11 frator 19 .a exchange, And 20-23, e, 1) I.Ch 2-1 11 25. e) of the channel in the controller (;,. re /) im b, 10kovO P1 exchange, orgapiach ksh p.1elu.on1nm image:. Ips.te satisfaction | ) echnich on obych1 g.yuvo.m og block i) according to npnopj: -; h b.toc-1 (installation accordinglyto the world;); itite: a., after the equipment 6: iOKOB 1-5 Astraivaet on (j6e4y anachche a1o; 5.1 (creative: ianpoea) scnna ..; a:; chd | aka.: om1, ch1a. change: plural of block geeig; al nrio |) itera from b,: k) ka 4 Iosti io i cooTiicTCTBe H1 JO but unrave,;: I 01HNM H1Ich. 11 and 1 o in b.i. control.-exchanging exchange.:, I h, - one of the following functions (CH1TOV I 17, according to ac1a; e 5yo; and the cat (Chistoi stan1; .11 va aacha of register 1) b / yukovy (Ch; a, sooT1k-tst1 h (line to the signal of ypOBiiH aritega, r. ls HpiiaiiaKOM block (rpyiHioBoro) of the exchange .aainiiaMH b.yuka ij e. Outputs e register 18 and tukutiku gi) 13 in block 4, managing the installation of signals of the priority levels so that, as long as one of the levels of the feature register is set, it is possible to satisfy the request only if the corresponding priority level is set, the satisfaction of all other requests, even seniors, t. e. setting all other zfovney priorities according to the assigned priority is blocked.

Thus, when the signal with perHCTipa signs is arranged, several other data words of block 6 with RAM are organized, i.e., one data array is exchanged, which makes it possible to use the channel buffer in RAM.

Block 6, having a buffer for vacuution, in general, initially sets requests for data exchange when filling the SPS 1 buffer allows you to accept (| P, When read from RAM) or issue (With a write operation IB RAM) the number of data words is less than the total volume of the RAM channel buffer (for example, four).

When the first request from block 6 for exchanging the data word by block 4 is satisfied, according to the assigned priority, the corresponding register register 18 of the Signs of block exchange is set. The exchange of the data word with the RAM is performed under the control of the block 5 1PO bus 10. After the completion of the service, neither the first request from block 6 (in the general case of completing the oi change from the RAM), for which the block exchange sign is set, immediately forms a new request for the exchange of the next word data, which is immediately satisfied, regardless of the presence of other requests, even those that are older when the requests are hard to satisfy.

Consequently, the rigid distribution of IB satisfaction of requests according to the assigned priority is violated when the signal is received from register 18 of the signs and one data is exchanged | M..m, which makes it possible to exchange data with (channel buffer in the RAM level. This exchange continues until the block exchange indicator of the register is reset; one of the conditions at the input of the element OR 25, which controls the reset of the register of attributes, does not occur.

The conditions for resetting the register of attributes occur When) complete for: full (dissipation) of the channel buffer in RAM, upon completion of the data exchange initiated by the channel IL.I of the peripheral device, when emergency situations arise (for example, bad).

Filling (resorption) of the channel buffer in the control of the RAM is allocated by the end decoder 19 end with buffer

channel: if there is a sign of blocks of the Exchange, coming to the decoder from the output of the register of 18 signs, and, aapec of data is generated at the time of forming the request for Exchange yes: in the RAM, coming through control buses 15 from block 5.

When the address of the data corresponds to the complete filling (resorption) of the buffer, the channel in the RAM, the address is sent to the RAM to release (fill) the buffer; At the output of the decoder 19, signals occur via bus 14 to block 6 and AND 20, the output of which sends a signal to one of the inputs of AND 23 and one of the 1 INPUTS of the OR 24, whose output controls the end trigger 16 setting block. Sipnal from the trIGGER of the end of the block via the bus 14 enters the corresponding block 6. The set of signals from the two decoder 19 and the trigger 16 on awl 14 indicates complete filling (resorption) of the channel bar in the RAM management, if the conditions for initial installation of requests to data exchange, ire; see a series of requests for data exchange from block 6, which resets the signal of the data exchange feature.

In the absence of a sign of data exchange from the corresponding block 6, incoming via control SHENE 14 to AND 23, and the presence of a signal at the output of the AND 20 element, a signal is output at the output of the AND 23 element, which, through the OR 25 element, resets the register 18 signs. The block communication is terminated. Satisfaction of the inquiries according to the assigned three-year term enters into force. If the conditions of the initial installation of the deadlines did not disappear in block 6 when signals arrived at bus 14, block 6 does not reset the signal of the data exchange feature, requests for data exchange “e blocks”. In this case, the element And 23 does not work and the reset of the register of 18 signs not P | p1oizhodnt. The blocking delays continue with the updated channel buffer in RAM management.

The completion of the block data exchange initiated by the channel (in the absence of bad situations) occurs when the data account in the current control word of the channel is exhausted. The null data counting signal comes from block 5 via bus 15 to element 22 and in the presence of a sipnal equalized the priority of block 6 from block 4 arriving via control bus 13 and another input of element 22, the output of element 22 produces a signal to the inputs of elements OR 24 and 25. The signal is output at the output of trigger 16 for the end of the block, which is fed through bus 14 to block 6, where the Data Exchange Signal Signal is unconditionally reset and requests for data exchange are blocked. The control signal CONC.M. Array on the bus 14 P1 goes to

block 5, which forms the signal END OF THE MASSIF. when it enters the RAM control via the 10-liter bus; when organizing access to the RAM, the channel buffer is released. The signal from the output of the element OR 25 resets the register 18 signs. The block communication is terminated. Thus, about & t, the END OF MASSIVE signal at BL | OKO1BO, the exchange is issued not at each IB RAM access, but at the end of the block Exchange.

The block exchange of data is also terminated upon completion of the data exchange initiated by the peripheral device. In this case, the signal of completion of the operation by the peripheral device from block i6 enters through the control pin 14, to the input of the element 21; The ori “of the signal of the priority level of the block 6 from the block 4, the post of the pilot on the control | ui: ine 13 to the other input of the element i 31, activates a signal that works as well as the signal from the output of the element i 22. The register 18 of signs is cleared. Block data exchange is guaranteed. The satisfaction of requests according to assignment | 0, mu priority comes into force.

The signal output by the slit 14 to signal the END OF THE MASSIVE is always done when the signal of the block 6 priority level is present, which makes it possible to send an additional request to the RAM to establish the signal of the END OF THE MASSIF to release the channel buffer in the RAM control (during the read operation, the buffer is used in RAM, during the RECORD operation, the symptoms of the buffer are reset), and to present the END OF MASSIF signal during the organization of the request for data exchange.

The introduction of a block exchange node improves the performance of a channel in a computing system with a given RAM bandwidth and total computing system 3ia by reducing the number of uncommitted data exchanges with RAM and reducing the number of collisions on accessing the channel RAM and the central processor.

Claims (2)

1. A byte-multiplex channel containing a control unit, a control information storage unit, a priority distribution unit, a control information modification unit, a control orformation unit, a interface unit with high-speed devices, a interface unit slow-acting devices, the first, second, third and fourth inputs-outputs of which are connected respectively with the first inputs and outputs of the channel, the control unit. the priority distribution unit and the control information generation unit, the second, third, fourth, fifth and sixth inputs / outputs of which are connected respectively to the second inputs / outputs of the channel, the control unit, to the first inputs and outputs of the interface units with high-speed devices, to the control information modification and block storing control information, the second KOTOiporo input-output is connected to the third input-output | M of the control unit; the fourth, fifth, sixth and seventh inlets of which are connected respectively with the third input-output of the channel, with the second-outputs of the interface units with high-speed devices, the modulation module of the control information, the p, ac / priority limit, the third input output of which is connected to the third inputs-outputs of the interfaces with high-speed devices , four; the open input outputs of which are connected to the fourth inputs by the channel's mic outputs, which is different from the fact that, in order to increase the performance of the channel, the exchange control block is inserted into it, the first input / output of which is connected to Werth vhodomvyhodom block raopredelen | FL (priorities The second input / output is connected to the seventh | M input of the control information formatting unit and with the fifth inputs of the output interfaces of the interface units with high-speed devices, the third input is connected to the fifth output of the control information generation unit. 2. Channel according to claim 1, characterized in that the exchange control block contains a group of AND elements, a prianak register, a terminal end decipher, first, second, third, fourth AND elements, a block end trigger, first and second OR elements, and the first input the block is connected to the first: input of the elements of the AND, nepiBoro, second and third And elements, the second input of the block is connected to the first input of the fourth And element, the second inputs of the second And element and the group of And elements, the output of which is connected to the first input of the sign register, whose second entrance connected to the output of the second element OR, and the output is connected to the first output of the block and the first input of the decoder of the end of the exchange, the output of which is connected to the second output of the block and the second input of the first element AND whose output is connected to the first input of the first element OR and the second input of the fourth element AND, the output of which is connected to the first input of the second element OR, the output of the second element AND is connected to the second inputs of the first and second elements OR, the output of the third AND is connected to the third inputs IE (the third and second elements OR, the third OD unit coupled to second inputs of the third AND gate, deshifratara end exchange and the first input latch -block end, the second input of which is connected to the output of the first OR gate and an output connected to the second output unit. one