SU798841A1 - Device for automatic testing of large-scale integrated circuits - Google Patents

Description

reriepkxop tests, input signal conditioning unit, controlled unit, reference unit ,; the unit is compared, the control unit, the memory unit and the display unit, I, the information input of the memory unit is connected to the JBXOAOM device data entry, the controlBiliBJimwiiHtt input is connected to the output of the control unit paralleime, command, first and second information and tests the memory block outputs are connected with the first input of the control unit, informational: with the inputs of the display and input unit and the information input of the generator; respectively, the control input of the test generator is connected to the trigger output of the control unit, and the output with the second information input of the pho block, E 4 of the input signals, the diagnostic and reference outputs of KOTOjporo are connected to the inputs of the contact and reference coOTJieTCTBHHHO blocks, the output of the comparator is connected to the second input of the control unit, the first block of which is connected to the corresponding input of the comparator, and signal output .- with control input of display unit. The first and second data transcoding blocks are entered into the two-digit binary code, the selector selector and the decoder of the output state of the reference unit, the output connected to the third input of the control unit, and the input œ with the outputs of the reference unit and the information selector of the address selector The input input of which is connected to the master output of the control unit, and the output to the address input of the memory unit, the second output unit of the control unit is connected to the corresponding input of the input-signals shaping unit, the inputs of the first and the second data transcoder into a two-binary binary code are connected to the output of the 1 MI controlled and reference blocks, respectively, and the outputs, respectively, with the first and second information blocks and inputs of the block: equilibrium. The drawing shows the block diagram of the proposed device. The proposed device for microprocessor control. The LSI contains a test generator 1, designed to generate sequences of object synchronization and pseudo-random} sequences on the basis of which the test is based. The outputs of the 1 tecTOB generator are connected to the inputs of the 2 fO unit {“input signals, which ensure the recollection of a set of signals corresponding to the current test beat, and its application to the terminals of the monitored LSI 3 and SINGLE-TYPE reference VIS 4, The conclusions of the two LSIs are connected appropriately the inputs of the first 5 and second 6 data transcoding blocks :, which ensure the conversion of the output: VIS signals into a two-digit binary code. The outputs of the first 5 and second b data conversion units are connected to the corresponding inputs of Comparison Zlok 7, which will be added to detect the logical inequality of the output signals of the monitored and the reference LSI. The output of the comparator unit 7 is connected to one of the inputs of the control unit 8. The reference codes of the VIS 4 are connected to the inputs of the state decoder 9, for analyzing the state of the bidirectional VIS outputs before supplying input signals to them, and to one of the inputs of the block 10 address selector. The output of the address selector unit 10 is connected to one of the inputs of the memory unit 11, which also has an input 2 for data entry. The memory unit 11 serves to store the commands implemented by the device, as well as the relevant data and tests necessary for the control. The outputs of the memory unit 11 are connected respectively to one of the control inputs 8, to one of the inputs of the input signal generation unit 2, to one of the inputs of the test generator 1, to one of the inputs of the display unit 13 for outputting the control results. The control unit 8 provides the interaction of all the units of the device in the verification process by generating corresponding control signals and distributing the commands and data from the memory units 11 to the remaining units of the device. For this purpose, the outputs of the control unit are connected respectively to the control input of the comparison unit 7, the control input of the input signal generation unit 2, one of the test generator 1 inputs, one of the display unit 13 inputs with one of the memory 11 inputs, from the inputs of the address selector block. The proposed device provides functional control of LSI on pseudo-random tests generated by generator 1 tests on deterministic tests specified from an external source (with a large test length or previously written in block 11 memory on deterministic tests specified as software-implemented algorithms using commands memory in block 11. The execution of a typical BIS control program on pseudo-random tests takes place as follows: Input pins of a controlled 3 and reference 4 BIS ( including bidirectional) are connected to the outputs of the block 2 forming the input

signals Output outputs of controlled 3 and reference 4 LSIs (including bidirectional) are connected to the inputs of the first GDB and the second 6 data transcoding blocks, respectively, sequence of commands are recorded in memory block 11, which provide programming of the following operations: setting the synchronization sequence of the monitored and reference LIS; setting a pseudo-random test by setting the required initial comprint of the test generator 1, the algorithm for generating a pseudo-random test sequence and its length; launching a test generator to apply a pseudo-random test determined by the relevant initial conditions to the findings of the monitored and reference LSI, and a supplement to the conclusions of the monitored and reference LSI specified in the program of the sequence of signals of the LSI into a known initial state.

After starting the device, using the appropriate program commands, the initial conditions that determine the pseudo-random test and the sequence of synchronization signals are sent to the test generator. Thereafter, a sequence of commands and data is received from memory block 11, with which the inputs to the controlled and reference LSI are fed through the input formation unit 2, the corresponding sequence of signals leading to both LSIs in a known initial state. Then, the test generator 1, when commanded from the memory block, provides a pseudo-random test to the inputs of the monitored and reference LSI. In the process of applying the test to the inputs of the monitored and reference LSIs during each of its cycles, signals from the LSI outputs of the same name enter the data conversion blocks 5 and b, where they are recoded into two-bit binary CODES, which are then compared in comparison block 7. If an inequality in the values of the signals at the LSI outputs of the same name is detected in the test cycle, the generator 1 of the tests O11G4 on it enters, and the display unit signals a malfunction of the controlled LSI 3. In each test step, the decoder 9 of the output state reveals Those conclusions of the reference LSI 4, which are currently in a state of logical 1 or O, and reports this to the control block 8, which issues the corresponding signal to the block 2 forming the input signals, prohibit the prohibitions These pins are any binary signal. .

When testing an LSI on deterministic tests, set from a source of programs or pre-recorded in a memory unit, the test generator is not started. The sequence of sets of input signals of the monitored and reference VIS 3 and 4 is specified via block 2 of forming the input signal directly using commands and program data, as is the case in the case of the sequence of converting the LSI 3 and 4 to a known initial state.

The control of microprocessor-based LSI on deterministic tests generally requires tests of a very long length. So, for example, only when checking the program counter and the register memory of the microprocessor W Lp1.e & 3080 requires 262ilO H 50-10 deterministic codes, respectively, and at least 1 10 codes are required to check the entire microprocessor. To store tests of this length, a very large amount of memory is required. If, during the verification process, a verification test from some external device (for example, from magnetic disks or from another external memory in parts) is entered into the memory memory, then the input time will be longer, which degrades the device performance. The disk in the test memory block 11 will take about 50 seconds to complete, in addition to the test execution time. In order to reduce the LSI verification time by minimizing the amount of input data defining the test, the proposed device provides another way to deterministic tests using an algorithm implemented by software reference reference LSI together with memory block 11. This method is applicable when the verifiable (and correspondingly reference LSI) is a device capable of providing a sample of a program from external to memory and program execution, such BIS include single-chip microprocessors, controllers of external computer devices and some others.

When checking on deterministic tests, specified in the form of a software-implemented algorithm, in the device memory block 11, except for the commands that provide the initial mouth; The LSI command line and the required synchronization sequence are used to enter commands that provide algorithmic test generation. The amount of memory required to store the specified commands is negligible. So for the microprocessor type diTteb 3080 it is (without taking into account the control

microinstructions) total lml 1.4 bytes. With the algorithmic method of control, the sequence of the required control test is formed using the reference LSI 4, which, together with the device memory 11, forms the micro-computer. The signals that occur at the inputs of the reference LSI when executing this micro-computer of a given program. are applied as a test to the inputs of the tested VIS. The output signals of the reference LSI as well as in the other methods of forming the tests considered earlier, are used as reference signals with which the output signals of the tested LSI are compared.

When choosing a program for the algorithmic test generation, the tested LSI is conditionally divided into internal modules, to which access is provided with the help of the appropriate commands. The control of the VIS consists in checking the execution of commands specific to each module, so to check the module of the dnteC microprocessor program counter. The 8080 is reasonably convinced that its contents can gradually increase to a maximum value. To perform this test, the program requires only 6 commands, some of which are repeated many times, which requires a naturally small amount of memory and a small amount of time to rewrite the program from the external storage device. (The total number of commands in the JUNE microprocessor program. 8080, necessary for its control by the method of algorithmic test generation 100).

The implementation of a typical functional control program based on algorithmic test generation in the proposed device is carried out as follows.

In memory block 11, commands are introduced to ensure the initial setup of the monitored and reference LSI, the specified synchronization sequence, and the program (in the language of the checked VIS, providing control of the control process, including the generation of the controlling test on the conclusions of the reference VIS. four.

After launching the device, the corresponding commands and data are extracted from the memory block 11 of the control unit 8 from the memory unit 11, which are fed through the input signal shaping unit .2 to the outputs of the monitored 3 and reference 4 VIS and set them to the same known initial state. Next, from block 11 comes the first command of the program for the algorithmic test generation, which transfers control of the process of sampling and executing the program of the reference VIS 4. At the same time, the block 10 of the address selector switches the corresponding pins of the reference LSI with the inputs of block 11, thereby ensuring the possibility of sampling from block 11 commands and data of the program for the algorithmic generation of tests in accordance with the control signals and addresses from the conclusions of the reference VIS, as well as the transfer of data from this LSI to block 11. According to le VIS transmission control reference sample and begins execution of instruction posledukvdih algorithmic generation of the test program. The command and data of this program are posted on the corresponding inputs of the reference LSI through block 2 of the formation of input signals. These: i.e commands and data are fed to the inputs of the checked LSI. The output cHPHaJiu of both IPOs after their conversion by blocks 5 and 6 are compared by block 7 as well, as is the case with other ways of forming tests. Similarly, the work of the pin state decoder 9 proceeds, which controls the process of applying signals to the bi-directional pins of the oISekx VIS. The program execution of the algorithmic test generation ends either when a VIS output signal mismatch is detected by block 7 (in this case, control block 8 stops the synchronization generator included in test generator 1), or by command transfer control to block 8. Thereafter, the selection of commands from the block 11, the memory is no longer provided by the reference LSI, but by block 8.

Introduction to the proposed device from the decoder of the status of the address selector outputs and the two data transcoding blocks improves the accuracy and speed of the control, as well as ensures the verification of the VIS at their operating frequencies. The speed is about 5 times higher than with a known device. For example, checking with the aid of a known microprocessor device L. 2-880 on tests stored in an external storage device requires, as noted above, not less than 50 s. while the control on algorithmically generated tests using the proposed device is approximately 10 seconds.

Compared with the known device, the proposed device requires less. The amount of internal memory due to the smaller amounts:. commands in the program - necessary to implement the control process.

Claims (1)

Invention Formula Device for automatic control of large HHTeipa.ribffbix :: x (m.