SU750478A1 - Converter of integer binary-decimal numbers into binary - Google Patents

Description

(54) CONVERTER WHOLE BINARY-DECIAL BINARY

I

The invention relates to the field of automation and computer technology and can be used in the construction of devices that carry out the binary-decimal information conversion.

A binary-decimal converter is known, which contains two shift registers, correction blocks and a control unit 1.

The disadvantage of this converter is a large amount of hardware.

The closest in technical essence to the present invention is a converter of a binary-decimal code into a binary one, containing the first and second shift registers, the first adder, the control unit, four AND elements and the first OR element, the first input of which is connected to the output of the first element AND, output The first element OR is connected to the first input of the first adder, the second input of which is connected to the output of the second element AND, the first output of the first shift register is connected to the first inputs of the third and fourth elements AND, the outputs of which x are respectively connected to a first input of the second shift register and a second input of said first OR gate, the first and second outputs of the second register

the shift is connected respectively to the first inputs of the first and second elements I, the first output of the control unit is connected to the second inputs of the first and third elements I, the second output of the control unit 5 is connected to the second input of the fourth element I, the second outputs of the first shift register are connected to the output sections of the converter 2 .

A disadvantage of this device is the relatively low speed, due to the fact that in each cycle only one new binary-decimal tetrad is involved in the conversion.

The purpose of the invention is to increase the conversion rate.

This is achieved due to the fact that the proposed converter contains a second adder, a switch, a memory unit, a fifth AND element and a second OR element, whose inputs are connected to the first and second outputs of the control unit, and the output is connected to the second input of the second AND element. The first output of the control unit is connected to the first input of the fifth element I, the second input of which is connected to the third output of the second shift register, and the output is connected

the first input of the second adder, the second input of which is connected to the output of the first adder, the output of the second adder is connected to the input of the first shift register, the switch inputs are connected to the converter data buses, the switch output is connected to the first memory input, the second input of which is connected to the third output the control unit, and the output of the memory unit is connected to the second input of the second shift register.

The drawing shows the functional diagram of the proposed Converter. The converter contains control line 1, control unit 2, first, second, third, fourth and fifth elements 3-7 AND, elements 8 and 9 OR, adders (binary) 10 and 11, shift registers 12 and 13, output buses 14 , memory block 15, switch 16, information buses 17.

The control bus 1 serves to receive a start signal at the input of the control unit 2, which ensures the operation of the entire device. The first output of block 2 controls the transmission of a binary number at the multiplication stage and is connected to the first inputs of the first 3, third 5 and fifth 7 elements I. The output of the first element 3 AND is connected to the first input of the first element 8 OR. The first output of the control unit 2 is connected to the first input of the second element 9 OR. The second output of control unit 2 is connected to the second input of the second OR element 9 and to the first input of the fourth AND element 6 and controls the summation in the first conversion step in each cycle. The output of the second element 9 OR is connected to the first input of the second element 4 AND, transmitting information without shifting in the first stage and shifted to a wide position towards the high-order bits in the second stage of each cycle. The output of the first element 8 OR is connected to the first input of the first binary adder 10 for summation with, information received at its second input from the output of the second element 4 I. Information from the output of the first binary adder 10 is fed to the first input of the second binary adder 11, adding the information arriving at its second input from the output of item 7 I. The output of the second binary adder 11 is connected to the input of the first shift register 12, which circulates and stores the results of the summation. The first and second outputs of the first register 12 shift are connected respectively with the output tires 14 and the second inputs of the third and fourth elements 5 and 6 And, providing the transfer of input information without shifting in the first stage and shifted in the second stage. The output of the third element 5 And is connected to the first input of the second register 13 of the shift, the first, second and third outputs of which provide information shifted by five, five and two positions, and are respectively connected to the second inputs of the second 4, first 3 and fifth 7 elements I. The third output of the control unit 2 is connected to the first input of the memory block 15, the second input of which is connected to the output of the switch 16, which provides the reading of the necessary binary equivalent. The input of the switch 16 is connected to the output of the women 17, providing the receipt of the next pair of transforming tetrads. The conversion is performed according to the Horner scheme in accordance with the following expression:

Ar ((E, 1100100 + Eg) 1100100 -f + ....- f Ez + O. 1100100 -f Eu, where Ai - is the desired binary number;

This is the binary equivalent of the pair of tetrads to be converted;

j is the number of pairs of tetrads determined from the ratio:

20

t is the number of tetrads of the original number. The conversion of the binary-decimal number is performed in the following sequence.

The commutators of the binary-decimal number being transformed are sent to the switch 16 to the 17-nd pairs, sequentially, pair by pair (starting with the highest pair). Simultaneously to the control unit 2 by the control

Bus 1 receives a signal that triggers the entire device. Let the second pair of tetrads be converted, the first shift register 12 stores the result of the transformation of the first pair in the first cycle. On the switch 16, a parallel code is sent to

the next pair of transforming tetrads, the code of which is the address by which one of the ninety-nine binary equivalents is chosen (according to the number of combinations of digits of two decimal digits from 01 to 99)

from memory block 15. The selected seven-bit binary equivalent is delivered by a parallel code to the second shift register 13. The first stage of the second cycle begins. The control unit 2 generates a resolution signal to the second and fourth elements 4 and 6 I. In this case, the contents of the first and second shift registers 12 and 13 are fed to the first and second inputs of the first binary adder 10. The result of the sum comes from the output of the first binary adder 10 to the first input of the second binary adder 11 and is summed with the zero arriving at its second input, since the element 7 And is closed. From the output of the second adder 11, the result is written to the first shift register 12.

Claims (2)

After this, the second stage of the second cycle begins, multiplying by 1100100 (one hundred in binary code). In this case, the fourth element 6 AND closes, and in addition to the second element 4 I, the first 3, third 5 and fifth 7 I elements open. The contents of the first shift register 12 enter the sixth bit of the second binary register 13, which shifts the information by two, five and six positions in the direction of senior bits. That is, in the second stage, it is multiplied by one hundred in an indirect way. The result of the multiplication by the serial code is fed to the first shift register 12, where it is stored until the next cycle. The described process of receiving the next convertible pair of tetrads, reading the corresponding binary equivalent, summing it up with the contents of the first shift register 12, multiplying the amount obtained, takes another j-3 cycle. The last cycle is different from the other cycles in that it is not multiplied by one hundred. The binary number is removed from the first shift register 12. The proposed converter, by multiplying by one hundred instead of multiplying by ten and simultaneously processing two tetrads, makes it possible to double the conversion rate. The invention of the Converter of whole binary-decimal numbers in binary, containing the first and second shift registers, the first adder, the control unit, four AND elements and the first OR element, the first input of which is connected to the output of the first AND element, the output of the first OR element is connected to the first the input of the first adder, the second input of which is connected to the output of the second element And, the first output of the first shift register is connected to the first inputs of the third 8 and fourth elements And, the outputs of which are connected respectively to the first input the house of the second shift register and the second input of the first OR element, the first and second outputs of the second shift register respectively are connected to the first inputs of the first and second AND elements, the first output of the control unit is connected to the second inputs of the first and third And elements, the second output of the control unit is connected to the second the input of the fourth element is And, the second outputs of the first shift register are connected to the output of the converter, in that, in order to increase the conversion speed, it contains a second adder, which the mutator, the memory unit, the fifth And element and the second OR element, whose inputs are connected to the first and second outputs of the control unit, and the output connected to the second input of the second And element, the first output of the control unit, are connected to the first input of the fifth And element, the second the input of which is connected to the third output of the second shift register, and the output is connected to the first input of the second adder, the second input of which is connected to the output of the first adder, the output of the second adder is connected to the input of the first shift register, the switch inputs are connected to converter information buses, the switch output is connected to the first input of the memory unit, the second input of which is connected to the third output of the control unit, and the output of the memory unit is connected to the second input of the second shift register. Sources of information taken into account during the examination 1. USSR author's certificate No. 311474, cl. G 06 F 5/02, 1968. 2. USSR author's certificate number 329525, cl. G 06 F 5/02, 1969 (prototype). CM TG-I --- - 1 TII T about I I t I fj I and n I O X CO S "M