SU746556A1 - Device for diagnosis of electronic computer units - Google Patents

Description

(54) - DEVICE FOR DIAGNOSTICS OF ELECTRON COMPUTING ELECTRONIC COMPONENT PARTS

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The invention relates to computing and can be used to detect and localize malfunctions of electronic computers.

A device for diagnosing a computer is known, comprising a diagnostic test drive, an input register, a control unit, a parallel code-to-serial converter, an exchange register, a comparison unit, a buffer memory unit l. This device does not provide fault localization with IC.

The closest technical solution to the invention is a device for diagnostics of blocks of electronic computers, comprising a series-connected test drive, an output register and a buffer memory block, the control input of which and the control inputs of the output register, test register, input register and result register Tata are connected respectively to the first, second, third, fourth and fifth outputs of the control unit connected to the output of the test accumulator, and the register output

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the result is connected to one of the information inputs of the output register 2.

This device is complex, which is determined by the large amount of test information stored in the storage: in addition to the test sets themselves, the storage codes of the output of the test block, comparison operations with the reference, reference and other service information that occupy about 50% of the storage volume are stored The remaining 50% of the volume is occupied by the dough sets themselves. With a large number of high-performance computer units, the storage capacity may already be a factor that makes it difficult to use the device.

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The aim of the invention is to simplify the device by reducing the amount of test information recorded on magnetic media.

This is achieved by those. that the control unit and the control code register are entered into the device, the information input of which is connected to the output of the input register, output via the code converter unit with the 30 information input of the control unit, and the control input with the sixth output of the control unit A control input connected to the information input of the result register, as well as the fact that the code converter block contains code converters whose first inputs are the first inputs of the block, and a control code converter, the first inputs of which are the second inputs of the block, the outputs of the code converters and the control code converters being the outputs of the block, and the four inputs are connected to the output of the decoder connected to the output of the pulse generator via a counter, and the control unit contains a serially connected modulo two inputs of which are the information input of the block, vf trigger, the synchronization input of which is the control input of the block.

FIG. 1 shows a block diagram of the device; figure 2 - block diagram. Converter code and control unit. ;

The device includes a test drive 1, input register 2, control block 3, test register 4, control code register 5, code converter block 6, control block 7, result register 8, output register 9, buffer block 10 parameters, and diagnosed block 11 , inputs 12N-12.P and 13 and outputs 14 and 15 of block 6, inputs 16 and 17 of register 9.

The block 6 (see Fig.2) includes converters 18.1-l8.n code, including m p spans (from O to t-1). The control inputs of the IS.l-lS.n converters are connected to the outputs of the decoder 19, the inputs connected to the outputs of the counter 20, the inputs of which are connected to the outputs of the pulse generator 21. Block 6 also includes the converter 22 of the control code, and block 7 includes the adder 23 modulo two and trigger 24 ...

The operation of the device can be reduced to performing the following sequence of operations:

. setting register 4 from accumulator 1 to supply the input dough sequences to block 11 according to the control program; installation in register 5 of the corresponding information expected at the output of register 4, the analysis in block 7 of information from the output of registers 4 and 5; the accumulation of the result obtained in the set of tests in block 10; the determination of faulty integrated circuits of the software of the right-of-order in order to receive the code; go to the next diagnostic cycle, i.e.

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confirmation of the correctness of the fault localization by stopping the diagnostic process on the first test that detected the malfunction, and clarifying the localization using a special indicator probe and reference reference in the circuit of the diagnosed unit.

When connecting the diagnosed unit 11 pins to the device connector and starting data from storage device 1 through register 2, they go to register 4, as a result, a test sequence is set at the input of unit 11, then, according to the control program from storage device 1, register 5 sets the control code of the expected register output 4 information. The analysis of the correctness of the state of block 11 for this test set is carried out in block 7, more precisely, by the addition circuit modulo K.

To clarify the essence of the process of analyzing the results, we consider the operation of the circuit shown in Fig. 2, where the adder 23 is used in the control circuit. At the time O determined by the state O of the counter 20, the outputs O of the transformers 1В.118 are received. , t, 2m ... m (nl) +1 register 4, and the output of converter 22 is the value of the zero bit of the control code from register 5. Thus, the input of the adder 23 at the time O receives information together with the control bit, the sum of which modulo two at the output is zero in the absence of not serviceability in the block 11. The single value of the output of the adder 23 indicates the presence of errors in the diagnosed unit. Similarly, at time 1, defined by state 1 of counter 20, the values of bits 1, t + 1.2m + 1 ... m (n-1) +1 register 4, and the output of converter 22 is the value of the first bit of the control code from register 5. The above also applies to the remaining information bits at the output of the converters 18.d-18.p and the control bits at the output of the converter 22. The state of the adder 23 is fixed by the trigger 24 and transmitted to result register 8, which can operate in two modes: shifter and counter ..

During the synthesis of tests for blocks and devices of methods for activating a one-dimensional path, one block output is usually activated. All others take an indifferent state.

In the proposed device, all block outputs that are in an indifferent state are masked by setting the corresponding nm outputs of the register 4 to the zero state. As a result, a change in the output signal tested on a particular input set leads to a change in the parity of the signals in the group, which detects control circuit .

In the shift mode, the state of the trigger 24 is shifted to the right by the control signal received from block 3. After filling the register 8, its contents are recorded in block 10 as part of the fault code. This process continues until the malfunction code is fully formed, after which the device stops. At the end of the check for malfunctions, it is read out from block 10 and according to the diagnostic reference book, malfunctions of the IC are determined.

To confirm the correctness of the fault localization by stopping the diagnostic process on the first test that detected the fault, register 8 is switched to the read counter mode by a control signal from unit 3 and restarting reads the number of test sequences before stopping the device. The number of the test determines the input set and the reference information in the diagnosed block given in the reference book.

The absence of a special switch to control the flow of test information to the test unit's outputs is due to the use in this diagnostic device of a new method of checking logic devices on ECL circuits, with the output contacts of the test cxe block 11, which form 4 mounting elements with the outputs of the corresponding register bits And, a low logic level (logical unit) is applied using test information recorded on a magnetic media.

With the proposed organization of a device for controlling units on a computer, the volume of the test accumulator is reduced by about 50%, the device’s structural scheme is simplified by eliminating the comparison unit and its connections.

Claims (3)

1. Device for diagnostics of electronic computing units machines that contain serially connected test cases, a VHBD register, a test register, a block of code converters, an output register and a buffer memory block, whose control input and the control registers of the output register, test register, input register and result register are connected respectively to the first, second, third, fourth, and fifth outputs of the control unit connected by the input with the output of the test accumulator, and the output of the result register is connected to one of the information inputs VARIABLE in tl y 5 that, in order to simplify the device, a control unit and a control code register are entered, the information input of which is connected to the output input b of the register, and the output through the block of code converters of the c. information input control unit, and the control input with the sixth output of the control unit, the seventh output of which 5 is connected to the control input of the control unit connected by the output to the information input of the result register. . 2. The device according to claim 1, characterized in that the block of code converters comprises code converters, the first inputs of which are the first inputs of the block, and the control code converter, the first inputs of which are the second inputs of the block, the outputs of the code and control code converters are the outputs of the block, and the second inputs are connected to the output of the decoder connected via a counter to the output of the pulse generator. 3. A device according to claim 1, characterized in that the control unit comprises a modulo-two modularly connected adder, the inputs of which are the information input of the block, and a trigger, the synchronization input of which is the control input of the block. Sources of information taken into account in the examination 1. US Patent No. 3585599, cl. 340-172,5, publ. 1971. 2. USSR author's certificate according to application no. 2406048 / 18-24, cl. G About F 15/46, 1976. 746556  ar 1C S vby 1 ib to