SU734671A1 - Binary-to-numeric-pulse code converter - Google Patents

Description

(54) BINARY CONTAINER IN NUMBER 1

The invention relates to automation and computing and can be used in the construction of computing and conversion devices using the number-pulse representation of information.

A known converter of a binary-decimal code into a unitary code containing a binary-decimal counter on the counting decade, a number decoding scheme, a control trigger with a setup input, an AND element with a clock supply bus, an OR element with a unit impedance thickness, and input elements And, which are connected to the inverse bits of the binary-decimal code, the recording bar and the reset bar, connected respectively to the input elements AND and the counting decade 1.

The disadvantages of this device are low noise immunity and reliability, due to the fact that a false pulse received by the write bus distorts the information being transformed, and the asynchronous supply of clock pulses with input information causes a hit of the “pulse fragments”, i.e. The first pulse at the output of the device will be unnormalized. PULSE CODE

telnosti. In addition, the known device cannot simultaneously convert multiple code values, which significantly reduces its functionality.

The closest in technical essence is a binary-to-impulse code converter that contains the first conversion channel, which contains a binary counter, a group of AND receive elements, a control trigger, a NOT element, an Inhibit element, the first input of which is connected to a single output control trigger, the second input element And the prohibition through the element is NOT connected to the first inputs. And the group of elements AND reception, and the output element

j And the prohibition is connected to the counting input of a binary counter, the group of inputs of the unit of installation of which is connected to the outputs of a group of I elements of the input, and the output of the binary counter is connected to the counting input of a control trigger;

20 of the zero setting of which is connected to the input of the zero setting of the binary counter 2.

In addition, the known device contains a storage register, additional AND elements, single-shot, differentiating chains, OR overflow element, OR output elements, memory trigger, control trigger, inverter, B (pulse of different polarity, additional OR element).

The named converter makes it less likely that the output will be corrupted at the moment when the conversion process of the previous code parcel is not finished. However, this is achieved by a significant complication of the circuit, a decrease in speed and noise immunity, which is caused by the use of single vibrators, differentiating chains, AND elements in each bit, as well as the need to carry out a repeated control cycle. The known converter also does not exclude the appearance of a pulse of irregular duration at the output of the pulse and cannot produce several code values with minimal hardware costs at the same time, which reduces the noise immunity and functionality of the device.

The purpose of the invention is to increase the noise immunity and increase the number of simultaneously converted numbers.

The goal is achieved by the fact that the converter contains n transform channels, a counting trigger, an OR overflow element, an additional NOT element, a delay element, three AND elements, and all the conversion channels additionally contain a memory trigger, an AND control element and a multiple input OR element, and the output the counting trigger is connected to the third inputs of the elements AND prohibit all conversion channels, the counting input of the counting trigger through the first element AND is connected to the input of the additional element NOT and the output of the element OR overflow, the inputs of which are respectively connected to the unit outputs of the control triggers of all conversion channels, the output of the second element I is connected to the input of setting the counting trigger to zero and the installation inputs of zero binary counters and memory triggers of all conversion channels, the output of the additional element NOT through the delay and the third element And is connected to the first inputs of the group of elements And reception and the first inputs of the elements And all conversion channels, the second inputs of the group of elements And the reception of which responsibly connected to the inputs of the multi-input element OR in each of the conversion channels, the output of the multi-input element OR is connected to the installation input of the memory trigger unit, the output of which is connected to the second input of the AND element, the output of which is connected to the installation input of the control trigger unit.

The drawing shows the functional diagram of the device.

The binary-to-pulse code converter contains 1 conversion channels with 2 "Output, 3" Input, 4 "Record, 5" Reset, 6 "Overflow, 7" Output Code, Counting Trigger 8, First Element And 9, OR 10 Overflow Elements , the second element is NOT 11, the second element is And 12, the third element is And 13, the element 14 is delayed and the bus 15 "Initial conditions, 16" Strobe, 17 "Start, 18" Output pulses. Numbers to be converted are received via tires 19. 3 the composition of each channel 1 includes a binary counter 20,

 built on counting flip-flops 21n connected by its output with a control trigger 22, the output of which is connected to the input of the prohibition element And 23. Trigger inputs 24 memory and a group of elements And 25, 26

5 are connected to the inputs of the flip-flops 2, and the combined inputs of the named elements are connected via an inverter 27 to the corresponding input of the inhibit element AND 23, to the control input of the trigger trigger 22 via the control element AND 28 and the setting input of the trigger trigger 22 ty 24, Bus 18 "Input pulses through the first element And 9 connected to the counting input of the counting trigger 8, the output of which through the element

3 and 23 of the prohibition is connected to the input of the counter 20, and the output of the directing trigger 22 is connected to the corresponding inputs of the And prohibiting element 23 and the overflow element OR 10. The memory element OR 29 is connected to a single input of the memory trigger 24, the output of which through the control element 28 is connected to the single input of the control trigger 22.

The device works with. food way.

Before starting work, it is set to its original state by a bus signal.

15 "Initial conditions that are gated with a corresponding bus signal

16 "Strobe, forming a signal through the second element And 12.

In this case, the control triggers 22 of all the conversion channels 1 are set to the zero state and the output of the OR element 10 overflow contains a zero level covering the input element AND 9, and the counting triggers 21 of the counter 20 of all the conversion channels 1 are reset. . When entering the input elements And 25, 26 (tires 7 "Input code) code other than

g is zero, the output of the memory element OR 29 produces a signal that sets the trigger of memory 24 to the state "1. Further, the above code is rewritten by the signal "Start via elgment I 13, which in this case is opened by a single level,

coming from the output of the element NOT 11, to the counter 20. For the entire duration of the recording, the element And the prohibition 23 is closed by the zero level, G1 coming from the inverter 27. Oh, w. at the same time the unit level at the output

memory trigger 24 permits the recording signal to pass through control element 28 to a single installation input of control trigger 22, set it to state 1, after which the output of the OR 10 element overflow results in a signal allowing the input pulse sequence from the device bus 18 to the element AND 9 to the input of the counting trigger 8. The first pulse in this case sets the named trigger to state 1, the second to state O, etc., i.e. Through the AND 23. banned elements, opened by the signal from the control trigger 22, pulses of normalized duration pass, equal to the period of the pulses of the input sequence. The foregoing allows the device to be operable in the case where the 17 "Start signal falls on the end of the duration of the first pulse of the input sequence, i.e. It prevents the device from entering the counters of 20 pulses of irregular duration, which can lead to failures at the beginning of the processing of information. Further, the signals at the output of the And 23 ban elements of the respective conversion channels 1 are considered to be the corresponding counters 20 and are fed to the bus 2 "Exit. During the entire information processing time, the element And 13 is closed by the zero level from the output of the element 11, i.e. until the end of the entire cycle of operation of the device, it is impossible to influence false or non-converting information on buses 7 "Input code of the conversion channels or on the" Start device "signal. It should be noted that the delay time of the delay element 14 is selected from the condition of ensuring the operation of all control triggers 22. After the number of pulses arriving at the input of the counter 20 of the conversion channel 1 begins to correspond to the input code, the counter 20 generates a signal that sets the state to "O control trigger 22, which closes the element And 23 of the ban, i.e. This channel 1 conversion work completed. At the same time, a zero level is output to the corresponding input of the OR element 10 overflow. Since the input code on different channels can be different, the first ends the working out, closes the element AND 23 of the prohibition of the conversion channel, which received the smallest code value. Then finishes the work of the second, etc. channels. After all the channels have completed the specified input code values, zero levels will form at all inputs of the OR 10 overflow element, and the named element will generate a zero signal prohibiting the passage of the input pulse sequence through the E 9 element. In this case, the E 11 element produces a single level, allowing the passage of the recording signal and rewriting the input code. In the case when

in the wounds / "The input code is present zero information, then the AND control 2nd element does not control the memory trigger 22 and there is no processing of the information, i.e. this prevents the device from running full

5 the amount of information determined by the counter size instead of zeros. Each conversion channel 1 has bus 2 "Output, 3" Input, 4 "Record, 5" Reset, 6 "Overflow and 7" Input Code. Thus, the introduction of the element And 13,

About the overflow element OR 10 and the delay element 14 of the second element NOT 11, the element OR 10 allows to increase the noise immunity of the device by an amount determined by the ratio

$ L

T rp.

where Toy. is the time for working out the information, Tb. Introduction of the counting trigger 8, group

0 input elements 25, 26 And reception allows you to completely exclude the impulse duration of irregular duration on the pulse counters, and turning on the inverter 27 eliminates the passage of interference to the inputs of the conversion channels 1 at the time of recording the input

S information. The proposed device allows a single code message of the input information to provide testing of several code values per number of pulses, which increases the speed of the system as a whole and expands the functionality of the device.

Claims (1)

Invention Formula A binary-to-pulse code converter that contains the first conversion channel, which contains a binary counter, a group of AND elements, a control trigger, a NOT element, an AND element the prohibition, the first input of which is connected to the unit output of the control trigger, the second input of the input of the prohibition is NOT connected to the first inputs of the group of I receive elements, and the output of the prohibition input connected to the counting input of the binary counter With the help of a group of elements AND of the reception, and the output of the binary counter is connected to the counting input of the control trigger, the input of the zero setting of which is connected to the input of the zero installation of the binary counter, characterized in that increase noise immunity and increase the number of simultaneously converted numbers; it contains n transforming channels, a counting trigger, OR element overflow, additional element NOT, delay element, three of the And element, and all conversion channels additionally contain a memory trigger, an And control element and a multi-input element