SU720816A1 - Device for multiplexing tv signals - Google Patents

Description

(54) DEVICE FOR COMPRESSION OF DIGITAL TELEVISION SIGNALS

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 5 W18, in addition, the output of the first comparison unit is connected to the input of the entered ZEPLISHISCHIx discharge unit, the other input of which is connected to the third output of the third memory register, and the output to a tetwerth input of the memory unit and the input lower memory unit, output connected to the fourth input of the unit to

The drawing shows the structural electrical circuit of the proposed device.

The proposed device for compressing digital TV signals contains ADC1, block 2 of bitwise comparison, block 3 for selecting a re-D character, memory card 4, control block 5 for memory, block 6, block 7 for setting the reference level, driver 8 for synchronization code, block 9 time intervals, switching unit 10, three registers 11, 12 and 13 of memory, two comparison units 14 and 15, unit 16 of the lower-order record, block of memory 17 of the lower-order, control unit 18 of the record.

The device works as follows. The input analog signal is fed simultaneously to the inputs of the A / D converter 1 and block 7. In block 7, the sync signal is selected, from to; by whose power the memory block 6 and the block 9 are installed in a certain state. The sync signal information is transmitted by the FingerName code, which is generated by the shaper 8, which is triggered by a signal, from the output of block 7. The seven-digit code from the output of A / D converter 1 is alternately recorded three registers 11, 12 and 13, which are a set of triggers. The code from the output of the third register 13 is fed to the second input of block 2, to the first INPUT of which bits of the code entered in memory block 6 are applied. Results

 comparisons in the form of logical levels of "zero in the absence

the logical "edy1nG" in the presence of changes is fed to block 3, which determines in which of the bits the change of characters in the sample should be transmitted. At the output of the block 3 logical level x units translate the 6 in. Memory block. the opposite of the previous state. From the outputs of coding block 4, the code is read

in the switching unit 10. Information in the unit

switching 10 is recorded by the SCHEDULE through sampling either from the output of coding block 4, or directly from the first three bits of the third register 13. Recording is controlled from block 9, which is triggered by nmt pulses of the ADC 1 samples. At the same time, the time of the first time (the four most senior code codes are written to the memory block. 6) For the 6 differences, in the four senior bits of two adjacent samples containing information about the true state of these bits, the first comparison block 14 serves. 15 performs a function720816

Comparison of the four most significant bits of the true code value from the third register 13 and the four most significant bits from the Old register 12, the states of which are transmitted as information about the number of code bits in which the change occurred. When the trigger states of the four most significant bits in the first block of comparison 14 match, the resolution signal is received; to the control unit 18, which records the true data of the next bits from the third register 13 to the memory block 17 and simultaneously to the memory block 6. Information from the memory block 17 is written to the switching unit 10. In case The first comparison block 14 signals that there are no changes in the higher bits, and the second comparison block 15 indicates that there is a change in at least one bit, then the control block 18 issues a ban on rewriting information from the second register 12 to the third register 13, and sample containing information about the bit number code transmitted information about the absence of variations, and the receiving side simply repeats the previous information.

The proposed device is distinguished by JT known in that, when it is used, with the same compression ratio, the system noise immunity is significantly increased due to the transmission of the true value, six bits of the source code in the areas of constant luminance. Significantly increases the rate of increase in large differences in brightness. ,

Claims (1)

Invention Formula A device for compressing digital television signals comprising successively connected bit-matching unit, a transmission symbol selection unit, a coding unit and a switching unit, another output of the transmission symbol selection unit, is connected via a memory management unit to the memory unit whose first output is connected with the first input of the bitwise comparison unit, the second output of the memory unit is connected to the second input of the memory management unit, and also the unit for setting the reference level, the input of which is connected to the input the analog-to-digital converter and the output are connected to the synchronization code generator, to the second input of the memory unit and to the first input of the time interval unit, the second input of which is connected to the input of the analog-digital converter and the output to the second input of the switching unit, output which is connected to the third input of the memory unit, while the output of the synchronization code generator is connected to the second input of the coding unit, characterized in that, in order to increase the noise immunity of the device, serially connected three memory registers, the first of which is connected to another output, an analog-to-digital converter, and the first output of the third register is connected to the second input of the bit comparison unit, the second outputs of the first and second memory registers are connected to the first inputs of the entered the first and second comparison bays, the other inputs of which are connected to the second output of the third memory register and the third input of the switching unit, while the outputs of both comparison units are connected to two inputs of the inputted recording control unit, the output of which is connected to another input of the third register memory, and the third input - with the output of the time interval block; in addition, the output of the first comparison block is connected to the input of the lower-order block, the other input of which is connected to the third, its third memory register output, and the output - to the fourth the input of the memory block and the low-order memory block inserted, the output connected to the fourth input of the switching unit. Sources of information taken into account during the examination - 1. USSR author's certificate for application No. 2502212, cl. H 04 N 7/18, 1977, (prototype).