SU717745A1 - Device for control of the period of timing pulses of computing system - Google Patents

Description

(54) PERIOD OF MANAGEMENT OF THE PERIOD

OF CLOCK SYNCHROIMPULSES OF A DIGITAL COMPUTING SYSTEM

an input with a time sensor, an output with a time setting block 4 and an additional output with the first input of the monitoring unit 6. Two counts of the number of failures are connected by a counting input with the first input of the device, the signal to which is fed from the output of the monitoring device of the computing system, and the second input of the monitoring unit 6 The output of this counter is connected to a circuit 5 comparing the number of faults. The output of the control unit 6 is connected to the setup inputs of the unit 4 for setting time intervals, frequency code 1 and circuit 5 for comparing the number of faults. The output of the time interval setting unit 4 is connected to the first input of the frequency code 1 counter and the AND-OR element 7. The output of the circuit 5 for comparing the number of faults is connected to the second input of the frequency code 1 and the second input of the AND-OR element 7 -The third input of this circuit is connected to the second input of the device, the signal to which is supplied from the time sensor, and the output to the installation inputs of the counter 2 is the accumulator and the counter 3 of the control time interval.

The device works as follows.

After switching on, all the blocks are in their original state. The contents of the counters are zero. On the 4 time interval setting blocks, the control 6 and the circuit 5, the nominal value codes are fixed compared to the number of failures. For example, the zero value in scheme 5 and the code corresponding to the duration of the computer system self-tests at block 4. The zero value of counter 1 corresponds to the nominal value of the clock period calculated for combinations of all parameters using the worst case method. In the event that the system allows for faults during the self-test phase, the initial state of circuit 5 may be different from zero.

In the initial state, the signals at the output of the control unit 6 are absent.

In the process of operation, time stamps arrive at the input of the counter 3 and block 4 continuously compares the current code value in the counter with the value of the interval code recorded in its register. In case of coincidence, a sigma is generated, which goes to the first (summing) input of the counter 1 of the frequency code and through the element I, by coincidence with the next time stamp, goes to the resetting inputs of counters 3 and 2, which are reset. After setting the counter 3 to the initial state, block 4 removes the signal from the input of counter 1. 1 If there is no signal from the output of circuit 5, the content of counter 1 of the frequency code is increased by one, which corresponds to a decrease in the period of synchroims following:

At the input of the counter 2, the number of failures in the process of receiving signals from the controllers of the system.

The signal of the control device is removed from the input of the counter after performing recovery. The counter 2 of the number of failures counts this signal and its content corresponds to the current value of the failure signal in the monitored interval. The comparison circuit 5 compares the current code value in the counter with the code recorded on its register and, if it coincides, produces a signal arriving at the second (subtractive) input of counter 1 and at the element I. OR. After the arrival of the next timestamp

the output of the AND-OR element passes the signal that arrives at the installation inputs of counters 2 and 3. By this signal, counter 2 returns to the initial (zero) state, the signal from the output of the comparison circuit 5 is removed

and the unit is subtracted from the contents of counter 1 if there was no signal at the output of block 4. A decrease in the counter code I corresponds to an increase in the clock time and, therefore, the speed of the CTieMbi. The frequency code does not change if the output of block 4 and the comparison circuit 5 signals appear simultaneously. This corresponds to the case of coincidence of the number of wallpaper, for-. fixed in the control interval, with

boundary limit value.

The control device signals are also sent to the input of the control unit 6. This unit, when the signal from the control device is received from the control unit, receives the contents of counter 3 at the time the signal occurs, sums it up with the code of the maximum permissible recovery time interval and switches to the comparison of the amount received with the current counter code 3. If the signal of the control device is not a signal. until the control recovery time has elapsed, the control unit generates a reset signal that switches counter 1 to the initial state. Simultaneously with this reset signal, block 4 and

Comparison circuit 5 goes to the ON state, blocks the change in state of counter 1, and resets counters 2 and 3 to the initial cue. The control unit removes the reset signal at its output after the control device removes the signal.

This mode of operation provides a smooth tuning of the clock frequency and keeping it at a value close to the optimal one.

In the event that some external conditions lead to an abrupt change in the speed of the devices, for example, in the direction of its increase, then at several time intervals by a successive increase in the value of

Claims (1)

Claim The control unit period of the sync clock of the digital computer Cu 2 ₀ tem comprising the counter of failures, input of which is the first input device monitoring time interval counter, the input of which is the second input-device code frequency counter whose output yavlyaet- output devices 25 camping , characterized in that, in order to increase the effective speed of the digital computing system, a block for setting time intervals, a circuit for comparing the number of failures, an AND-OR element, a block of In this case, the time interval setting unit is connected by an input to the counter of the control time interval, and by an output - to the first input of the frequency code counter and the AND-OR element, the circuit for comparing the number of failures is connected by the input to the counter of the number of failures, and by the output - to the second input of the frequency code counter and the AND - OR element, the third input of which is connected to the second input of the device, and the output to the installation inputs of the counter of the number of failures and the counter of the control time interval, the additional output of which is connected to the first input of the control unit, Torah input of which is connected to first input device and an output control unit connected to a frequency adjusting input code counter unit set time intervals and the number of failures of comparison circuit.