SU703852A1 - Pseudorandom number generator - Google Patents

Description

(54) GENERATOR OF PSEUDICAL NUMBERS

one

The invention relates to the field of computing and can be used in the simulation of random processes.

Pseudo-random number generators are known based on shift registers with modulo-two adders in feedback circuit 1.

However, generators of this type have a significant drawback. In the case of a sample of the next pseudo-random number, a hard correlation is observed between the subsequent values of the multi-digit pseudo-random number codes at each device operation cycle. In order to avoid the presence of a correlation dependence in such devices, it is necessary to sample the output numbers only after 1: cycles, where is the pseudo-random number, and an is the shift register size. But at the same time, a second major drawback appears - a low speed, which in the limiting case is n times less than the clock frequency of the device.

These drawbacks are eliminated in a number of devices that allow to generate multi-bit uncorrelated pseudo-random numbers at each tick.

The closest technical solution to this invention is a pseudo-random number generator containing the first and second shift registers 2.

Such a generator allows one to generate multi-digit codes at each cycle of the device operation, however, it has a small period of a sequence of pseudo-random numbers.

The aim of the invention is to extend the functionality of the generator by increasing the period of the generated sequence of pseudo-random numbers.

Claims (2)

To achieve this goal, the generator contains the first and second frequency dividers, the NAND element, the AND element, the OR element group and the AND element group, whose outputs are connected to the inputs of the second shift register, respectively, whose outputs are the generator outputs and through AND-HB connected to the first inputs of a group of elements OR, whose outputs are connected to the first inputs of a group of elements AND, respectively, the second inputs of which are connected to the outputs of the first pefStrpa with the engine and yygo input, the input “sd to ig” is connected The output of the second frequency divider, the input of which is combined with the second inputs of the group of elements OR, and is connected to the first input of the element And and To the output of the first frequency divider whose input is the input of clock pulses and connected to the second input of the element And whose output is connected to the input shift second shift register. The block diagram of the generator is shown in the drawing. The generator contains the first and second recurrent registers 1 and 2 of the shift, the first and second dividers 3 and 4 frequencies, a group of 5 elements I, the inputs of which are connected to the outputs of the register, 1 and a group of 6 elements OR, and the outputs - with the inputs of register 2, the outputs of which through the element AND-7 is connected to the inputs of a group of 6 elements OR, the second inputs of which are combined with the input of the element 8, are connected to the output of the first divider 3 frequencies and through the second divider 4 frequencies are connected to the input "register shift 1. The input of clock pulses is connected with the entrance of the first divider 3 through the element and the frequency I. 8 - to the input "shift register 2. The generator works as follows. After the initial entry of arbitrary numbers in registers 1 and 2, the signals of the clock pulse generator in register 2 begin to change states with a period L In the (1) st operation, the 3 hours divider signal: the total values of register bits 2 are modulated from two a value located in the bits of register 1. A new number is obtained in register 2, which gives rise to a new elementary cycle. During the () -th cycle of operation of this cycle, the following change occurs in the state of register 2, and so on. Element 8 is necessary to prohibit a change in the state of register 2 in the cycle of summation. Since the division factors of 3 and 4 are equal to 1, T O during the cycles of summation from register 1 is 11fMEDDG% TYNESSL ag & same number. The second term, which is in register bits 2, is new in each tact cycle, so there will come such a factor, when the terms match, and because the summation modulo two is random, the result will be a zero sequence. In this case, the element AND-NOT 7 is triggered and the signal on.,., -. .------ f. --.-- .. - - -. - -t, -. ™ 1 -..-:;. wi-4., Jtjt ..--- -; G - - .- its output will permit the execution of one more summation in the next cycle of operation, the result of which will be a BUT & 6yo 6lO1 in register 2. One more tact of summation is necessary, because otherwise the register is in progress. ticks would generate only a null combination. The number "O we get with the period () () + L. After 1.tkb in summation, the state of register 1 changes, it will now receive a new number, and the whole previous cycle repeats. This will continue until such time as register 1 passes its full period. Thus, the total period of the sequence produced by the proposed generator is defined as T: () () + 1 (2-1) (). Using the proposed pseudo-random number generator will make it possible to obtain pseudo-random numbers with a sufficiently large repetition period without significant hardware costs, which is especially important when used in probabilistic converters and in devices for converting input information of stochastic computing machines. The possibility of obtaining the number "O at the output of this generator improves the quality of the output sequence of binary numbers. Claims Pseudorandom number generator containing the first and second Shift registers, characterized in that, in order to expand the functionality of the generator by increasing the period of the generated pseudorandom number sequence, it contains the first and second frequency dividers, the AND-NOT element, the element, the group of elements OR and the group of elements AND, whose outputs are connected to the inputs of the second register SvTT1 GASO, respectively, whose outputs are the outputs of the generator and, through the AND-NEA element, are CONNECTED with the first inputs rows or groups of elements, the outputs of which are connected to first inputs of the group of AND gates, respectively, second inputs of which are connected to the outputs of the first shift register, respectively, input "shift which is connected to the output of the second divider; the frequency bodies whose input is combined with the second inputs of the group of elements OR AND is connected to the first input of the AND element and to the output of the first frequency divider, whose input is the INPUT of clock pulses and connected to the second input of the AND element, output K0t0p 0g0 is connected to the input "offset of the second shift register. Sources of information, pr Tye yo attention in the examination. 1. V. Yakovlev and R. F. Fedorov, Stochastic Computing Machines. L., “Mechanical Engineering, 1974, p. 246-270. 2. USSR author's certificate number 436340, cl. G 06 F 1/02, 1973 (prototype). about , Ogrg ; | PG T -f :: x