SU696510A1 - Pseudorandom code generator - Google Patents

Description

The invention relates to the field of computer technology and can be used as generators of verification codes in installations using various probabilistic methods for detecting failures in digital circuits, as well as sensors generating binary pseudo-random codes with an arbitrary number of units for machine synthesis of control tests. A pseudo-random code generator containing triggers with counting and set-up inputs and forming only uniformly distributed pseudo-random codes 1 is known. The pseudo-random code generator is closest in technical essence to the pre-polled invention and contains a shift register with modulator two in the reverse link, a modulator. the shift, each bit of which contains a tripper, the first, second and third elements AND, and the element OR, and whose inputs are connected to the output of the second and third elements AND, first The second input of the second e-plug And is connected to the trigger output, and the second input of the second element And is combined with the second input of the third, Lemme-1t I and connected to the first input of the first element And, the output of which is connected to the second input of the trigger, and the second input of the first element AND is the input of clock pulses, the output of the element OR of each bit is connected to the first trigger and the third element AND the subsequent bit 2. However, this generator does not allow generating pseudo-random codes of constant weight. The purpose of the invention is to enhance the functionality of the generator by generating pseudo-random codes of constant weight. To achieve this goal, the generator contains a block for specifying the code weight, the input of which is connected to the output of the element OR the last bit of the shift register, and the output of the block for specifying the code weight is connected to the first inputs of the trigger and the third element And the first digit of the shift register, the shift register with an adder modulo two in the feedback circuit is connected to the first inputs of the first elements I ka: the one bit of the shift register respectively.

The drawing shows a functional diagram of the generator.

The generator consists of an n - bit shift register 1 consisting of flip-flops 2. A single output of flip-flop 2 in the i-oM bit is connected; with the input element And 3, the output of which through the element OR 4 is connected to the information input 5 of the trigger 2 in (i + l) -oM bit and to the same input of the element And 6 also in the (1 + 1) -th bit. The zero outputs of the trigger 7 of the p-bit shift register 8 with a modulo two adder are connected in each bit with the inverse input of the element 6, and also with the input of the element 3 and with one input of the element 9, the second input of which is connected to the clock bus signals 10, and the output is connected to the clock input 11 of the trigger 2. The output of the element And 6 is connected to the input of the element OR 4. The output of the element OR 4 is the last bit through the block specifying the weight of the code 12 connected to the INPUT ;. 5 flip-flops 2 in the first category and with one input of the element And 6 in the same category. To the inputs of the block 12 connected tires 13 and 14 sets the weight of the code.

The generator will consider the example of dl.

Before starting, the code is set; To do this, in order to set the weight of the code 13, units in a quantity equal to the specified weight of the code P are received. At the same time, the shift register 8 with the cyKiiviaTopoM modulo two in the feedback feedback circuit is not fed and the register 8 retains its original (zero) state. As long as all the triggers 7 of register 8 remain in the zero state, the signal from the single output of trigger 2 in any bit goes through the elements AND 3 and OR 4 to the information input 5 of trigger 2 of the next bit. When the clock signal arrives at the inputs of 11 all triggers 2, it is written to the trigger 2 (i + l) -ro of the information discharge from the output of trigger 2 i-ro bit. Thus, the units arriving on the bus 13 are shifted in register 1 in the usual way and fill the first P bits of the switch.

After the weight has been set, the clock signals are sent to register 8. In register 8, a pseudo-random sequence of zeros and ones is formed.

The process of forming code combinations in register 1 proceeds as follows. For example, the code in the register is 0110, and in the previous clock on register 1, the code combination 1100 was formed. In this case, the zero signal from the zero output of the second and triggers

The third bit will close the I and E elements in the corresponding bits, so the clock signals 10 will not pass to the inputs of 11 triggers 2 in the second and third bits and these triggers will retain their state. At the same time, a single signal from a single output of flip-flop 2 of the first bit goes through the elements AND 3, OR 4 in the first bit and through the open zero signal from the trigger of the triggers 17 elements And the second bit goes further through the element OR 4 of the second bit and an open zero signal from the trigger output 7 of the third bit of the element AND 6 through the element OR 7 to the input 5 of the trigger 2 of the fourth bit. The considered signal does not pass through the fourth-bit element B of the fourth bit, since it is closed by a single signal from the output of the fourth trigger of the fourth digit. On input 5 of trigger 2 of the first bit, the zero signal from the output of trigger 2 of the fourth bit acts. At the time of the clock signal 10, the unit will be recorded in quarTs tr: -1yr 2 and zero to the first trigger 2. As a result, code 0101 is generated on register 1.

In the same way, when shifting the code bits jump over triggers.

units in correspondence

the corresponding bits of the register 8. Marked triggers 2 retain their previous state. At the same time, the number of ejanHHU in the code on register 1 remains unchanged; -.

Since the sequence of zeros and ones at the outputs of register 8, which is equal to the code shift in register 1, is a pseudo-random sequence (with equal probability

), then

occurrence

and

the mixing of units in register 1 will occur in random order and pseudo-random constant-weight code combinations will be generated at the outputs, and the mathematical

one

in binary

waiting on appearance

the sequence at the output of any register bit 1 will be equal to the value of ir p P - the weight of the code, an - the number of bits of the register 1.

The weight of codes generated on register 1 can be changed without stopping during operation of the device using the code weight setting block 12. For this, the required number of pulses (units) is fed to the input of block 12 via bus 13 in case of i weight increase or bus 14 in the case of reducing the weight of the generated codes.

The generator can be used as a sensor for input sets in automatic test synthesis systems for complex logic circuits. At the same time, in a number of methods of searching for control tests such properties as