SU657455A1 - Device for shaping synchronizing pulses at information reproduction from magnetic carrier - Google Patents

Description

dsrzhki - to the input "reset of the second trigger, the output of which is connected to the second input of the second match unit, the output of which is connected to the installation input of the third trigger, the output of the first trigger is connected through the second delay unit to the second input of the first match unit, the inputs of the second assembly are connected to the inputs of the phase the detector, the outputs of the second and third assemblies are connected to the inputs of the third coincidence unit, the output of which is connected to the input "reset the third trigger, through the fourth assembly to the input" reset the first trigger, and output d of the first flip-flop is connected via a third delay unit to the input of the fourth assembly .;

FIG. 1 shows a block diagram of the described device; in fig. 2 - block. M is the block for determining the permissible pulse mismatch.

The device contains a phase detector 1, a pulse generator 1, a voltage controllable, delay blocks 3 and 4, a match block 5, 6, a block 7 for determining the allowable pulse error at the inputs of the phase detector, a match block 8, 6.:iOK pulse duration in amplitude, block pa.mti 10, block 1 I setting the mode of operation of the device.

FIG. 2 denotes: 12 - assembly, 13 and 14 - blocks of coincidence, 15 and 16 - triggers, 17, 18 and 19 - delay blocks, 20 - trigger, 21, 22, 23 - assemblies, 24 - block of coincidence, 25 - source pulses.

The device works as follows.

In case of untimely occurrence of pulses at one of the inputs, phase detector 1 generates wide signals, I receive one of the delay blocks 3 or 4 at the inputs of matching blocks 5 or 6. Block 7 for determining the permissible pulse mismatch generates signals, passing signals from the output of the delay blocks 3, 4 through the match blocks 5, 6. The mode setting unit 11 outputs a signal in the initial tuning mode of the drive, allowing the passage of 5 and 6 sigals of any duration through the match blocks. This provides a change in the frequency and phase of the pulses of the pulse generator 2 with a significant initial mismatch of the moments of arrival and pulses at the input of the phase detector 1. The inputs of the assembly unit 12 receive pulses from the outputs of the phase detector 1.

The pulses from the output of the assembly 12 are fed to the coincidence blocks 13, 14. The pulse from the output of the coincidence block 13 charges the triggers 15 and 16 and enters through the delay block 17 to the input "reset trigger 16. The trigger 15 in the set state is given by a signal delay 18, prohibits re-cocking triggers 15,

16 during the time determined by the delay time of the delay block 19. The trigger 15, the delay block 18 and the match block 13 provide one-time cocking of the trigger 16 for a signal of considerable length from the output of the assembly 12. The trigger 16, after setting, outputs a signal to the 6jio connector 14 with a level prohibiting for a time determined by the delay time of the delay block 17, the passage of signals through the coincidence block 14. That is, if the output of the assembly has a duration shorter than the detectable value (determined by the delay time delay block 17), the trigger 20 remains in the cleared state, and the matching blocks 5, 6 skip signals that change the frequency and phase of the pulse generator 2. If the output signal of the assembly 12 has a duration longer than a certain value, the trigger 20 will be set to When the impulse through the blocks of coincidence 5, 6 is prohibited. The signal from the output of the trigger 15, passed through the delay block 19 and the assembly 21, resets the trigger 15. This enables the re-cocking of the triggers 16 and 20. The same pulses go to the input of the assembly 22 as the phase inputs Vågå detector 1. On the assembly 23 inputs pulses output from the delay units 3 and 4.

The coincidence circuit 24 produces a pulse resetting the trigger 15, in the presence of a pulse at the output of the assembly 22 and no signal at the output of the assembly 23.

The device can perform its functions without a source of pulses 25.

FIG. 1 and 2 do not show inverters that may be necessary to match the polarity of the signals.

The described device does not change the frequency and phase of the generated pulses when the pulses disappear or are not timely generated at one of the inputs of the phase detector, is able to work when recording information in any known manner and has increased reliability of operation.

Claims (2)

1. A device for generating synchronizing pulses when reproducing information from a magnetic carrier, comprising a phase detector, one of the inputs of which is connected to the output of the pulse generator, a pulse width and amplitude conversion unit, the output of which is connected to the input of the memory block connected by the output to the input of the pulse generator , characterized in that, in order to increase the reliability of the device, it is equipped with two delay units, three coincidence units, a unit for determining the permissible error ovan and unit installation mode of the device. the output of the phase detector is connected to the inputs of the permissible error matching unit and the outputs of the delay unit whose outputs are connected to other inputs of the permissible error detection unit and to the first inputs of the first two matching blocks, the second inputs of which are connected to the output of the third matching block, the outputs of the two matching blocks are connected to the inputs of the pulse-to-amplitude conversion unit, the inputs of the third coincidence unit are connected to the output of the permissible error matching unit mpulsov and to the output mode setting unit of the device. 2. The device according to claim 1, characterized in that the pulse error detection unit is made of four assemblies, three coincidence blocks, three delay blocks and three triggers, the output of the first assembly, whose inputs are connected to the outputs of the phase detector, connected to the first inputs first and second blocks match, the output of the first match block is connected to the setup inputs of the first and second triggers, through the first delay block to the input "reset the second trigger, the output of which is connected to the second input of the second match block, the output of which is connected to the setup input of the third trigger, the output of the first trigger is connected through the second delay unit to the second input of the first matching unit, the inputs of the second assembly are connected to the inputs of the phase detector, the outputs of the second and third assemblies are connected to the inputs of the third matching unit Whose output is connected to the input "reset third flip-flop, and via the fourth assembly - to the input" reset the first flip-flop, and the output of the first flip-flop is connected via a third delay unit to the input of the fourth assembly. Sources of information taken into account in the examination 1. US patent No. 3414894, CL. 340-174.1, 1973.