SU622017A1 - Harmonic signal frequency meter - Google Patents

Description

one

This invention relates to the field of radio measurements.

A device for frequency measurement is known, which contains a drive in which the result of the previous measurement is recorded, a frequency doubler, the signal from which a decade counter and additional counters are transmitted through a gate opened for a certain amount of time.

This device does not deplete sufficiently (w accuracy.

The closest in technical essence to the invention is a device containing a counter, one input of which is connected to a gate through a series-connected shaper of reset of the counter and a time relay, the second input of the counter is connected to the input signal bus through a series-connected pulse selector, and the counter outputs, bit by bit, are connected to the inputs of the decoder; three valves, the outputs of which are connected to the first inputs of the trigger, the outputs of which are connected to passages device interrogation pulse generator, which is connected to the output time switch input and a delay element.

The device prototype does not provide sufficient reliability of measurements.

In order to increase measurement reliability in a device containing a counter, one input of which is connected to the strobe pulse bus through serially connected pulse shaper pulse generator and a time relay, second counter input of the counter is connected to the input rot signal through the serially connected time selector the bottom is connected to the inputs of the decoder, three valves, the outputs of which are connected to the first inputs of the trigger, the outputs of which are connected to the outputs of the device, form The polling pulse generator, whose input is connected to the time relay output, and the delay element, are entered into the analyzer, the trigger reset pulse shaper, three additional counters, three additional gates, the first inputs of which are connected to the decoder outputs, and the second additional gates outputs are connected to the polling pulse shaper , at the same time, the first inputs of additional counters are connected to the outputs of additional Veptlles, and the second inputs of additional counters are combined and through the delay element are connected to moat output analyzer, whose inputs

connected to the inputs of the trigger pulse trigger generator and the outputs of additional counters, the second analyzer output is connected to the control input of the trigger trigger pulse generator, the outputs of which are connected to the second trigger inputs.

The structural electrical circuit of the described device is shown in the drawing.

The device contains time relay 1, driver 2 pulses, driver polling 3 polling pulses, driver 4 pulses resetting the counter, time selector 5, counter 6, decoder 7, gates 8-13, additional counters 14-16, triggers 17-19, driver 20 pulses trigger reset, analyzer 21, delay element 22. Strobe pulses are fed to bus 23, and input signal to bus 24. The output signals are removed from the outputs 25-27.

The principle of operation of the device is as follows.

The input signal on the bus 24 is fed to the driver 2 pulses, which generates pulses corresponding to the moment of crossing by the input signal of the bullet voltage level.

1- {and the input of time relay 1 via bus 23 receives two consecutive pulses, the first of which determines the beginning, and the second - the final completion of the timing. Relay 1 gmemepi generates a pulse that determines the frequency measurement time and opens the time selector 5. During this time, the number of pulses arriving at counter 6 corresponds to a preliminary estimate of the frequency of the input signal. The decoder 7 identifies the number of pulses in the counter 6 with the number of the frequency band and generates a signal that opens one of the gates 8-10.

On the falling edge of the pulse coming from the time relay 1, the polling impulse generator 3 generates a pulse, which acts on the second inputs of the valves 8-10, and in the generator 4 of the counter reset pulses, an impulse is generated that is delayed for some time relative to the impulse polling pulse of 8-10 which sets the counter 6 to the initial state.

When one of the gates 8-10 of the signal from the decoder 7 and the pulse from the generator 3 polling pulses is present at the inputs, a unit is recorded in the corresponding additional counter 14-16 connected to this gate 8-10.

The measurement process is then repeated. By filling in one of the additional counters 14-16 opens connected with

The valve is 11-13, and the analyzer 21 calculates the difference between the number of units in this and the other counters 14-16. When the minimum difference of a given value increases, the analyzer 21 generates a pulse, which, through a corresponding open valve 11-13, sets the corresponding trigger 17-19 to the single state and starts the driver 20 of the flip-flop triggers, which sets the rest of the triggers 17-19. the If any counter 14-16 is set to zero, the minimum difference of the set value is not exceeded, then the second inputs of the valves 11-13 and the driver of 20 trigger reset emulsions will not be affected by the pulse from the analyzer output 21. Therefore, the state of the trigger 17 19 does not change. Counters 14-16 after triggering of analyzer 21 are set to zero state by pulses passing through delay element 22.

Claims (1)

Invention Formula A device for measuring the frequency of a harmonic signal, containing a counter, whose input is connected through a serially connected reset reset pulse generator and a time relay, is connected to a rotary gate, the second counter input is connected via a successively connected time selector, and a pulse shaper is connected to the input signal bus, and the outputs of the counter are connected with the inputs of the decoder, three valves, the outputs of which are connected to the first inputs of the trigger, the driver of the polling pulse, the input of which is connected n with a time relay output, and a delay element, characterized in that, in order to improve the reliability of the memory, an analyzer, a trigger generator for resetting flip-flops, three additional counters, three additional valves, the first inputs of which are connected to the outputs of the decoder, are entered into it, the second inputs of additional gates are connected to the interrogation pulse shaper, while the first inputs of the additional counters are connected to the outputs of the additional gates, and the second inputs of the additional counters are combined and through the element The holders are connected to the first OUT} of the analyzer, the inputs of which are connected to the inputs of the trigger pulse reset generator and the outputs of additional counters, the second analyzer output is connected to the control input of the trigger reset pulse generator, the outputs of which are connected to the second trigger inputs. 25 27 ge