SU561955A1 - Multiplex channel - Google Patents

Description

by channels connected to the channel, the I / O path of the I / O interface-external devices is possible only if there is a complete set of elements of this chain, and this test requires the installation of a storage medium (punched card, punched tape) on the external device. In addition, such a check is impossible during the operative operation of external devices and does not allow checking and predicting the state of the I / O interface path.

The aim of the invention is to increase the reliability of operation. In the described multiplex channel, this is achieved by introducing a comparison unit, the first input of which is connected to the second output of the interface unit with external devices, and the first output - to the fifth output of the channel, the address setting unit, the output of which is connected to the second input comparison unit, data driver, the first input of which is connected to the fourth channel input, the second input is connected to the output of the comparison unit, the third input is connected to the second input of the comparison unit, and the first and second outputs are connected respectively to Normally, the channel output and the third input of the comparison unit, the driver of the control signals, the first and second inputs of which are connected to the fourth input of the channel and the second input of the data generator, and the first output is connected to the sixth output of the channel, the command driver, the first input of which is connected to the second output control generator, their signals, and the output is connected to the fourth input of the comparison unit, the third input of the data register and the second input of the interface unit with external devices.

The drawing shows the block diagram of the described multiplex channel.

The block diagram contains a unit 1 interface with the central processor, unit 2 interface with the central RAM, subchannel register 3, control register 4, cell address modification block 5, information register 6, local memory block 7, interface block 8 with external devices, comparison unit 9, address setting unit 10, register I of data, driver 12 of control, their signals, command driver 13 and interface control unit 14.

The operation of the described multiplex channel in standard modes for receiving and transmitting information between the central random access memory and external devices consists in the fact that when the instruction “Start I / O from the processor to the channel” is received, the conjunction block 1 with the central processor issues an instruction sign and the number code external device for fixing on the register 3 subchannel. Through the unit 2 of the interface with the central memory, the address word is received into the channel.

channel n on it is the control of the channel word with fixing the control information of the subchannel on the control register 4. The modification of the addresses of the central RAM memory cells is carried out by the unit 5 of the modification of the addresses of the cells, the data exchange with external devices via the information register 6. A condition code is generated in interface unit 1 with the central processor. In parallel with the reception of control information into the channel, the address located on the subchannel register 3, through the interface 8 with external devices, is used to initialize the external device, exchange service information with it and send the command code to it. When executing the command "Read received from an external device via interface 8 with external devices, data bytes are formed into words on register 6 information and, as they are formed, are transmitted to interface 2 with central memory and then into central memory . The address of the cell is issued from the unit 2 in conjunction with the central operational memory. The command “Write the order of information transfer is reversed: via the block 2 of the interface with the central operative memory, register 6 of information and then byte-by-bit via the block 8 of the interface with external devices to the external device. The control information of the subchannel is stored in block 7 of the local memory, where it is recorded after the end of service of the external device and from where it is retrieved when processing of the next data byte begins. The data is exchanged as soon as the external device is ready for their transfer, for low-speed devices - in the channel time division mode (in the multiplex mode). If the external device is ready to transmit a data byte, it places a service request on the channel. The channel fetches the address of the external device making the request. At this address, registers 4 and 6 are received from block 7 of the local memory, the control information of the subchannel and the data word, the data byte is exchanged with the external device, and the modified control information and the data word are returned from registers 4 and 6 to block 7.

There are time intervals (pauses) in the multiplex channel operation when the channel is not busy with data transmission. During such a pause, the address from address setting block 10 is provided to block 8.

The de-assigned address is received on the register I of the data and compared by the comparison unit 9 with the address present in this block. In the case of the comparison of addresses, the address from block 10 is transmitted through the register I of data to the block 8 of interface with external devices. The shaper of 13 teams sends to the block 8 a nervous command of the control test

(for example, “Read). The command goes to the data register 11 and then to the control signal generator 12, which determines the further course of the operation. The command generator 13 generates a zero byte of the status and sends it through the data register 11 to block 8, confirming the normal execution of the operation. Next, control data bytes are transmitted via the interface. The command "Read data bytes" is transmitted from the shaper 13 of the commands through the data register 11 to block 8 and sent for comparison with those in the shaper 13 to block 9 of the comparison. The "Write Data Bytes" command is transmitted from the driver of 13 commands to block 8, then to the register I of data and compared by block 9 of comparison with the existing byte at the output of the driver of 13 commands.

In the process of transmitting control information, the presence of requirements for servicing from other external devices, the presence of new designs from the central processor, the need for issuing interrupts, etc. are constantly analyzed. The presence of at least one of these conditions having higher priority interrupts the execution of the control test, I / O interface. The interface control unit 14 is logically disconnected from the I / O interface. The channel switches to the operational mode of execution of the main data exchange programs. During the next pause, the interface control unit 14 issues a service request, block 8 samples the interface control unit 14 via the I / O interface, and the control bytes of information are resumed.

Claims (2)

1. USSR Author's Certificate No. 453685, G 06F 3/04, 1974. 2. Kagai, BM and Kanevsky, MM Digital computers and systems. Energie, 1974, p. 509-513. i I: cz: z ± u