SU479105A1 - Device for coupling a computer with on-off pulse sensors - Google Patents

Description

The average frequencies of all these devices are so high that the probability of P < I, /) overlaying n messages increases to values at which the reliability of the evaluation of the process being monitored becomes less than permissible.

The purpose of the invention is to increase the reliability of the information collected.

This is achieved in that a memory management unit is inserted into the proposed device, the output of the matching unit is connected to the memory unit, the output of the OR circuit is connected to the memory management unit, and the memory unit and the memory management unit are interconnected with each other. computer machine.

FIG. 1 shows a block diagram of the device; in fig. 2 — memory block and memory control block.

The device contains a pulse shaping unit I, which generates a pulse of sufficiently short duration at the moment the sensor triggers, group coding unit 2, which serves to receive a message code from a single pulse and amplify the power of the transmitted signal, matching unit, OR 4 circuit generating pulses information recording, memory block 5 (information storage consisting of sub-blocks) and memory management block b.

In FIG. 2, the following notation is adopted: 7 — busses of information recording pulse, 8, 9 — awls of a pulse of a memory sub-block, 10 — busses of read pulses, II — pulse-code reading widths, 12 — busses of initial settings pulses, 13 - bus pulse end of reception of information, 14 - bus pulse end of circulation, I5i and 15-2 memory subunits, 16 - local control unit, 17 - address register, operating in counting mode, 18 - number register, 19 - memory cube, 20 - a controlled node containing decoders, drivers and amplifiers for one and a half bits of writing and reading chains of the memory cube, 21 — a controlled node, but in the address chains of the memory cube, 22 n 23 — key control circuits, 24, 25 — triggers for switching memory sub blocks, 26–33 key control circuits; 34-37 - potential outputs of the trigger, 38-pulse-code bus information, 39, 40-bus pulse installation in the register number, 41, 42-bus pulse end of circulation, 43, 44 - bus pulse initial setup register number, 45 , 46 - bus pulse initial setup address register.

The device works as follows.

At the time of the controlled event, the corresponding sensor is triggered, and the pulse shaping unit generates a pulse of sufficiently short duration. The impulse goes to block 2, where it is converted into a parallel message code consisting of an object code (object address) and a message feature code (monitored parameter). The signal amplified by power passes through block 3 and is written to the register of the number of one of the sub blocks of block 5. At the same time, the signal is fed to the input of the OR 4 circuit, which forms a recording pulse, which is sent by block 6 to the appropriate memory sub block and it is used to overwrite the contents of a register of numbers into a memory cube.

By filling the cube with information

from the memory block, a filling pulse of the corresponding subblock is output, which enters block 6. On the basis of this pulse, block 6 automatically shuts off the filled subblock and turns on the free subblock

memory to collect information. At the same time, the memory control unit generates in the computer a pulse filling the memory unit. Having received this impulse, the computer rewrites the contents of the filled sub-block of the memory block into its memory.

Thus, the memory management unit automatically switches one of the free subunits of the memory block to the collection of information, and the computer rewrites the contents

sub-block information filled in its memory.

Consider the operation of blocks 5 and 6. The initial state of the circuit is set by a computer, which sends the corresponding commands on buses 12 and 13. We take the initial state of the circuit in which the output 34 of the flip-flop 24 and the output 37 of the flip-flop 25 permitting the outputs of the key circuits 22, 26, 27, 31, and 33, and from the outputs 35 and 36 of the indicated triggers, the potential of the prohibition is given to the outputs of the key circuits 23, 28, 29, 30 and 32. The message from the sensors, converted by blocks 1, 2, 3 into a parallel pulse code, passes through bus 38, key circuit 22, and is written to register 18. Simultaneously, conversion is converted by OR circuit to information write pulse, which is sent through key circuit 26 in block 16 of subunit 15 and turns into

it impulses to rewrite the contents of register 18 into the cells of memory cube 19.

At the end of the record number of each message, block 16 sends a setting pulse to the “About register 18” through bus 39, and a pulse through bus 41.

the end of the address register 17, operating in counting mode. This pulse is used in it to set the address of the next message by increasing the register contents by one. By filling

The last cell of the cube of memory at the output of register 17 is a pulse of filling the subunit of memory, which enters through the bus 8 into the memory control unit and switches the triggers 24, 25. At the same time, the pulse

through the key 27 is written down the tongue 9 in the computer and serves as a signal that the cube of the subunit 15i is filled.

A pulse through buses 44, 46 is also sent to subunit 152 to set the address and number registers of this subunit to the initial state. Switching triggers 24, 25 leads to a change in the sign of the potential at their outputs 34-37 on the opposite. In this connection, the key circuits 22, 26, 27, 31 and 33 are banned, and the outputs of the key circuits 23, 28, 29, 30 and 32 are allowed. From this point on, information is received and recorded by subunit 152, and the contents of subunit 15i are overwritten by bus 11 via computer 11 via its commands sent to block 16 via bus 10. Before reading the information sheet in subunit 15i, the computer sends the key 32 pulse setup, in which registers 17 and 18 are installed in the "O.

Reading the contents of each cell ends with issuing from the block 16 a pulse of the end of circulation, which is fed to register 17 via bus 41, setting the address of the next cell in it. A simultaneous end-of-pulse impulse through the key circuit 30 and the bus 14 is sent to a computer to organize reading of the contents of the day cell. By filling out the ISa subunit with information, it issues

on bus 8 to block 6, the pulse of filling the subblock and for collecting information are again switched on subunit 15i, etc.

Subunits 15i and 152 can be controlled not only automatically, but also by computer commands sent to the control unit and buses 12 and 13. The pulses coming in through these buses set the triggers 24, 25 to the appropriate position.

Subject invention

Device for interface of computer with two-position impulse sensors according to aut. St. No. 371574, characterized in that, in order to increase the reliability of the collected information, a memory management unit is inserted into the device, the output of the matching unit is connected to the memory unit, the output of the OR circuit is connected to the memory management unit, and memory management interconnected and with the computer.

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