SU1748141A1 - Device for correcting time scale - Google Patents

Abstract

The invention is used in synchronization systems for time scale correction. SUMMARY OF THE INVENTION: The device comprises a generator 1. a phase shifter 2, a frequency divider 3. a code converter in a time interval 4, two shift registers 5, 8, a correction code converter 6, two single pulse drivers, 17 , block of comparison of codes, three triggers 10, 11, 18, two elements OR 12, 13, three elements AND 14, 15, 16 and a decoder 19. 1-2-3-12-10-14-6-8-9- 16-17-12, 19-18-7-4-2-7, 19-11-5-9, 3-1B-7. 2-7. 5-2-4-2, 14-6, 15-6, 3-13-8-11. 19-10, 5-16.1 silt

Description

The invention relates to a pulse technique and can be used in synchronization systems to correct the time scale.

The aim of the invention is to increase the noise immunity.

The drawing shows a structural diagram of a device for correcting the time scale.

The device for correcting the time scale includes a generator 1, a phase shifting unit 2, a divider 3.) a frequency, a code converter 4 in a time interval, a shift register 5, a correction code converter 6, a single 15 pulse generator 7, a shift register 8, block 9 code comparison, triggers 10 and 11, elements OR 12 and 13, elements 14, 15 and 16, driver 17 single pulses, trigger 18, decoder 19 .. 20

The output of the generator 1 is connected to the input of the phase-shifting unit 2, the output of which is connected to the clock input of the converter 4 _{} by the} first input of the driver 7 and the input of the frequency divider 3, the output of which 25 is connected to the R-input of the trigger 18 and to the second inputs of the OR elements 12 and 13, the command input of the device is connected to the input of the decoder 19, the first output of which is connected to the R-input of the trigger 10 and the R-input 30 of the trigger 11, the direct output of which is connected to the output of the register 5, the clock input of which is connected to the first input of the OR element 13 and the clock output converter 6, the information output 35 of which is connected to the corresponding inputs of registers 5 and 8, the output of register 8 is connected to the clock input of trigger 11, the information inputs of the device are connected to the first inputs of elements And 14 40 and 15, the second inputs of which are combined and connected to the input register 8 and the direct output of the trigger 10. S-input which is connected to the output of the element OR 12, the first input of which is connected to the output 45 of the device and the output of the former 17, the input of which is connected to the output of the element And 16, the first input of which is connected inen with the output of the code comparison unit 9 · whose inputs are connected to the corresponding outputs of the registers 5 and 8, the low-order output of the register 5 is connected to the first control input of the phase-shifting unit 2, the second control input of which is connected to the output of the converter 4, the formation inputs of which are connected to the corresponding outputs of the upper bits of the register 5, the output of which is connected to the second input of the element And 16, the outputs of the elements And 14 and 15 are connected to the corresponding inputs of the converter 6, the second output of the decoder 19 with is single with the S input of trigger 18, the direct output of which is connected to the second input of the driver 7, the output of which is connected to the trigger input of the converter 4..

The device operates as follows. * ·

The generator 1 is a source of pulses of a stable frequency, for example, 5 MHz to start the phase-shifting unit 2, which is made in the form of a frequency divider with a variable division ratio. In the initial state, the division coefficient of block 2 is equal to K, which is determined by the presence of a logic 0 signal at its second control input from the output of the converter 4, independently of the signal level at the first control input. The pulses from the output of block 2 are fed to the input of the divider 3. The divider 3 further divides the frequency of the generator 1 to 1/60 Hz and counts the time (minutes and hours). The time scale formed by the divider 3 is a set of pulse signals with frequencies from the frequency of the input signal of the divider 3 to 1/60 Hz and the time code of minutes and hours. '.

From the output of the divider 3, pulses with a frequency of 1/60 Hz are fed to the input R of trigger 18, through the OR element 12 to input R of trigger 10. At the same time, the outputs of triggers 10 and 18 are set and supported by the logic 0 signal. From the output of trigger 10, the logic 0 signal ”Arrives at the input of the register 8, which is set to the initial state by pulses with a frequency of 1/60 Hz, coming from the output of the divider 3 through the OR 13 element to the clock input of the register 8. At the output of the register 8, the signal of Logical 0 is set and maintained. Correction BP scales Meni in the proposed apparatus is as follows.

To write to the device a correction code for the command input of the device, i.e. at the inputs of the decoder 19, the first command is supplied in the form of a specific binary code, for example 0101. In this case, a pulse is generated at the first output of the decoder 19, the duration of which is equal to the duration of the command. This pulse is supplied to input S of trigger 10 and input R of trigger 11.

In this case, the output of trigger 10 appears a logical 1 signal, which allows the passage of signals from the information input of the device through the elements And 14 and 15 to the inputs of the Converter 6. Simultaneously, the appearance of a logical 1 signal at the output of the trigger Yusnima5. 1748141 6 there is a setup signal from the setup input of register 8, allowing writing information to it. At the output of register 8, the signal of logical O is supported. At the 5th output of trigger 11, logical O appears, which is fed to the input of register 5.

It should be noted that the command 10 is sent to the command input of the device immediately after the appearance of a 1/60 Hz pulse at the output of the divider 3 in order to ensure that the correction code is recorded until the next 1/60 Hz pulse appears. In this case, 15 a high frequency of transmission of the correction code (for example, · 100 kHz) ensures the end of the code recording long before the next pulse of 1/60 Hz.

To the information input of the device, 20 i.e. to the first inputs of the elements And 14 and 15, a sequential correction code is supplied. The correction code has the following structure: the least significant digit is the correction symbol, the highest digit is the correction value in the binary 25 code. The correction code is transmitted twice.

The code is transmitted over two communication lines in the form of code units of the zeros iod code. ” In this case, the unit of the correction code corresponds to the presence of a pulse on the communication line of the unit code and the absence of a pulse on the communication line of the zero code ”, and the zero of the correction code corresponds to the absence of a pulse on the communication line of the unit code and the presence of a pulse on the communication line of the zero code”. The code of units and 35. the code of zeros through the elements And 14 and 15, respectively, is supplied to the first and second inputs of the Converter 6.

A direct sequential correction code is generated at the information output of converter 6, and a clock pulse is generated at the clock output. ''.

The correction code from the information output of converter 6 is supplied to the information inputs of registers 5 and 8. 45 Clock pulses from the clock output of converter 6 are transmitted to the clock input of register 5 and through the OR 13 element to the clock input of register 8. There is a logical 0 s at the input of register 5 50 of the trigger output 11, therefore, under the influence of clock pulses, the register 5 is set to its original state. In this case, at the output of register 5, a logic 0 signal is set, which is fed to the second 55 input of the And 16 element.

At the output of the setup of register 8, there is a logical ”1 signal from the output of trigger 10, while the correction code is written to register 8 under the influence of clock pulses. Upon completion of writing to the correction code register 8, a logical G signal appears, which is fed to the trigger input of trigger 11. Logic 1 is fed to input I of trigger 11, and logic 0 is input to input K. At the same time, logic 11 is written to trigger 11 1, which goes to the input of the register setup 5. removing the installation signal and allowing the recording of the code.

The repeated correction code is recorded in register 5, while the code recorded in register 8 is saved, which is ensured by the noted construction and the principle of operation of the use of registers. Upon completion of the recording of the repeated correction code in the register 5, a logical 1 signal appears at its output, which goes to the second input of the And 16 element.

. The correction code from the outputs of the bits of the register 8 and from the outputs of the bits of the register 5 is fed to the block 9 code comparison. When the codes match, the output of block 9 shows a logical-1 signal, which is fed to the first input of the And 16. element. At the output of the And 16 element, a logical 1 signal appears that triggers the shaper 17. At the output of the shaper 17, a single pulse appears through the OR element 12 enters the input R of the trigger 10 and resets it. The logic 0 signal from the output of trigger 10 prohibits the passage of signals through the elements And 14 and 15 to the inputs of the converter 6 and sets the installation signal at the input of the setup 'register 8. At the same time, the pulse from the output of the former 17 goes to the control output of the device, indicating that the code is written correction to the device is completed, the correction code is recorded correctly and you can carry out the correction. ^: '

To directly correct the time scale for the command input of the device, i.e. to the inputs of the decoder 19, a second command is supplied in the form of a specific binary code (for example, 0110), different from the first command (for example, 0101). In this case, an impulse is formed at the second output of the decoder, which is fed to the input S of trigger 18, and trigger 18 is set to a single state. Logic 1 from the output of the trigger 18 starts the driver 7, the first input of which receives pulses from the output of block 2. The driver 7 selects the second pulse from the moment of its start from the pulse train at the first input. This pulse is fed to the start input of converter 4, the output of which is a pulse whose duration is proportional to the binary code of the correction value supplied from the outputs of the upper bits of register 5 to the recording inputs of converter 4,

The pulse from the output of the converter 4 is fed to the second control input of block 2 and changes its division ratio by 5 K + 1 depending on the correction sign coming from the output of the least significant bit of register 5 to the first control input. A change in the division coefficient of block 2 leads to a shift in the time scale formed by divider 3. At the end of the pulse at the output of converter 4, the following is restored: the initial division coefficient K of block 2.

The magnitude of the shift of the time scale is 15

Δΐ- + ΝΤ, where T is the pulse repetition period of the generator) 1;

N is the number corresponding to the binary 20 code of the correction amount in the correction code.

This ends the correction.

The next pulse of frequency 1/60 Hz from the output of the divider 3 sets the trigger 18 to zero and through the OR element 25 13 it goes to the clock input of register 8, at the installation input of which there is a logical 0 from the output of trigger 10. Register 8 is set to the initial state, while at the output of the register 8 and 30 the output of block 9 appears logical "0. The state of the trigger 11 does not change. The code recorded in register 5 is saved, which allows you to later repeat the time scale correction if necessary without re-writing the correction code. .

Claims (1)

Claim A device for correcting a time scale comprising a generator, a phase-shifting unit, a frequency divider, a code converter in a time interval, a shift register, an element And a correction code converter, a single pulse shaper 45, a decoder, wherein the generator output is connected to the input of the phase-shifting unit, the output of which is connected to the input of the frequency divider, the first input of the first driver of a single 50 pulses and the clock input of the code converter in a time interval, the output of which is connected to the second control by the phase-shifting unit, the first control input of which is connected to the output of the lower radar of the first shift register, the outputs of the highest bits of which are connected to the information inputs of the code converter in a time interval, the trigger input of which is connected to the output of the first shaper of a single pulse, the information and clock outputs of the correction code converter connected to the corresponding inputs of the first shift register, distinguishing ^one with one. that, in order to increase the noise immunity, three triggers, two AND elements, two OR elements, a second shift register, a code comparison unit, a second single pulse shaper, the output of which is the output of the device and connected to the first input of the first OR element, are introduced into it. the output of which is connected to the R-input of the first trigger, the direct output of which is connected to the installation input of the second shift register and the second inputs of the second and third elements And, the outputs are co-; which are connected respectively to the inputs of the correction code converter, the information and clock outputs of which are connected respectively to the information input of the second shift register and the first input of the second OR element, the output of which is connected to the clock input of the second shift register, the output of which is connected to the clock input of the second trigger, direct output which is connected to the installation input of the first shift register, the output of which is connected to the second input of the first element And, the first input of which is connected to the output of the unit with equal codes, the inputs of which are connected to the corresponding outputs of the first and second register will shift ha, the command bus of the device is connected to the input of the decoder, the first output of which is connected to the S-input of the third trigger, the R-input of which is connected to the output of the frequency divider and the second inputs of the first and second OR elements, the second output of the decoder is connected to the S-input of the first trigger and the R-input of the second trigger, the output of which is connected to the installation input of the first shift register, the output of the first element And is connected to the input of the second form the world of a single pulse, the first inputs of the second and third, elements And are connected to the information input buses of the device.