SU1742856A1 - Digital information recording and reproducing device - Google Patents

Abstract

The invention relates to the field of instrumentation and can be used in the construction of long-term storage devices on a movable medium, as well as in the transmission and storage of information. The aim of the invention is to simplify the device. SUMMARY OF THE INVENTION: A device for recording and reproducing digital information comprises 1 magnetic driver 1, 2 blocks 2, 7 of code conversion, 1 block 3 of control, shaper 4 of control bit, 1 shaper of 5 error signs, 1 block 6 of zero adders, two, 2 multiplexers 8.9, 1 encoder 10, t adder 11.1 memory block 12, 1 register 13, 1 block 14 AND elements, 1 block 15 elements OR NOT. 1-2-8-4-5-14-15- 12, 1-3-1, 2-9-12-13--6-9, 3-8, 3-9, 3-Yu, 3-12 , 3-13., 3-11. 6 Il. § (L

Description

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31742856

The invention relates to instrumentation and can be used to build long-term storage devices on a movable medium, as well as in the transmission and reception of information.

The aim of the invention is to simplify the device by simplifying the shaper of the characteristics of reproduction errors.

SUMMARY OF THE INVENTION The essence of the invention is to form, when recording check bits, and place each check bit after a group of (v-1) information bits. During reproduction, the check bits are formed in the same way as when recording, and compared with the reproduced check bits. The incomparability of the corresponding check bits indicates the presence of errors in a certain part of the information. The number of the defective information bit is determined by the distance between adjacent non-;

matched control bits. i

Fig about 1 presents a structural

device layout; in fig. 2 is a block diagram of a test bit former for} 5; in fig. 3 - The flow chart of the error signer for 5; in fig. A is the block diagram of the control unit; in fig. 5 cyclogram of the device in the recording mode information in the drive; FIG. 6 is a sequence diagram of the operation of the device in playback mode,

A device for recording and reproducing digital information (Fig. 1) contains a magnetic storage device 1, a first code conversion unit 2, a control block 3, a check digit driver C, an error indication generator 5, an absolute modulator two block 6, a second code conversion block 7 , multiplexers 8 and 9, encoder 10, adder 11, memory block 12, register 13, block 14 of elements AND, block 15 of elements OR NOT.

Unit 2 is designed to convert a serial code into a parallel one and is made in the form of two registers 16 and 1 / o. Block 7 is designed to convert a parallel code into a serial one and can be made as an AND-OR element. The check-driver k for 3–5 (FIG. 2) contains registers 18–25 and modulators 26–32 modulo two.

To fix the packet of K-) bits, the registers i9 21, 23 and 2k must contain K bits, register 18 - K + 3 bits, register 20 - K + 2 bits register 22 - K + 1 bits, register 25 - bits Shaper 5 error signs for) 5 (fig, 3) contains adders

33-40 modulo two, triggers P1-43, register 44, elements AND 45-48. In this case, the register 44 must contain To bits.

The control unit 3 (Fig. 4) contains a pulse generator 49, pulse counters 50 and 51, triggers 52-56, decoders 57, 58, registers 59, 60, elements AND 61-65, elements OR 66-71, elements OR- NOT 7 and 73, inverters

74.75, delay element 76, as well as keys 77 and 78, triggers 79 and 80, elements OR 81-83, element AND. The outputs of the OR-NOT 73 element, the inverter 74, the inverter 75, the AND 61 element, the OR 5 element 70, the LZ trigger, the fourth register output 60, the OR 71 element, the AND 65 element, the OR-NOT 72 element are outputs from first to dec corresponding to block 3 controls.

The device works as follows

At the beginning of each mode, all blocks of the device are reset to 0 (not shown in Fig. 1-3). The first output of the generator 49 produces a non-discontinuous sequence of pulses (Fig. 5a). In the information recording mode, a pulse is formed at the first control output of accumulator 1 (Fig. 56), for example, when

0 specified zone. This pulse sets in 1 the triggers 52 and 53, which enable the operation of the counter 50 and the register 59 and reset to the O counter 51. With a certain code

5, the counter 50 corresponding to the interval from the location of the zone to the beginning of the information, a pulse is formed at the first output of the decoder 57 (FIG. 5c), which is written to the register 59 by the next pulse of the generator 49. At this, the trigger 52 (FIG. 5d) and the counter 50 are reset in O, the operation of the counter 51 is permitted

0

A single signal advances along register 59 and signals are sequentially generated at its zykhods (Fig. 5e, f, f, g, i) with a duration in the period Tp of the output pulses of the gene 51/42856

9. Memory block 12 (537RU6 microcircuit) is in playback mode, because its control input receives a single signal from output j of element 12. Pulse from the first output of register 59 passes through element 70, the elements of the OR NOT block 15 and enters the resolution inputs (Fig. 5m) of the memory elements of block 15. 10 According to these pulses from block 15, information is reproduced which, on the falling edges of similar pulses formed by element 73, is recorded. After recording a given array of information, taking into account the protective gap from the control With the bits following the end of the array, the 5Y decoder is triggered, and its signal sets Triggers 53 and 54 to O. The writing process ends. When recording information, blocks 2,5,6,9,10,11, I and 15 and register 60 do not work.

In the information playback mode, a pulse is generated at the second control output of the accumulator 1 (Fig. 6a), for example, when the register is set to 13 with a parallel code. 15 of this zone. This impulse is set to 1 triggers 52 and 55, which enable the counter 50 and register 60 to work, and the counter 51 is reset to O, With a certain counter code 50 corresponding to the interval from the location of the zone to the beginning of the information during playback, on the second At the output of the decoder 57, a pulse is generated (Fig. 6b), which is recorded in the first register bit 60 by the first reproduced clock pulse (Fig. 6d), the trigger 52 (Fig. 6c) and the counter 50 are reset to 0, the counter 51 is resolved. promote The signals from the second to the fifth outputs of the register 60 are shown in sequence along the register 60 and at its outputs, successively forming signals with a duration in the period Tb of the output clock of the accumulator 1. 6e, f, f, h „

In this mode, the encoder 10 does not work. Therefore, the output address codes of all adders of block 11 correspond to the output code of the counter 51.

The output register code 13 through 20 multiplexer 8 is fed to the inputs of the generator H, where the values of the control bits are formed by summing the current information bits in the adders with intermediate 25 values of the check bit. Intermediate values resulting from the summation in each clock cycle are recorded in registers 18-25. The finally formed control jQ bits are formed at the output of register 25, which arrive at the information input of the element AND-OR 7. The information bits to be recorded go to the other information inputs of the element N-OR 7 from the outputs of the register 13. At element 7 The parallel code is converted into serial by connecting the corresponding information and control bits to the output of element 7 with control signals from the outputs of register 59 (fig.5d, / e, f, g, i). The address counter 51 triggers on the falling edge of the signal from the second output of register 59 (Fig. 5k).

The cyclical operation of the register 59 is provided by recording the signal from the fifth output of the register 59 through the key 77 and the element 67 to the input of the same register.

The trigger 5 is set to V1 and opens the element And 61. The shifted clock pulses of the generator A9 through the element And 61 arrive at the clock

3S

40

1 triggers 52 and 55, which enable the counter 50 and the turnout of the 60, and the counter 51 is reset to 0. With a certain code, the counter 50 corresponding to the interval from the location of the zone to the beginning of the information during the playback, on the second output of the decoder 57 is formed the pulse (Fig. 6b) that is recorded by the first played clock pulse (Fig. 6d) is recorded in the first register bit 60, the trigger 52 (Fig. 6c) and the counter 50 are reset to 0, the counter 5 is enabled. The single signal moves along the register 60 and on his exits last Signals with a duration of T i of the output clock of the accumulator 1 are formed. Signals from the second to the fifth outputs of the register 60 are shown in FIG. 6e, f, f, h „

The information received from accumulator 1 by a serial code is recorded from register 16 and at a predetermined front of the signal from the fifth output of register 60 (Fig. 6h) is written by a parallel code to register 17. The output code of register 17 is transmitted through multiplex 9 to information the inputs of block 12 and is recorded by the output pulse formed by element AND 63 (Fig. 6L) and fed to the resolution inputs of block 12 through the element OR 70 and the elements OR NOT of block 15 at the address corresponding to the counter code 51.

In the information playback mode, multiplexer 8 is opened with a zero Signal from the output of flip-flop 53 for passing the output code of register 17.

/, .. l 55 Information bits from the outputs of the magnetic input of the magnetic accumulator (Fig. 5l). The G-17 is fed to the inputs of a Formation of the output signals of the element 7 arriving at the information input of the accumulator 1, is shown in FIG. 5n.

The rapper k, which forms the check bits, is similar to the recording mode. Formed test bits in

After recording a given array of information, taking into account the protective gap with the control bits following the termination of the array, the 5Y decoder is triggered, and its signal sets the O flip-flops 53 and 54 to O. The writing process ends. When recording information, blocks 2,5,6,9,10,11, I and 15 and register 60 do not work.

In the information playback mode, a pulse is generated at the second control output of the accumulator 1 (Fig. 6a), for example, when a given zone is located. This pulse is set

Triggers 52 and 55, which allow the counter 50 and register 60 to operate, and counter 51 are reset to 0, When a certain counter code 50 corresponds to the interval from the location of the zone to the beginning of the information during playback, a pulse is generated at the second output of the decoder 57 Fig. 6b), which, with the first reproduced clock pulse (Fig. 6d), is recorded in the first register bit 60, flip-flop 52 (Fig. 6c) and the counter 50 are reset to O, the counter 51 is allowed. The single signal moves along the register 60 and his exits n thus formed signals in the period of duration Tb of output clock pulses accumulator 1 "signals from the second through fifth register outputs 60 are shown in FIG. 6e, f, f, h „

The information received from accumulator 1 by a serial code is recorded from register 16 and at a predetermined front of the signal from the fifth output of register 60 (Fig. 6h) is rewritten by a parallel code into register 17. Output-: register code 17 through multiplexer 9 goes to information inputs block 12 and is recorded by the output pulse formed by AND 63 (Fig. 6L) and received at the resolution inputs of block 12 through the OR 70 element and the OR-NOT elements of block 15, at the address corresponding to the counter code 51.

In the information playback mode, multiplexer 8 is opened with a zero Signal from the output of flip-flop 53 for passing the output code of register 17.

Information bits from the outputs of the OE-GISTR 17 are fed to the inputs of the imaging unit k, which forms the check bits in the same way as the recording mode. Formed test bits in

the former 4 and the reproduced check bits from the output of the register 17 are fed to the inputs of the adder 33 of the former 5 signs of errors. If the corresponding check bits do not match, the adder 33 generates a single signal of an error sign. The presence of each error in the allowable error package leads to the formation of two signs of errors, the distance between which in the number of bits (cycles) uniquely determines the location of the defective bit.

The control of the coincidence of signs of errors in the distance between them is carried out by elements. A single signal at the output of each of these elements is a correction signal for the corresponding bit of information. Further, the signs of errors causing the correction signal are blocked using modulo-two adders, the outputs of which are connected to the output of the corresponding element AND driver 5. If there is a single correction signal from the outputs of generator 5 from block 12, the information at the corresponding address is reproduced and written to register 12; in block 6, the reproduced information is corrected. The corrected information, via multiplexer 9, arrives at the information inputs of block 12 and is recorded at the same address. The change of addresses b, the locus VI for reproducing and recording the corrected information is carried out using the encoder 10 and the block 11 of adders.

The signal element 71 (Fig. 6i) encoder 11) generates address shift codes, which are constant for each of the memory elements of the 12 block. The output codes of the encoder 10 are summed up in block 11 with the counter code 51 and arrive at the address inputs of the block 12. On the elements And block 14 is the coincidence of the output pulses of the element 65 (Fig. Lc) with the signs of errors from the driver outputs:. The output pulses of block 14 through the elements OR of NOT block 15 are fed to the resolution inputs of block 12. The inputs of the recording-playback control unit of block 12 receive the output signals of element 72 (Fig. 6m). Reproduced from block 12 information is recorded in register 13 on the falling edge of you 17428568

the signal of element 73 (fig.bn). At the time of recording in block 12 of the information corrected in block 6, the multiplexer, lexor 9 is switched by the signal from the fourth output of register 60 (Fig. 6g). The pulses for generating the resolution signals of the block 12 are formed from the output clock pulses of the accumulator Yu 1 by delaying the element 76. The repetition of control signals during playback is provided by transmitting the signal of the removed output of the register 60 to its first input information 15 through the element 68 and the key 78.

The falling edge of the first pulse from the fifth register output 60 trigger 56

is set to 1. Second and after 20

25

thirty

35

The following pulses from the fifth output of register 60 pass through elements 62 and 69 and on the trailing edge the state of the address counter 51 is changed (Fig. 6p). Upon reaching a predetermined code in the counter 51, the decoder 58 is triggered, the trigger 55 and the register 60 are zeroed. The reproduction of information from accumulator 1 and the recording of the corrected information in block 12 is completed. In the playback mode, block 7 and register 59 do not work, and their outputs have zero signals.

When recording information from memory block 12, a recording start signal is received in the pulp and paper mill and the pulp-and-paper plant, through which the flip-flops 52 and 79 are set to 1. The key 77 connects the input of register 59 to its fourth output.

At a zero signal on the control dp input of multiplexer 8, its outputs are connected to the outputs of register 17. Since there are no signals from the outputs of accumulator 1, the inputs of drivers h and 5 and the corresponding information input of block 7 from the output of generator 4 receive zero signals in four clock cycles of register 59 Similarly to the mode of recording information into the drive from block 12, in each cycle, a code is selected by sequentially changing addresses in counter 51 and written into register 13 on the AND-OR element 7 The conversion of the four-bit parallel register code 13 to serial is performed. Element 84 generates clock pulses. The outputs of elements 7 and 84 and are connected respectively to the information and clock

4S

50

55

set to 1. Second and after

five

0

five

The following pulses from the fifth output of register 60 pass through elements 62 and 69 and on the trailing edge the state of the address counter 51 is changed (Fig. 6p). Upon reaching a predetermined code in the counter 51, the decoder 58 is triggered, the trigger 55 and the register 60 are zeroed. The reproduction of information from accumulator 1 and the recording of the corrected information in block 12 is completed. In the playback mode, block 7 and register 59 do not work, and their outputs have zero signals.

When recording information from memory block 12, a recording start signal is received in the pulp and paper mill and the pulp-and-paper plant, through which the flip-flops 52 and 79 are set to 1. The key 77 connects the input of register 59 to its fourth output.

When the signal on the control input of the multiplexer 8 is zero, its outputs are connected to the outputs of register 17. Since there are no signals from the outputs of accumulator 1, the inputs of drivers h and 5 and the corresponding information input of block 7 from the output of generator 4 receive zero signals in four clock cycles of register 59. Similarly to the mode of recording information into the drive from block 12, in each cycle, a code is selected by sequentially changing addresses in counter 51 and written into register 13 on the AND-OR 7 element the conversion of the four-bit parallel register code 13 to serial is exhausted. Element 84 generates clock pulses. The outputs of elements 7 and 84 and are connected respectively to the information and clock

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0

five

entrances to the pulp and paper mill. When the counter code 51 reaches the address of the end of the information, the decoder 58 produces a pulse, according to which the trigger 79 and the entire device are reset.

When writing information to block 12, a pulse is received from the CEC, according to which the triggers 52 and 80 are set to

single state. Key 7 & connects the output of element 68 to the input of the second bit of register 60, from which the operation is prevented through element 82. The control input of multiplexer 9 receives a signal (Fig. 6g), and the control input of block 12 receives a signal from the output of element 72 ( Fig. 6m).

When the DCC is connected in parallel to drive 1, a serial code is received from the output of the DCC to the information input of the register 16, which is advanced along the register 16 through the output clock of the DCC. The device operates with four cycles of register 60. Similarly to the mode of reproducing information from accumulator 1, the output pulses of element 63 (Fig. 6l) through element 70 and elements of OR-NOT unit 15 are fed to the resolution inputs of unit 12 and are written in parallel code unit 12 output register code 17. Since the zero output signal of the trigger 55 element 65

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 5 20

thirty

ten

 AN 4K + 2 $ -7;

UN4 6K + 3} -12; + O-18.

With} 5, the encoder 10 should generate the following address offset codes in the channels: N, 9K + 9; N- 7K + 7; N 5K + 6; .

The device corrects error packets with a length of bits with a guaranteed gap between defective packets of at least

M K} (2; H) + --i-pi - 1 bits.

When} 5 M 45K + 49 bits. When implementing control block 3, a set of elements 57.58, 61-65,

67-75,77,78 and 8 can be made in the form of a permanent storage device. When the accumulator 1 and DCC work together, their like outputs connected to the inputs of register 16 are combined using OR elements, and the output of element 7 is connected simultaneously to the information input of drive 1 and DI. The presence of clock pulses at the output of element 61 or 8 indicates that information has arrived. in the drive or CVC, respectively.

Thus, the device allows receiving information from the CCP to the memory unit 12, recording information (with one

is closed, then the resolution pulses are reproduced by the temporary formation of control

bits) from memory block 12 to a magnetic storage device, receive information, from a magnetic storage device to memory block 12 with simultaneous correction of the four bits of information on successive bits, transmit information

the records and records of the corrected information (Fig. 6k) are not formed in this mode. As a result, in each cycle, the CIC in block 12 is recorded

from block 12 to the CEC. In this case, block 12 can be used as an additional memory of the CIC without accessing the magnetic storage device. As a result, the functionality of the proposed device is expanded in comparison with the known,

changing the address of the counter 51 o Upon reaching the counter code 51 value of the address of the end of the information, the decoder 58 generates a pulse, by which the trigger 80 and the whole device is reset to its original state.

The maximum code of the address offset of the corrected information in comparison with the current code of the counter 51 in the first channel of block 12 is in general

N

R

() K + & 2Hi ± ll bit.

In the remaining channels, the code for shifting the address of the information being corrected is reduced compared to the first channel by the number of bits.

transfer information

from block 12 to the CEC. In this case, block 12 can be used as an additional memory of the CIC without accessing the magnetic storage device. As a result, the functionality of the proposed device is expanded in comparison with the known,

Simplification of the device is provided by using the same check bit generator both in the recording mode and in the playback mode for correcting the defective bits without changing the correction capabilities compared to the known ones.

Claims (1)

Invention Formula A device for recording and reproducing digital information comprising eleven 17A2856 magnetic drive, information and clock outputs of which are connected respectively to the information and first clock input of the first code conversion unit, an error condition generator, the outputs of which are connected to one group of inputs of the modulo-two block, the control bit generator output connected to one input of the second conversion unit, the output of which is connected to the information input of the magnetic storage device; the clock, first and second control outputs of the magnetic storage device are connected to the first, second and third inputs of the control unit, the first output group of which is connected to the control group The inputs of the second conversion unit, the outputs of the first to the fourth control unit are connected to the control inputs of the corresponding pilot bit, and Signs of the error, the second clock input of the first code conversion unit, and the clock input of the magnetic storage device, which is due to the fact that, in order to simplify the device, the first and second multiplexers, an encoder, an adder, a memory block, a register, a block are entered into it AND elements and the block of OR-NOT elements, the outputs of the first code conversion unit are connected to the first group of inputs of the first and second multiplexers, the group of outputs of the first multiplexer is connected to the information inputs of the pilot bit generator, the output of which oh and one 12 the output of the first multiplexer is connected to the information inputs of the error signer, the outputs of which are connected to the first group of inputs of the block of elements AND, the outputs of the block of elements AND are connected to the first group of inputs of the block of elements OR-NOT, the outputs of which are connected to the first group of control inputs of the memory block, encoder outputs are connected to the first group of inputs of the adder, outputs of the adder are connected to the address inputs of a memory unit whose outputs are connected to the information inputs of the register, outputs of the register are connected to another group of block adders modulo two, whose outputs are connected to the second group of inputs of the second multiplexer, the outputs of the second multiplexer are connected to the information inputs of the memory block, the outputs of the register and the common bus are connected to the second group of inputs of the first multiplexer, the outputs of the register are connected to the second group of inputs the second code conversion unit, the first and the fifth to the tenth outputs of the control unit are connected respectively to the register clock input, a group of information inputs of the block of elements OR - NOT, the control input of the first multiplexer, the control input of the second multiplexer, the input of the encoder, the second group of inputs of the And block and the second group of control inputs of the memory, and the second group of outputs of the control. 2 one MUXt a III I I I II II I III I I I I I I I I I II / r, ... FIG. four toil / "