SU1695319A1 - Matrix computing device - Google Patents

Abstract

The invention relates to computing and can be used in electronic computers as a programmable, specialized real-time peripheral processor with a parallel-sequential implementation of calculations. The aim of the invention is to extend the functionality of the matrix computing device by providing the possibility of processing information in real time. The goal is achieved in that the device containing the input register 2, the matrix of 4 computational cells, the register 5 of the result and the element of comparison 8, is entered into the block 1 of the input buffer memory, the matrix 3 of the storage cells, block 6 of the output buffer memory, block 9 of the memory These programs, control unit 10, synchronization unit 11. 4 il.

Description

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The invention relates to computing and can be used in electronic digital computers as a programmable specialized real-time peripheral processor with parallel-pipelined implementation of calculations.

The aim of the invention is to extend the functionality of the matrix computing device by providing the possibility of processing information in real time.

Figure 1 shows a diagram of a matrix computing device; Fig 2, the memory cell of the matrix; Fig. 3 shows a control unit; figure 4 - block synchronization.

The matrix computing device (Fig. 1) contains a block 1 of the input buffer memory, an input register 2, a matrix of 3 storage cells, a matrix of 4 computing cells, a result register 5, a block b of the output buffer memory, a microcommand register 7, a comparison element 8, a block 9 programs, a control unit 10 and a synchronization unit 11. In addition, the device contains data input 12, data output 13, program-control input 14, address input 15, control output 16, and readiness output 17.

Each memory cell 18 of the matrix 3 (FIG. 2) contains a register of 19 commands, two input switches 20, 21, two output switches 22, 23, a switch 24 of memory matrices, a memory matrix 25, a transit control block 26, delay element 27, information inputs 281-284, information outputs 291-294, program input 30, program output 31, program input control input 32, synchronization input 33. The command register 19 of the memory cell 18 contains a two-bit field 34 of the output address of the memory matrix 25, a two-bit field 35 of the address of the exit of the transit, a two-bit field 36 of the transit entrance address, a two-bit field 37 of the address of the input of the memory matrix 25 and an eight-bit field 38 code delay values.

The control unit 10 (FIG. 3) contains a decoder 39, a register 40, a permanent memory (ROM) 41.

The synchronization unit 11 (figure 4) contains a generator 42 clock pulses, the first 43 and the second 44 elements And the counter 45.

The device works as follows.

The operation of the matrix computing device is controlled from the control unit 10 under the influence of commands received from the computer via inputs 14 and 15. Data is loaded at the rate of their arrival through the input 12 of the device data into unit 1 of the input buffer memory. From the address input 15 of the device connected to the computer address bus, to the input of the decoder 39, there are commands that determine the type of information received from the software control input 14 connected to the computer data bus. The information supplied to the input 14 of the control unit 10 may. There are three types and are entered under the influence of signals appearing at the outputs of the decoder 39, either in block 9 of program memory, or in register 40 of control unit 10, or in counter 45 of synchronization unit 11. In register 40 of control unit 10, the commands , under the influence of which the ROM 41 generates signals at the control outputs of the control unit 10 that establish the specified modes of operation.

The counter 45 of the synchronization unit 11 records the number of synchronization clocks necessary for the execution of the predetermined mode. In block 9 of the program memory, the programs for setting the matrices 3 and 4 are entered. The installation of the matrix 4, 3 in the programming mode (settings) or the processing mode (calculations) is performed according to the signal from the control output of the control unit 10 supplied to the matrix mode selection input.

Before starting the task, the program is entered into the command registers of the matrices 3 and 4 from block 9 of the program memory through the register of 7 microcommands. The program is stored in the process of solving in the registers of the commands of the matrixes 3 and 4. A sequential connection of the registers of the instructions of the cells in each row of the matrices, as well as the serial connection of the last register of the previous lines to the first register of commands of the next row of matrices, allows you to record programs in the sequential code until full load of the program in the cells. The microinstructions register 7 serves as a buffer register that converts commands received from block 9 of program memory in a parallel code into a sequential code for writing to cell instruction registers.

When the program is re-written in the cells of matrices 3 and 4, a comparison of commands written in the registers of memory and computational cells with re-recorded commands occurs at the output of element 8 connected to the control output 16 of the device and a program recording error is generated .

The input data stream enters the parallel code on the input register 2, where it is converted into a serial code and the order is loaded into matrix 3 and further from the outputs of matrix 3 to matrix 4. Matrix 4 is intended for performing calculations, and matrix 3 serves for matching time intervals, arising from the processing of information flows.

Each of the modes ends by stopping the generator 42 under the influence of a signal arriving at its input from the transfer output of counter 45. After receiving this signal, also coming through the corresponding output of the synchronization unit at the ready output 17, the computer, in accordance with its program, initiates the execution of the next mode.

Claims (1)

Invention Formula A matrix computing device containing an input register, a matrix of computational cells, a result register, a microinstruction register, a comparison element, the output of the microinstruction register is connected to the first input of the comparison element, the programming output of the matrix of the computational cells is connected to the second input of the comparison element, the output of which is the control output device, the data output of the matrix of computational cells is connected to the input of the result register, characterized in that, with the aim of expanding the functional, by providing real-time information processing capabilities, an input buffer memory block, a storage cell array, an output buffer memory block, a program memory block, a control block, and a synchronization block are inputted into it input buffer memory, the output of which is connected to the input of the input register, the output of which is connected to the serial data input of the matrix of storage cells, and its parallel outputs and data inputs are connected respectively to the pair -parallel data inputs and outputs of the matrix computing cells result register output is connected with the input of the output buffer memory, the output of which is the data output of the device, the software control input of the device is the first input of the control unit, the outputs of the first through fifth of which are connected respectively to the control inputs of the input buffer memory, cells, matrixes of computational cells, block of output buffer memory, block of memory programs, and the sixth and seventh outputs of the control unit are connected respectively to the first and second permitting inputs of the synchronization unit, the first software output of the control unit is connected to the address input of the program memory block, the output of which is connected to the register input of microinstructions, the output of which is connected to the program input of the memory cell matrix, the program output of which is connected to the program input of the matrix of the computation cells, the second software output of the control unit, the first output which is connected to the synchronization inputs of the input buffer memory block, the output buffer memory block, the program memory block and the first synchronization inputs of the input register and the microinstruction register, the second output of the block synchronization is connected to the synchronization inputs of the matrix of memory cells, the matrix of computational cells, the result register and the second synchronization inputs of the input register and the register of microinstructions, the third output of the synchronization block is the device ready output, the address input of which is the second input of the control unit, the first selection selection of which is connected to the select input of the program memory, and the second selection output is connected to the synchronization input of the same name. J / pr 6oixo Jbf R one i -.-.- iPer & y .BropdV,   Bnfrfbi 6X00 w g. eun pCpui .3 FI / pe K Lro "p 6xod 3 "0, D I   Bnfrfbi g. eun p FI / pe K 4f Tperuu "t / xocJ sync H "