SU1693608A1 - Device for testing computer - Google Patents

Description

The invention relates to digital computing and can be used for operational control of the program execution process in microprocessor systems and the exclusion of unauthorized actions in the control.

The purpose of the invention is the expansion of the functionality of the device by monitoring the reliability of the program address.

Figure 1 presents the functional diagram of the device; figure 2 is a functional block diagram of the processing of interrupt requests; Fig. 3 is a functional diagram of an address generating unit and an address translation unit; figure 4 ~ functional block diagram of the formation of the length of the team,

The device comprises an address translation unit 1, a command length generation unit 2, a first 3 and a second 4 groups of OR elements, the first 5, second 6 and third 7 registers, the first 8 and second 9 comparison blocks, trigger 10, the block 11 for processing interrupt requests, the block 12 address generation, memory unit 13, the first 14, second 15 and third 16 elements OR, the first 17, second 18, third 19 and fourth 20 delay elements.

The device has a reset input, a group of address inputs, a group of m interrupt sync inputs, an interrupt request synchronization input, the addresses of the address strobe ”, address to the stack, and write.

Block And processing interrupt requests contains a node 21 priority interrupt, decoder 22, fourth 23 and fifth 24 registers.

Block 12 formation of the address contains a group of triggers 25.1 ..... 25.K, counter

26. Unit 2 for forming the length of a command contains a programmable matrix 27 and read-only memory 28.

The device operates as follows.

In the initial state, the device is driven by a signal received at the reset input. In this case, the trigger 10 errors are set to the state corresponding to the absence of errors during program execution. In addition, the reset signal, passing to the output of each of the hl elements OR of the first group 3, sets to zero all the bits of the first register 5, designed to receive interrupt request signals received from the group interrupt sync inputs, and containing m triggers with separate installation synchronizing and information inputs. The second 6 and third η-bit registers are also set to zero.

'The principle of operation of the device, namely, monitoring the correct execution of the control computer programs, is based on comparing the address value of the current command with a valid address uniquely determined by the value of the address of the previous command. Determination of admissibility is carried out on the basis of information about the physical addresses of the memory allocated for downloading controlled programs. In determining the validity of program addresses, three situations arise.

1. If the current command is a transition command, then two values are valid for the address of the next command, one of which is generated in the proposed device using the address conversion unit 1, the second register 6 and the second group of 5 OR elements, and the other using the third register 7 and block 2 forming the length of the team. The first value is equal to the transition address specified in the current command, and the second is the sum of the starting address of the current command and the length, expressed in bytes.

The values generated in this way will be used for comparison with the address of the next (behind the current) command, which will go to the address generation unit 12. Wherein; To compare the generated values with the address of the next command, two comparison blocks 8 and 9 are required. If one of them generates an equality signal for the admissible and newly arrived values, then there is no error during the execution of the controlled program, and trigger 10 retains its state corresponding to the absence of an error, otherwise the output of the OR element 16 will be the logical level “0, and with by the arrival of the signal, the address strobe trigger 10 is set to state 0, i.e. the device gives a signal to the output bus, indicating a failure in the course of program execution.

Block 1 address translation, it is advisable to perform on the basis of a programmable logic matrix (PLM) 27 and read-only memory (ROM) 28 (Fig 3), based on the following considerations.

Since, as a rule, in controlled programs, the number of branching (branching) commands and POP (issuing data from the stack) commands is much less than the number

2 ^П , where η is the bit depth of the MP address buses, then the transition addresses specified in the branch (branch) commands should be stored in ROM cells, the 1-bit address of each of which is uniquely generated using the PL M at the known address of the branch (branch) command . At the same time, in the zero cell of the ROM there will be zeros, and this cell will be accessed when the n-bit address arriving at the PLM does not apply to addresses that specify branching (branch) commands and POP commands. Thus, each address that defines the POP or branch (branch) command is associated with a 1-bit ROM address, and the number I is significantly less than the number p. For an example of the implementation of the proposed device for monitoring the functioning of a microprocessor system (MPS) based on the K580 series of MPs get n = 16 and 1 = 5. The need to consider POP type instructions as transition instructions is due to the fact that the stack in the controlled computer is used not only to store the return address to the interrupted program, but also to save the contents w general purpose registers and processor status words. For these purposes, the commands PUSH (write data to the stack) and POP (send data from the stack) are used. As a device stack for monitoring, a memory unit 13 is used, which is a random access memory. When executing a command of the PUSH type, which is accompanied by the issuance of MP signals Record and Appeal to the stack (as the last for MP 588 series, bit D2 of the MP status word can be used, indicating operation with the stack), the contents of the third register 7 are saved, and when the command is executed of the POP type (when the Read signal appears on the external bus of the device), the same value is again overwritten in the third register 7, i.e. on the third register 7, an incorrect value of the address of the next command is formed instead of a value equal to the sum of the value of the address at which the POP command is stored and the value of this command in bytes. In order to generate a valid value for the address of the command following the POP type command, any POP command is considered as a transition command, and therefore, the valid value of the next command address is generated on the second register 6 using the address translation unit 1.

2. If the current command is not a jump command, ie if the linear section of the program to be monitored is executed, then the only quantity allowed for the address of the next command is that it is generated using the third register 7 and the command length generation unit 2 and stored on the third register 7. When the address of the next command comes from the address buses to the address generation unit 12 and is stored in the counter 26 and the triggers 25.1 - 25.4, it can be compared with the permissible value stored in the third register 7, using the second comparison unit 9. After comparison, a new address value of the next command is formed on register 7 as the sum of the value stored in register 7 and the value corresponding to the length of the current command, expressed in bytes. If we consider a microcomputer built on the basis of the K580IK80 microprocessor (MP) as the control computer, then the length of any command cannot exceed three bytes. Therefore, the value of the address of the current command may differ from the value of the address of the next command by the values of the two least significant digits, and, in addition, a difference between the remaining senior digits of one may be possible.

Therefore, the unit 2 of the formation of the length of the command will generate the values of the two least significant bits of the address of the next command, which are recorded in the triggers 25.1 and 25.2 of the block 12 of the formation of the address (for the considered example, K = 2) after analyzing the address of the current command for validity. To form the value corresponding to the higher digits of the next expected address, the single-bit PLM output used in the command length generation block 2 is used, the binary signal from which is supplied with a corresponding delay to the counting input of the counter 26. From the output of the address generation block 12, i.e. from the outputs of flip-flops 25.1 and 25.2 and counter 26, the address generated in the described manner after the corresponding delay time tg is rewritten in the third register 7 and the process of monitoring the admissibility of the command addresses is repeated.

3. If an interrupt request is processed, then the control process is carried out similarly to the cases considered. The transition address is generated in the block 11 for processing interrupt requests. From the output of node 21 of priority interrupts (BPP) (a typical BPP K58914K14 can be used), the signal at the input of the interrupt request synchronization receives information on the decoder 22, on one of the m output iij3608 lines of which there is a csc-dump that resets the bits to 'C' state first register 5, corresponding to this interrupt. and thereby preparing it to receive the next interrupt signal. At the same time, information from the output of the BPP is recorded in an e-bit register, consisting of (1od2t) -rzryadnogo fourth register 23 and (n-1od2gp '| -bit. One fifth register 24, thus forming the address at which the command is stored transition to the next interrupt processing subroutine Synchronization and retrieval ^: tions of δ a from the block 11 of the interrupt processing

VH request for interruption’s return return ·; o the non-receipt of the · · · register 7 from the one used as the stack is necessary, the chronization of interrupt requests appears when the interrupt is confirmed.

Since when will you need a stack for n to an interrupted program? ·. the key is the same as the information on the input of the output block 13 of the memory ιτι of the proposed device and the output of block 12 of the formation of the address of the day for this purpose using the signal Inverse corresponding to the block 13 of the memory and the decision of block 12 which eliminates the simultaneous formation of the formation for synchronization, synchronize, neither do I: address address, submission nn • t at the wall, the input is nervous: it is unnatural;

i, yi about re; ns; Eeyore /.

Second 14 and third 15 elements OR. s also delay lines 17 - 20 are used to coordinate the operation time of individual elements and drains of the device. Signal formation is generated.

Claims (1)

A device for controlling a computer containing an address conversion unit, a first registration unit, a first group of IL22 elements, a first correspondence unit, a trigger, and the group of input icons of the address conversion unit is the address group s; <device inputs for connecting to the address bus controlled by vych and with lutal with; and mashin and si. the group of sync inputs of the first register is the SYNC INPUT device group for connecting to the bus the interruption control is controllable: the first one is the busbar, the first inputs of the OR elements of the first group, the trigger reset input are connected to the device reset input, the output of the elements • OR of the first group are connected to the corresponding bit reset inputs of the first register, the trigger output is the output of the device error, which is important because, in order to expand the functionality by controlling the reliability of the address CA program, it additionally contains a block for processing and interrupt requests, two registers, a second group of elements AND L AND, a second comparison unit, an address generation unit, a memory unit, a command length generation unit, three OR elements, four delay elements 10, and information the inputs of the first register are combined and connected to the potential of a logical unit, the group of outputs of the first register is connected to the group of inputs of the request processing unit 15 interrupts, the outputs of the interrupt code of which are connected to the second inputs of the elements OR of the first group, the outputs of the address conversion unit are connected to the first inputs of the OR elements of the second group, 20 the second inputs of which are connected to the outputs of the interrupt vector of the interrupt request processing unit, whose sync input is! /, the input of the first delay element is connected to the synchronization input of 25 interrupts for the device to be connected to the synchronization line of the interrupt requests of the controlled computer, the output of the first delay element is connected to the first input of the first 30 OR element, the second input of which is the first the second input of the second E-OR is connected to the output of the second delay element, the input of which is the input of the address strobe of the device for connecting to the strobe line 35 of the address of the controlled computer, the outputs of the OR elements of the second group are connected to the information inputs of the second register, the sync input of which is connected to the output of the first element 4G OR, the inputs of the initial installation of the second and third registers are connected to the reset input of the device, the group of outputs of the second register is connected to the first group of inputs of the first block Nia, the second group ^ζ · 5 inputs whose first group of inputs ^Auto: aege comparator unit, the group of the third register inputs are connected to a group of outputs forming unit addresses and group storage unit outputs a group address vho50 up in which and the group forming the address unit data inputs connected with a group of address inputs of the device for connecting to the address bus of a controlled computer, a group of 55 outputs of the third register is connected to the main input of the memory block, the second group of inputs of the second block ep in the group of information inputs of the command length forming unit, the group of outputs of which is connected to the synchronization input corps of the address forming unit, the outputs of the first and second comparison blocks are connected respectively to the first and second inputs of the third OR element, the output of which is connected to the 5 input of the setup in 1 trigger, whose sync input and the resolution input of the command length generation unit are connected to the output of the fourth delay element, the input of which, the input of the second delay element, the block resolution input is converted addresses are connected to the input; the address strobe of the device for connecting to the address; the address strobe of the controlled computing machine; the inverse of the resolution block of the address generation unit and the resolution of the memory block are connected to the input; Access to the device stack for connecting to the line; Address to the stack of the controlled computer; recording input of the memory block is the Record input of the device for connecting to the line. The recording of the controlled computer, the read input of the memory block and the input of the third delay element are connected with input Read device for connecting to a line Reading of a controlled computer,