SU1691846A1 - Computing device of loop local network - Google Patents

Abstract

The invention relates to computing and can be used to build loopback local area networks. The aim of the invention is to increase speed by reducing the access time through the loopback interface. The goal is achieved by the fact that each computing device of a local loopback network contains an operation unit 1, a receiving shift register 2, a transmitting shift register 3, a control unit 4, a conjugation unit 5, a multiplexer 6, information and control lines 7, a buffer unit 8 memory 1 hp f-ly, 3 ill.

Description

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The invention relates to computing and can be used to build local loopback networks.

The purpose of the invention is to increase speed by reducing the access time through the loopback interface.

Fig. 1 is a block diagram of a loopback local computer network; Fig. 2 is a control block diagram; in fig. 3 is a block buffer circuit diagram.

The loop local area network consists of computing devices, each of which contains an operation unit 1, a receiving shift register 2, a transmitting shift register 3, a control unit 4, a conjugation unit 5, a multiplexer 6, information and control lines 7 and a buffer memory unit 8 ti

The control unit consists of a driver 9, a decoder 10, elements AND 11-23, elements OR 24-34, elements AND-OR 35 and 36, counters 37-39, and triggers 40-46

The buffer memory block includes the elements from the first to the sixth elements NOT 47-52, the first element OR 53, the seventh element NOT 54, the element OR-NOT 55, the second element OR 56, the first to fourth triggers 57-60, the first and the second elements are And 61 and 62, the eighth element is NOT 63, the element IS-NOT 64, the first, second and third counters 65-67 and the memory node 68.

Petleva local computer network works as follows

Each computing device of a loopback local computer network has two modes of operation - the mode of the loop controller and the mode of the terminal device.

In the terminal mode, in the transmitting shift register 3 operational unit 1, through a multiplexer 6, a word of a special format is placed — the query word. As soon as the logic of the control unit 4 detects the absence of a transit message at the input of the loopback interface of the computing device, the interface unit 5 opens the loop and the transmitting register 3 is connected by its serial output to the output of the loopback interface. The data received at the input of the loopback looped interface is accumulated in the receive register 2, which in this case serves as a buffer. Immediately after completing the transmission of the interrogation word, the serial output of the transmitting register 3 is disconnected from the output of the loopback interface, and the serial output of the receiving register 2 is connected to the latter. register 2 does not contain loop-sent transit messages, which is detected by control unit 4, and, at its command, interfacing unit 5 closes loopback inputs one and the output, simultaneously disconnecting the serial output of the receiving register 2 from the loopback output.

The query word transmitted in this way to the loop goes through it to the input of the computing device that is in the loop controller mode, and then to its receiving register 2. Further promotion of the query word through the loop stops, since in the loopback interface of the computing device, In the loop controller mode, the interface 5 always opens the loop and connects the serial output of the transmitting register 3 to the loop output.

The query words received in the receive register 2 of the computing device - the loop controller are recognized by the control unit 4 and are received by its signal via the first port of the buffer memory unit 8. At the time of reception of the query word, the input of the multiplexer 6 is locked by the control signal from the control unit 4. Thus, in the buffer storage unit 8, the query words of the exchangeable computing devices in the terminal device mode are accumulated. In accordance with the queue of query words analyzed by the operation unit 1. through the second port of the buffer memory block 8, the information highway 7 receives a message for transmitting it to a ready-to-receive computing device. The message words through the multiplexer 6 are alternately placed in the transmitting shift register 3, and then in sequentially transmitted to the loop.

Pass through the loop, the message reaches the ready-to-receive computing device, which is in the terminal device mode. In it, the words of the incoming message are alternately placed in the receive register 2, and then through multiplexer 6 arrive on the information highway 7. Pass through the loop, the message returns to the transmitting computing device.

After the queue of query words has been exhausted, the computing device, which performs the function of the loop controller, switches to the terminal device mode, and

the controller function is transferred to the next loopback interface, which was previously in terminal mode. A notification of a change in the operation mode as a control word is placed in the transmitting register 3 of the computing device, the loop controller, and then transmitted to the loop. The selected computing device, in the terminal mode, receives a control word about the mode change to the receive register 2 and is recognized by the control unit. The control unit-4 changes the terminal device mode to the loop controller mode, issuing a control action to the interface unit 5, which opens the loop and connects the serial output of the transmitting register 3 to the loop output. After this, the operation of the loopback local area network is repeated.

Claims (2)

Claim 1. A loopback local area network device comprising a gateway unit, an operation unit, a control unit, a buffer memory unit, a multiplexer, a receiving shift register and a transmitting shift register, and the information input of the device (used to access the local network) is connected to the first information input of the interface unit and to the information input of the receiving shift register, the overflow output of which is connected to the first control input of the interface unit, the output of which is Connected to the output of the device (used to access the local network), the first output of the control unit is connected to the control input of the transmitting shift register, the transfer output of which is connected to the second control input of the interface unit, the information outputs of the receiving shift register are connected to the inputs of the control unit mode and to the information inputs of the multiplexer, the outputs of which are connected respectively to the information inputs of the transmitting shift register, the outputs of the first and second groups of the control unit Connected respectively to the control inputs of the interface unit and to the control inputs of the first group of the multiplexer, information inputs / outputs of the operating unit through the information highway are connected respectively to the information inputs and outputs of the control unit and multiplexer, controlling the inputs and outputs of the operating unit through the control highway connected respectively to the control unit mode inputs and outputs to the control inputs of the second multiplexer group, characterized in that, in order to increase the speed of the device by reducing the access time through the loopback interface, it will keep the buffer memory unit connected the control input of the buffer array unit, the outputs of the group of which through the information highway are connected to the information inputs of the operation unit, the control unit and the multiplexer, the control inputs of the group and 5, the output of the buffer memory unit through the control line is connected to the control inputs-outputs of the operation unit, to the inputs to the outputs of the mode of the control unit and to the control inputs of the second 0 multiplexer groups, information outputs of the receiving shift register are connected respectively to the information inputs of the buffer memory block. 2. A device pop 1 that differs5 so that the buffer memory block contains a memory node, first to third counters, first to fourth triggers, first and second AND elements, and NAND element from first to eighth elements are NOT, first and second 0 OR elements and OR-NOT element, the first control input of the group of the block is connected to the input of the first element NOT and to the installation inputs in O of all counters, the output of the first trigger is connected to the information input of the second trigger whose output is connected to the first input of the first element And, the output of which is connected to the synchronization input of the second trigger, the second control input of the group of the key unit 00 keys to the input of the second element NOT, the output of which is connected to the input of the third element NOT and to the read input of the memory node, the third control input The d group of the block is connected to the input of the third element NOT and 5 to the second input of the first element I, the output of the first element is NOT connected to the first input of the second element I, to the input of the installation in O of the third trigger and to the first input of the first element OR, whose output is 0 keys to the input of the installation to O of the fourth trigger whose output is connected to the output of the block, the output of the third element is NOT connected to the input of the fifth element NOT, the output of which is connected to the input of the sixth element NOT, the output of the third trigger is connected to the information input of the third trigger, to the input of the seventh element and to the first input the element OR NOT, the output of which is connected to the counting summing inputs of the first and second counters and to the second input of the second element AND, the output of which is connected to the installation input in O of the second trigger, the output of the seventh element is NOT connected to the input of the eighth element NOT and to the input of the node entry the memory, the outputs of which are connected respectively to the outputs of the block group, the output of the eighth element is NOT connected to the second input of the element AND LINE, the output of the fourth element is NOT connected to the synchronization inputs of the first and fourth triggers, the output is six a NOT element connected to the second input of the first OR gate, to the counting input of the third summing counter and the counting input of the second subtractor schet0 The sensor, whose information outputs are connected to the inputs of the NAND element and to the inputs of the second element OR, the output of which is connected to the information input of the fourth trigger, the output of the NI element is connected to the information input of the first trigger, the information inputs of the first and third counters are connected respectively to the address inputs the write inputs and to the address inputs of the memory node, whose information inputs are connected respectively to the information inputs of the block, the control input of which is connected to the synchronization input of the second th flip-flop. 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