SU1672587A1 - Device designed to correct distortions in tv image signals - Google Patents

Abstract

The invention relates to television. The purpose of the invention is to improve the accuracy of the correction of the distortion of the television signal. The device contains delay lines 1 and 4, adder 2, switch 3, multipliers 5, elements 6 and 10 and 11, shift register 7, storage unit 8 and counter 9. The goal is achieved by expanding the range of amenable distortion correction. 1 il.

Description

The invention relates to television and can be used to improve the quality of television images.

The purpose of the invention is to increase the accuracy of distortion correction of the television 5 signal.

The drawing shows a diagram of the device.

The distortion correction device of the television image signal contains 10 delay line 1, adder 2, switch 3, N additional delay lines 4ι ~ 4p, N multipliers 5ι-5p, N elements And 6ι ~ 6η, shift register 7, memory unit 8, counter 9, the first 10 15 and second 11 additional elements I.

A device for distortion correction of a television image signal operates as follows.

When the corresponding potential is supplied, the shift register 7 is set to a single state.

Delay line 1 and N additional delay lines 4i-4 _{n are} made on analog shift registers (CCD), i.e. by the technology of charge-coupled devices. Moreover, the duration of each delay (equal to KT, where K is the number of cells; T is the clock frequency) should correspond to the duration of the information part of the line of the television signal, i.e. from the slice of the horizontal blanking pulse to the front of the next horizontal blanking pulse (SGI).

The outputs of the shift register 7 are set to 35 in a single state, allowing the passage of clock pulses through the N elements AND 6) -6n into the delay line 1 and the additional 4ι ~ 4 _P delay lines. With clock pulses, the signals from the input of the device advance to the output.

End of pulse generated on output lines 1, _n 4yu4 delay indicates the beginning of the emergence of the information of a television line. With a slice of 45 pulses of the GIS, the counter 9 and the shift register 7 are reset to the zero state, N elements And 6 are closed, and the clock lines 1., 4ι-4η of the delays are stopped. They go into storage state. At the same time, switch 3 closes, eliminating the premature influence of the potential of the extreme cells of the 1.41-4 _P delay lines through adder 2 on the output signal.

Clock pulses through an open element And 10 go to the counter 9, which starts enumerating addresses in the storage unit 8. After a time corresponding to the shift of the first echo signal relative to the beginning of the information part of the line, the corresponding address from the counter 9 causes the output of the storage unit 8 the emergence of a single potential level, allowing the timing of the shift register 7 through the second additional element And 11 clock pulses. The unit is entered into the first bit of the shift register 7 and the corresponding potential opens the corresponding element And 6r 6p and switch 3. The signal from the delay line 1 is fed to the multiplier 5ι ~ 5η, which forms a signal level proportional to the first superimposed echo signal. At adder 2, the signal delayed from the delay line is added to the signal from the additional line 4ι ~ 4 _η and subtracts the echo signal from it, thereby eliminating image distortion.

The next echo is eliminated by adding to the next, respectively shifted, signal from the next additional delay line 4ι-4 _η .

After a predetermined number of clock cycles, determined by the duration of the SGI (12 μs), the pulse from the second output of the counter 9 closes the first additional element And 10, thereby eliminating the repeated search of addresses by the counter 9.

In storage mode, t, e. during the absence of clock pulses, the input information is not entered into the additional delay lines, however, this loss of information occurs during the transmission of the non-information (service) part of the line and does not affect the image signal quality. In connection with the continuous arrival of clock signals in the delay line to the output of the adder 2 are all the signals of the line.

The second additional element And 11 using clock pulses ensures the presence of pulses on the first clock input of the shift register 7 also in the presence of units in the storage unit 8, in two adjacent addresses.

Thus, the proposed device in comparison with the known allows you to expand the range of correctable distortion and thereby improve the quality of the television image. The structure of the device allows you to set the multiplier coefficients manually using potentiometers, and the delay by step-by-step sorting of addresses in the recording mode of the storage unit 8. Without changing the structure, the tuning process can be automated, for which multipliers must be performed using digital-to-analog converters.

Claims (1)

Claim A device for distortion correction of a television image signal containing a delay line in series, the first input of which is an input for a video signal, an adder, a switch, the outputs of which are connected to the corresponding additional inputs of the adder, characterized in that, in order to improve the accuracy of distortion correction of a television signal, N additional delay lines, the first inputs of each of which are an input for a video signal, N multipliers, N elements AND, shift register, storage unit , counter, first and second additional elements AND, while the first inputs of N elements AND, the first and second additional elements AND are inputs for clock pulses, the output of the first additional element And is connected to the input of the counter, the outputs of which are connected to the address inputs of the storage unit, the output which through the second input of the second additional element And is connected to the first input of the shift register, the second inverting inputs of the counter and the shift register are inputs for the horizontal blanking pulse, the second output with the sensor is connected to the second input of the second element And, the third input of the shift register is an input of a logical unit, the outputs of the shift register are connected to the second inputs of the corresponding elements And, to the corresponding control inputs of the switch, while the output of each of the N elements And is connected to the control input of the corresponding additional line delays, the output of each of which is connected to the input of the corresponding multiplier, the output of each of which is connected to the corresponding signal inputs of the switch.