SU1667088A1 - Device for user interfacing to a communication channel - Google Patents

Abstract

The invention relates to computing technology, in particular to devices for interfacing a subscriber with a communication channel. The purpose of the invention is to improve the noise immunity of the device by overwriting information into the buffer memory and bringing the device out of the fault state to the exchange ready state. For this purpose, a known device containing a receiving node, a transmission node, a shift register, two counters, four flip-flops, a pulse generator, the first and second groups of AND elements, a single vibrator, two modulo-two adders, a comparison element, a buffer register and a third counter are entered. The transmission node converts the information coming from the computer into phase-modulated bipolar pulses and transmits them to the communication line. The receiving node serves to receive and convert signals from a communication channel. The first counter and the first trigger form a timer, designed to track the time intervals of the exchange, and the second, third, fourth triggers and the comparison item, the device status register. The second counter tracks the accumulation cycle of information in the shift register, and the entered counter and buffer register protect the received information from the effects of impulse noise at the input and prepare the device to continue the exchange. 4 il.

Description

The invention relates to computing and can be used in systems for the exchange between a computer and a remote external device, such as a display.

The purpose of the invention is to increase the reliability and noise immunity of the device by ensuring that information is overwritten in the buffer memory and the device is brought out of a state of failure to the ready state for exchange.

Figure 1 presents the block diagram of the proposed device; FIG. 2 is a diagram of a driver of phase modulated signals of a transmission node; FIG. FIG. 3 is a diagram of the decoder of the receiving node, the shift register and the buffer register; figure 4 - timing charts of the device

The device (figure 1) contains a shift register 1. the second 2 and the first 3 counters, the first group of 4 elements And, the third 5, the first 6, the second 7 and the fourth 8 triggers, receiving node 9, transmission node 10, pulse generator 11, information input 12, information input / output 13, first 14 and second 15 modulo-two adders, reference element 16, third counter 17. single vibrator 18, second group 19 of elements I, device information output bus 20, strobe information record 21

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nation, the first synchronization input 22, the installation input 23. the second synchronization input 24 reception and the buffer register 25.

Shift register 1 is designed to convert serial code into parallel and vice versa.

The counter 2 pulses of the shift monitors the end of the reception or transmission of the information parcel of n pulses and generates a signal overwriting the information of the shift register 1 in the buffer register 25.

Counter 3 and trigger 6 form a timer designed to track the exchange intervals.

Groups 4 and 19 of the And elements are multi-bit buffer amplifiers for interfacing with the main line of a computer.

The triggers 5, 7, and 8 and the compare item 16 constitute a device status register.

Receiving node 9 contains a us, r i-tel receiver 26 and a decoder 27 and is designed to receive and convert input signals from a communication channel.

Transmit unit 10 comprises amplifier-transmitter 28 and phase-modulated driver 29.

Adders 14 and 15 modulo two are designed to generate test bits during transmission and reception of information.

Comparison element 16 serves to compare check bits when receiving information from a communication line.

Counter 17 provides periodic setting of counter 2 to the initial state after receiving or transmitting information, as well as during the absence of signals in the line.

Buffer register 25 is designed to receive, store and output information in a computer.

The one-shot 18 clears the flip-flops 5 and 8.

Phaser 29 phase-modulated signals (figure 2) contains the shift register 30, the element AND NOT 31 and the switch 32.

The decoder 27 (fig.Z) contains the elements AND-NOT 33-36, triggers 37 and 38 and the element OR 39,

Information is exchanged between the computer and the external device via a two-wire line, such as a coaxial cable. The signals exchanged by the computer and the external device are informational links from phase-modulated two-pulse pulses (Figure 4a).

The device works as follows.

At the command of the computer, a general reset signal is generated on the bus 23. At the same time, the device sets the trigger 7 Ready for transmission and starts the one-shot 18 which resets the trigger 5 Ready receiver and the trigger 8 Timer failure. A reset signal is also provided to the node.

0 9 line reception. If there is no exchange between the computer and the external device, the receiving node 9 does not generate information synchronization pulses and the counter 17 is in the counting mode; 5 clock pulses from the generator 11. The transfer pulses from the output of the counter 17 (FIG. 4z) enter the parallel recording input of the counter 2, providing his initial

0 installation. At the same time, the recalculation factor of the pulses of the counter 2 determines the duration of one information parcel. The computer then generates a reception synchronization signal, which enters the device via bus 22. This signal opens AND 19 elements and reads the status of the flip-flops 5, 7 and 8 and the comparison element 16, forming the device status register, into the computer. After analyzing the device state register, if trigger 7 is set to be transmitted, information is written in parallel to shift register 1 via bus 12 by pulse 21 bus. Trigger 7 is reset, allowing

5 work shaper 29.

The shift register 30 and the NAND circuit 31 included in the imaging unit 29 (Fig. 2) form four series of pulses shifted one relative to the other for the period of the oscillator frequency. The first and second series are used to form a signal. Switch 32 connects to the amplifier-transmitter 28 in pairs the first and second or second and first outputs of the shift register 30, if 1 or O is received at the control input of the switch. From the output of the pulse transformer of the amplifier - transmitter 28, bipolar pulses are transmitted to the communication line. Thus,

0 serial code. coming from the output of the shift register 1, controls the switch 32 of the imaging device 29. The bipolar signal also arrives at the input of the node 9, which receives a linear signal.

5 Receiver amplifier 26 of receiving node 9

amplifies the input signal and generates two sequences of impulses. corresponding to the positive and negative half-periods of the input signal (Fig.46, c) These two signal sequences are fed to the input of the decoder 27 (Fig.Z).

At the initial moment, the triggers 37 and 38 (FIG. 3) are reset to zero by a reset signal, therefore, the AND-HE elements 33 and 34 are open.

The pulse corresponding to the positive half-period of the input signal is fed to the input of the decoder 27 and sets the trigger 37. At the same time, the AND-HE element 34 is closed and the AND-HE element 35 is opened. The pulse corresponding to the negative half-period is through the AND-HE element 35 and the element OR 39 enters the sync output node 9 reception. The leading edge of the same pulse resets the trigger 37. Information is recorded in the shift register 1 on the leading edge of the shift pulse from the single output of the trigger 37 (FIG. 3), which is the information output of node 9. Simultaneously, the shift pulses (fig.4g) from the output of node 9 reception is received at the counting input of the counter 2 and the recording entry of the counter 17. At the same time, the counter 17 is blocked by shift pulses at the time of receiving the information package.

With the arrival of the nth shift pulse, the transmission cycle of one information parcel ends, and at the output of counter 2 a transfer signal is formed, according to which the data from shift register 1 is copied to buffer register 25 (fig.4d, e).

When transmitting information, trigger 5 is not set by the transfer signal of counter 2, since its information input is set low from trigger output 7.

Thus, the information transmitted to the communication channel is moved in the device along the ring formed by transmission node 10, reception node 9 and shift register 1, and recorded in the buffer register 25. This can be used to diagnose the operation of the device.

Reception of information from the communication channel is carried out similarly.

In this case, the information input of the trigger 5 is set to 1, and when the transfer signal is received from the counter 2, the Ready receiver indicator is set. In order to increase the reliability of the received information, a check bit is formed by the adder 14 at the transition. After receiving the package, a check bit is formed by the adder 15 and the compared and compared element 16 compares the formed and received check bit. The result of the comparison is entered in the status register. By analyzing the status register, you can determine the presence of a failure.

According to the requirements of the interfaces, it is necessary to determine not only failures, but also to withstand specified time intervals.

when performing exchange operations. For these purposes, a timer built on counter 3 and trigger 6 is used. When recording, for example, the instructions in shift register 1 for transmission to an external device at the information input of trigger 6 are set to 1. The trigger 6 is set by the clock and enables counter 3 to work. the same clock pulse records the number. Synchronized counter 3 receives subtractive pulses. Transferring counter 3 sets trigger 8. But if a parcel was received from the external device earlier, then when trigger 5 is installed, trigger 6 is reset and

disables the operation of the counter 3. When reading the state register, the single-oscillator 18 is started and resets triggers 5 and 8.

After receiving the next information parcel, the data is automatically transferred from the shift register 1 to the buffer register 25 for storage and subsequent issuance in a computer. The impulse noise in the channel, which triggers the decoder 27 and generates false shift pulses, distorts the information in shift register 1 and causes counter 2 to fail. The data in buffer register 25 is not distorted, and counter 2 is removed from

Failure to readiness to receive information pulses from the output of the counter 17.

In addition, the use of the buffer register 25 makes it possible to combine, in time, the storage operations of the previous one and the receipt of subsequent informational packets. At the same time, the requirement for speed of a computer decreases, productivity and reliability of operation are increased when exchanging with several external

devices. This is due to the fact that without the use of the buffer register, the transfer of information from the shift register 1 to the computer must be performed in the time interval between two information packets, otherwise the information will be corrupted. The use of buffer register 25 significantly increases the storage time of information in the device. For example, for a clock frequency of 1 MHz, the accumulation time of an information packet of 11 pulses is 11 µs. When working with external devices on the interface of the exchange of display media with a computer, for which the minimum interval between

information packets is 2 microseconds, the storage time of information in buffer register 25 is 13 microseconds.

Claims (1)

Invention Formula A device for interfacing a subscriber with a communication channel, comprising a receiving node, a transmission node, a shift register, two counters, four flip-flops, a pulse generator, the first and second groups of And elements, a single vibrator, two modulo-two adders, a comparison element, and an information input the receiving node and the information output of the transmission node form the input-output device for connecting to the communication channel, the first information input of the shift register, the group of inputs of the first modulo-two adder, the information inputs of the first counter and the first trigger form a device input group to connect to the subscriber information output group, the installation input of the receiving node is connected to the second trigger input and the one-shot start input and is the device input for connecting to the subscriber's installation output, the shift register recording input is connected to the first write input of the first counter the sync input of the first trigger and the reset input of the second trigger and is the input of the device for connection to the gate output of the subscriber, the second information input the shift register is connected to the information output of the receiving node, the sync output of which is connected to the counting input of the second counter and the synchronous input of the shift register, the information output of which is connected to the information input of the transmission node, the synchronous input of which is connected to the output of the pulse generator and the counting input of the first counter, the setting input of which is connected to the output of the first trigger, the reset input of which is connected to the output of the third trigger, whose information input is connected to the setup input of the node problem and the output of the second trigger, the sync input of which is connected to the sync input of the third trigger and the output of the second counter, allowing the one-shot input is connected to the first inputs of the elements AND of the second group and is the input of the device for connection to the first reception synchronization output the subscriber's outputs, the elements of the first and second groups form a group of device outputs for connecting the subscriber's information inputs to the group, the first inputs of the elements of the first group are the device inputs for connecting to the second output synchronization output of the subscriber, the second inputs of the elements of the second group are connected to the outputs of the second , third and fourth triggers and a reference element, the output of the first counter is connected to the setup input of the fourth trigger, the reset input of which is connected to the reset input of the third trigger and the output of the one-shot, the output of the first modulo two connected to the first information input of the shift register; the output of the second modulo-two adder is connected to the first input of the comparison element, characterized in that, in order to increase device noise immunity by providing information rewriting to the buffer memory and bringing the device from the failed state to the exchange ready state, the buffer register and the third one are entered the counter, the counting input of the third counter is connected to the output of the pulse generator, and the recording input is connected to the synchronous output of the receiving node, the output of the third counter is connected to the recording input of the second counter, the output of which is connected to the input of the buffer register, the group of information inputs of which is connected to the group of information outputs of the shift register, the group of information outputs of the buffer register is connected to the second inputs of the AND elements of the first group and the group of inputs of the second modulo-two, the second input of the reference element. FIG. one FIG. I To line signal receivers FIG. five