SU1667087A1 - Device for controlling exchange between a processor and a memory - Google Patents

Abstract

The invention relates to digital computing and can be used in computing systems. The purpose of the invention is to expand the functionality of the device by automatically setting the device to the format of the information package. The goal is achieved by introducing a tuning unit into a device containing two pulse distributors, two address generation units, a call synchronization unit, and a conversion mode decryption unit. The tuner contains three registers, three comparison circuits, a counter, two AND elements, an OR element, and first and second pulse shaping nodes. 9 il.

Description

The invention relates to digital computing, in particular to devices for interfacing with memory.

The aim of the invention is to expand the functionality of the device by automatically setting the device to the format of the information package.

Figure 1 presents the block diagram of the proposed device; Figures 2 to 9 illustrate functional diagrams of a call synchronization unit, the first and second memory blocks, the decode mode of the access mode, the tuner, the address generation units, the first and second pulse generation units.

The device contains (Fig. 1) address forming blocks 1 and 2, a call synchronization block 3, a block of the decoding mode of the hits mode 4, blocks 5 and 6 of the memory, and a block 7 of setting.

Block 3 synchronization of addresses contains (figure 2) nodes 8 and 9 elements And elements And 10-13, the pulse generator 14, the trigger 15. elements 16-18 delay and distributor 19 pulses.

Blocks 5 and 6 of memory contain (FIG. 3 and 4) groups of elements AND 20-31, groups of elements OR 32-35, and elements 36 and 37 of memory.

Block 4 decryption mode calls contains (figure 5) elements AND 38 and 39, element OR 40, elements AND 41-44, elements OR 45 and 46, inputs 47 and 48 start and reset and flip-flops 49-51.

The tuning unit 7 comprises (Fig. 6) the registers 53-55 connected to the data buses 52-55, the comparison circuits 56-58, the counter 59. the elements 60 and 61 of forming (extracting) the first and second pulses, the elements 62 and 63 and the element OR 64 .

Blocks 1 and 2 of the formation of the address contain (Fig.7) elements OR 65-68, elements And 69 and 70 and counters 71 and 72.

FIG. 1-7 also show the lines 73-90 of the connections of the device and the first and second distributors 91 and 92 of the pulses.

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Nodes 60 and 61 of the formation of the first and second pulses contain (Fig.8 and 9) triggers 93-95 and elements 96-98.

The device works as follows.

In the initial state, counters 71 and 72 are reset, and triggers 49 and 50 are set to zero. The trigger 15 can be installed in any position, for example in a single.

The start signal on line 47 sets the trigger 51 to a single position, and an element 43 is opened, the signal from the output of which passes through the element OR 46 to line 82, a ZAN signal indicating the start of the exchange. This also starts the generator 14, which generates CX3 pulses of master synchronization for the processor.

The response of the processor to the CPS pulses is the production of CXI 1 source pulses; which arrive at elements 60 and 61

The first pulse of SHI 1 in the data bus 52 generates an information package format code, which is set programmatically and is written to registers 53 and 54 on the selected first pulse of the SHI 1. On the second pulse of SHI 1, the packet duration code appears on the second bus 52 pulse SHI 1 is written to register 55.

After the second pulse of SHI 1, the element 61 transmits the subsequent pulses of SHI 1 in the form of pulses of SHI 2, which are sent to the elements And 10 and 11 as pulses of the recording frequency. Data bus 52, bitwise, is connected to inputs D 1 of memory elements 36 and 37.

Thus, the information to be recorded in memory blocks 5 and 6 is bound to the SHI pulses, and the recording is performed in parallel across all inputs, for example, memory block elements 36 and 37, since the single position of the trigger 15 corresponds to the recording mode in elements 36 and 37 of blocks 5 and 6, switched alternately by distributor 91 through the corresponding AND elements of nodes 20 and 21,23 and 24, as well as the read mode for elements 36 and 37 switched by distributor 92 through the corresponding And 28 and 31 elements of the memory block. At the same time, information is read from elements 36 and 37 of memory block 6 by bits at the expense of distributor 19 and elements of node 9, with which they are accessed through elements 28 and 31 and elements 35 and 33. Thus, readout information from blocks

5 and 6 of the memory are selected sequentially and bit by bit from previously written bytes.

The address change in memory blocks 5 and 6 in read mode occurs with the help of the corresponding counter 71 or 72 through the element OR 67 or 68 on a pulse in the last bit of the distributor 19, which is reflected in the line 88 of the counter 71 or in the line 74 for the counter 2 .

0In the recording mode, for example, the elements 36 and 37 of the memory block 5, the frequency pulses of the SHI 2 arrive at the delay element 16 and through the open element 10 to the element 17 and further on the open elements 20

5 this, the entry of the RECORD / READ of the memory block 5 impulse SHI 2 arrives earlier than the sample input, since the response time of the delay element 17 is less than the switching time of element 16. The end of the pulse SHI 2 at the specified memory inputs occurs simultaneously , since at the end of SHS 2 impulses, element 16 closes AND 12 and the delay time of delay element 17 is equal to the sum of the response times of AND 12 and AND 21 (if the response times of AND 20 and OR 14 are equal). The change of address on the elements 36 and 37 in the recording mode is performed using the corresponding counter 71 or 72 through the corresponding element OR 67 or 68 at the end of SHI 2 on line 87 or 74.

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The format code of the parcel is stored in registers 53 and 54, i.e. information is stored in the memory block until the counter code 71 or 72 is equal to the code stored 0 in the register 53 or 54. The moment of equality of the codes is fixed by the circuit 56 and 57 of the comparison. In the recording mode, the counter 71 or 72 is reset, the OR key is 65 or 66 every time after the codes on the

5 inputs of the comparison circuit 56 or 57 by signals on line 83 or 84. The signal from the output of circuit 56 or 57 affects the corresponding distributor 91 or 92, with the help of which,

0 switching of the next memory blocks. Counter 59 counts the number of individual packages received in the memory blocks to determine the duration of the package, the code of which is stored in register 55. When

5, the sending time will be equal to the previously set, the circuit 58 comparing the codes of the counter 59 and the register 55 outputs a signal KP indicating the end of the sending. The signal KP sets the registers 53, 54 and 55 to its original position. The process of recording information is faster process

read, therefore, it makes sense to release the common processor bus before the end of the read mode. The common bus is released by removing the ZAN signal when tilting, for example, flip-flop 49, which occurs when the valve 91 selects the last row of memory blocks (the signal in the last bit of the valve 91) and the format codes of the parcel 53 register and counter 71 (signal at the output of comparison circuit 56).

The ZAN signal is restored when the memory unit is released during the process of reading information from it (the signal on line 80 at the output of the OR element 45).

The device is stopped by tilting the trigger 51, for example, the reset signal.

Claims (1)

Invention Formula A device for controlling the exchange of a memory processor, comprising two address generation units, the output groups of which are respective groups and the outputs for connecting to the address input groups of the first and second memory blocks, the access synchronization unit, the first output and the synchronization input are corresponding the output and input for connecting to the processor clock buses, and the second, third, fourth and fifth outputs and the first and second groups of outputs are the corresponding outputs for connecting nor to the write-read, sample, and sample input groups of the first and second memory blocks, the decryption mode decoding unit, the first output of which is the output of the device for connecting to the processor bus, and the start and reset inputs are respectively the reset inputs and starting the device, and two pulse distributors, the output groups of which are the corresponding output groups for connecting to the gate groups of the first and second memory blocks and connected respectively to the first and second bits The deciding inputs of the decryption mode of the access mode, the first and second clock inputs of which are connected respectively to the fifth and sixth outputs of the contact synchronization block and the first clock inputs of the first and second address generation blocks, the second clock and enabling inputs of which are connected respectively to the fourth and fifth outputs and the first and second groups of exits the synchronization block of the calls, the clock input of which is connected to the first installation inputs of the first and second address generation units and the second output the decryption mode of the call mode, which is due to the fact that, in order to expand the functionality of the device by automatically setting the device to the format of the information package, it is 0 a setting unit, the first group of information inputs, the synchronizing input and the first output of the setting unit are the corresponding inputs and output of the device for connecting to the information and synchronization buses of the processor, and the second and third groups of information inputs are connected respectively to the output groups of the first and second blocks forming the address, the second installation inputs of which are connected to the second and third outputs of the tuner and the clock inputs of the first and second pulse distributors, setting inputs connected respectively to the installation input of the access synchronization unit and the third output of the conversion mode decryption unit, the first and second information inputs and the fourth output of which are connected to the second and third outputs of the setting unit, the installation input of the setting unit and the enable input of the request synchronization unit, the fifth and sixth outputs are connected with the first and second clock inputs of the tuner, and the tuner contains three registers, groups of information inputs which are connected to the first group of information inputs 0 tuners, three comparison circuits, two AND elements, the first inputs of which are connected to the first and second clock inputs of the device, respectively, and the outputs are corresponding to the first and second inputs 5 of the OR element connected by the outputs to the counter input of the counter, the formation units of the first and second pulses, the output groups of the first and third registers are connected respectively to the first groups of inputs of the first to third comparison circuits, the second groups of inputs of which are connected respectively to the second and third groups of information inputs and 5, a group of outputs of the counter, a reset input connected to the output of the third comparison circuit and the reset inputs of the registers; the reset inputs of the first and second registers are connected to the outputs of the first pulse shaping unit, the synchronous input and the setting the input of which is respectively the synchronization and installation inputs of the tuning unit and connected to the synchronous input and the installation inputs of the second pulse shaping unit, the first and second outputs of which are connected respectively to the first output of the tuning unit and the third register synchronous input, the outputs of the first and second comparison circuits are connected respectively to the second inputs of the first and second And elements and to the second and third outputs of the tuner. 1 A 77 FIG. 2 Shi991 if -four Z.80Z.99L ДЗ 80 L, in. 5 fas. eight