SU1661773A1 - Device for controlling power supply - Google Patents

Abstract

The invention relates to computing and can be used in redundant computing systems (complexes) to control a power supply system. The aim of the invention is to increase the resolution of the power control of the device. The device contains N secondary power supply sources 1, N level sensors, each of which consists of threshold elements 2 and 3 of overvoltage and undervoltage of the element OR 4, integrator 5, two pulse formers 6 and 7, two triggers 8 and 13, two elements And, 9 and 10 element OR 11, multiplexer 12, counter 14, element NOT 15, generator 16 pulses, 1 Il.

Description

The invention relates to computing technology and can be used in redundant computing systems (complexes) for controlling power supply systems.

The aim of the invention is to increase the resolution of the power control.

The drawing shows the block diagram of the device.

The device contains secondary power sources 1, level sensors, Including threshold elements 2 and 3, overvoltage and undervoltage, and Element OR 4, integrator 5, pulse shaper 6 and 7, first trigger 8, elements AND 9 and 10, element OR 11 , multiplexer 12, second trigger 13, counter 14, NOT 15 element, pulse generator 16, device primary network bus 17, control enable bus 18, power failure (interruption) bus 19, Power source faulty code bus 20 interrupts). Upon powering on the device, the triggers 8 and 13 are reset to the initial state (the installation circuit in the block diagram is not shown).

The device works as follows.

When voltage is applied to buses 17 at the outputs of secondary sources 1, supply voltages appear, which respectively arrive at the combined inputs of threshold elements 2 and 3, reacting respectively to increasing and decreasing the input voltage by issuing signals from the logic 1 .

After a time sufficient to complete the transients and determined by the parameters of the integrator 5, the driver 6 is started. At its output, a signal is generated that is synchronized by the first phase of the clock signal of the generator 16, which sets the counter 14 to its initial state and, via the OR 11 element, triggers the trigger 13, and is also inverted on the element HE 15, blocking the element AND 9 for the duration of the effect of this signal.

The subsequent signal of the second phase of the generator 16 through the element And 10 enters the counting input of the counter 14 which changes its state and generates at the output an address code of the multiplexer 12. Next, the signal of the first phase of the generator 16 is fed to the input of the element 9, interrogating the output state of the multiplexer 12 and, respectively, the source of power 1.

In the absence of a signal of a logical unit (source 14 fault) at the first information input of the multiplexer 12 at the output of the element And 9 there is no signal. The second phase clock signal is then passed through the AND 10 element to the counting input of the counter 14, which forms the address code for the state of source 1. The next signal of the first phase polls the state of this source, etc.

Consider further the operation of the device in the event of a failure of some source 1.

At the output of this source 1, the voltage is out of range. In this case, depending on whether the limit has been violated (upper or lower limits), threshold element 2 or 3 is triggered. A unit level signal appears at the output of the OR element 4 and at the input of multiplexer 12. When this input is read, the output of multiplexer 12 is set to a single-level signal, which, by the appearance of a clock signal of the first phase, arrives at the setup input of the trigger 8, respectively, turning it on.

A single-level signal from the output of the trigger 8 sets the trigger 13 to the initial state and is transmitted to the output of the device via the bus 18. The trigger 13 through the inputs of the elements 9 and 10 blocks the circuits of both phases of the clock signal. A code corresponding to the number of the faulty power source is transmitted to the buses 20 from the output of the counter 14. The computer receives information about the number of the failed power source, starting to read the information from the buses 20 to receive the interrupt signal from the bus 19.

I

To keep the device running

on the computer control, a signal is transmitted to bus 18, which starts the driver 7. From the output of the driver 7, the synchronized signal through the element OR 11 resets the trigger 8, turns on the trigger 13, which causes the control cycle to continue.

Claims (1)

Invention Formula A device for monitoring the power supply system containing N secondary power sources, the inputs of which are connected to the input bus of the primary power supply network of the device and the integrator input, two pulse drivers, the first trigger connected by the installation input to the output of the first element AND, the first level sensor containing the OR element, the first and second inputs of which are connected respectively to the outputs of the first threshold elements of overvoltage and undervoltage, the output of the first flip-flop being the fault output and powering the device, characterized in that, in order to increase the resolution of the control device, a multiplexer, a second AND element, a second trigger, a NOT element, a pulse generator, an OR element, (Y-1) -th level sensor, each of which contains the OR element, the first and second inputs connected respectively to the outputs of the threshold and overvoltage elements, the output of the 1st secondary power source (, N) connected to the inputs of the overvoltage and undervoltage elements of the 1st level sensor, Exit to the OR element 0 second is connected to the i-th information input of the multiplexer, WELLPUT connected to the first input of the first element I, the second input of which is co-connected with the clock inputs of the first and second pulse formers and the first output of the pulse generator, the second output connected to the first input of the second element I, the output of which is connected to the counter input of the counter, the output of the counter is the output of the code of the faulty power source of the device and connected to the address input of the multiplexer, the reset input of the counter is connected to the first the input of the OR element and the output of the first pulse generator, the enabling input of the integrator connected to the output, the enabling input of the second pulse driver is the device start input, and the output is connected to the second input of the OR element whose output is connected 5 with the reset input of the first trigger, the installation input of the second trigger and through the element NOT with the third input of the first element I, the fourth input of which is connected to the second 0 to the input of the second element And the output of the second trigger, the reset input connected to the output of the first trigger.