SU1660178A1 - Convolution code decoder - Google Patents

Abstract

The invention relates to telecommunications and can be used in digital transmission systems using a convolutional code when decoding using the Viterbi algorithm. The aim of the invention is to improve the speed of the device. The device comprises a synchronizer 1, a block 2 for calculating branch metrics, processing channels 3 consisting of a comparator 4, an erasing unit 5 and a subtractor 6, a state metrics calculating unit 7, a memory unit 8, a correction unit 9, a timing unit 10 and a register 11 10 il.

Description

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The invention relates to telecommunications and can be used in digital transmission systems using a convolutional code when decoding using the Viterbi algorithm.

The aim of the invention is to improve the speed of the device.

Figure 1 shows a block diagram of a convolutional code decoder; in fig. 2 - synchronizer; FIG. 3 shows a block for calculating branch metrics; in FIG. 4, a subtractor; FIG. 5 shows the bending unit; FIG. in FIG. 6b, a state Metric calculation unit; Fig. 7 shows the comparison-addition-selection node; on Fig - correction block (figure 2-8 disclosed individual blocks of the decoder convolutional code for example code with speed 1/2 and code limit 2); Fig. 9 is a graphical illustration of the decoding process of a completely zero Viterbi code sequence using known decoders (a); the same, but using this decoder (b); in fig. 10 - decoding a completely zero sequence using an abbreviated search based on the known principles (a); the same, but based on the principle of processing branch metrics proposed in the invention (b).

The device comprises a synchronizer 1, a block 2 for calculating branch metrics, processing channels 3 consisting of a comparator 4, an erasing unit 5 and a subtractor 6, a state metrics calculating unit 7, a memory unit 8, a correction unit 9, a timing unit 10 and a register 11 .

Synchronizer 1 contains an inverter 12, keys 13-24, D-triggers 25-30.

The branch metrics calculation unit 2 contains registers 31 and 32 and a fixed memory node 33.

Subtractor 6 contains a group of 34 inverters, adders 35 and 36 and multiplexer 37..

The erasing unit 5 contains elements 38-43 OR.

The state metric calculating unit 7 contains the comparison-addition-select nodes 44-47 and the comparison node 48.

Block 9 correction contains adders 49-51 modulo two, inverter 52, elements And 53-55, elements OR 56 and 57, counters 58 and 59 pulses and D-flip-flop 60.

Each of the comparison-addition-select (CER) nodes 44-47 comprises a comparator 61, a multiplexer 62, a register 63, and adders 64 and 65.

The decoder works as follows. Synchronizer 1 input synchronously with the clock signal receives an information signal, the three bits of which are a quantized value

one received character code sequence. In the synchronizer f, these quantized values are grouped in pairs - each pair of three-bit signals corresponds to one received code branch.

Since in a continuous sequence of three-bit signals

ten ...

the boundaries of the code branches are not known a priori, then there are two possibilities for their group-and-15 operations:

Correct branch synchronization

five

0

five

0

five

0

five

Incorrect synchronization of branches

Synchronizer 1 ensures the correct synchronization of the branches according to the signal that arrives at its second input. The outputs of synchronizer 1 are rewritten to block 2 of calculating branch metrics with a clock frequency that is two times less.

The operation of unit 2 according to Table 1.

Tab. 1 contains four matrices, each of which describes signals on one group of outputs of block 2. At any position of the matrix there is a decimal equivalent of a three-digit binary number that appears on this group of outputs. Suppose that code branch 01 is received without errors. Then, on the group of outputs M2, the metric of branch 01, which is equal to 000 and corresponds to the position A7 in the matrix (marked in the table with a circle), is used. On the output group M2, the metric is branch 10, which is 111 and corresponds to the decimal equivalent of 7 in the same position A7. On groups of outputs M1 and M1 of opposite metrics, branches 00 and 11 in the same positions A7 have equal values of 3, which are the decimal equivalent of the number 011. When these equal values arrive at the inputs of the subtractor 6. YO will output the signal at its output equal to 3 - 3 0. It is fed to the first input of the comparator 4 and, since the threshold signal at the second input of the comparator 4 is not less than 0, then at its output a log signal is output. 1 and will cause on both outputs of block 5 signals 111 no matter what values of the metrics

branches took place at its first and second entrances.

This means that the branch metrics, calculated in block 2, are erased, and in block 7, through register 11, information is received that the transmission of code branches 11 is not very reliable. The difference in the metrics of the branches 01 and 10, obtained in the corresponding subtractor 6, whose input is connected to the outputs M2 and M2, is equal to O - 7. The absolute value of this difference, 7, the reader 6 outputs to the inputs of the corresponding comparator 4, and since the threshold signal at its second input does not exceed 7, then the output of the comparator receives a log signal. O, which will ensure that the 01 and 10 branches metrics calculated in block 2 are unchanged at block 7 through block 5 and register 11. This means that block 7 receives information that code branch 01 is most likely and code branch 10 not very likely.

Further processing of branch metrics in block 7, memory block 8, and correction block 9 does not differ from processing in known decoders. In particular, in block 9, the reception quality is continuously evaluated based on the decoding results. If the reception quality is below the acceptable level, it is determined that the synchronization of the branches is incorrect and the second input of the synchronizer 1 is given a signal to correct the synchronization branches.

The state metric calculation unit 7 operates as follows.

The clock input of the state metrics calculation unit 7 receives a signal from the block 10. Synchronously with the clock signal (the bit boundaries coincide with the clock signal transition from the log to the log. 1) the information inputs of the block 7 from the register 11 are received in parallel code by three-bit branch metrics , which are indicated in Fig. 6 as follows: M1 - metric of the branch M1 - metric of the branch M2 - metric of the branch M2 - metric of branch 10.

As can be seen from Fig. 6, block 7 consists of 2 (in this example, V 2) identical processing nodes 44-47 of the CERs, which operate simultaneously, in the same way and in interaction with each other. Therefore, we consider the operation of a single CER node.

Node 45 of the CER stores a four-bit binary number — let's call it the M7-2 state metric. This number is summed with the two metrics of the M2 and M2 branches entering the inputs of the node 45 of the CER register 11. As a result, two sums are formed, which we denote as follows: M2 -t -NI7-2; M2 + M7-2.

The first of these amounts is fed to the input of the node 46 CER, and the second - to the input of the node 47 5 CER.

As a result of a similar operation, the sum of М1 + М7-1 is formed in the node 44 of the CER, which from the output of the node 44 of the CER enters the input of the node 45 of the CW.H.Also in the node 46 of the CER 10 forms the sum of M1 + M7-3, which from the output of the node 46 enters input node 45 CER.

These two sums are compared with each other at node 45. If the 15 inequality M1 + M7-1 M1 + M7-3 is satisfied, then the output of node 45 is a log level. 1. From this point in time, node 45 will store the sum of M1 + M7-1: M7-2 M1 + M7-1 as the state metric M7-2, and 0 the previous value M7-2 will be erased.

If M1 + M7-K M1 + M7-3, then

node45 as a state metric M7-2

will store the amount of M1 + M7-3: M7-2

 M1 + M7-3, and the previous value of M7-2

5 is also erased.

Similarly, the remaining nodes 44, 46 and 47 CERs work.

The newly obtained state metrics, through the outputs of all nodes 44-47 of the CERs, are compared to the 2 inputs of the node 48 comparison. At node 48, all 2 state metrics are compared in magnitude. The signals at the outputs of node 48 are generated in accordance with Table 2. /

5From this table. 2 it follows that the log. one

it appears on only one of the two outputs of the comparison node 48, namely the one that corresponds to the largest state metric.

0 An electrical schematic diagram of nodes 44-47 CERs is shown in FIG. 7. For node 45, the metric M2 of branch 01 goes to the upper inputs, and the lower inputs - metric M2 of branch 10. In adders 5 64 and 65, the corresponding branch metrics are added to the state metric M7-2, which is stored in register 63. The results are summed through the outputs of node 45 go to the corresponding inputs of nodes 46 and 0 47. At the same time, the inputs of node 45 receive the summation results from the corresponding outputs of nodes 44 and 46, which are compared in magnitude in comparator 61 in FIG. The output signal of the comparator 5 61 is output to the output and at the same time controls the multiplexer 62. If the result of the summation, it arrives at the inputs A1A4 of the comparator 61. is greater than the result of the summation, entered at its inputs В1В4. then at the output of the comparator 61

there is a log. 1. Otherwise, a log will appear. ABOUT.

In the latter case, if a log appears at the A / B input of the multiplexer 62. 1, then a four-bit signal passes through its inputs through the inputs of the CER node 45. If, on the A / V input of the multiplexer 62, a log appears. Oh, then at its outputs a four-bit signal passes through third outputs 4.

The outputs of the multiplexer 62 are connected to the inputs of register 63, therefore, when the clock signal at the input from the log. About to log. 1, the output of multiplexer 62 is recorded in register 63 as a new state metric M7-2. The cycle described below is repeated.

The subtractor works as follows.

Let it be necessary to calculate the difference of two numbers: decreasing M1 1 (10) 001 (2); deductible M1 7 (10) 111 (2).

Then, in the adder 35, the following operations are performed.

The signals at the inputs A3, A2, A1. AO: 0001. Signals at the inputs of OT, B2, B1. VO: 1000. Signals at the input of PO.1.

The signals at the outputs S3, S2, S1. SO: 1010.

In the adder 36, the following operations are performed.

The signals at the inputs A2, A1, AO: 010, The signals at the inputs JB2, B1, JBO:. The signal at the outputs of S2, S1, SO: 110.

The signal 3 from the output of the adder 35 acts on the control input of the AV multiplexer 37 so that when S3 1, signals 110 (2) 6 (10) pass through its outputs, which is obviously a modulus of the difference of two numbers 1 and 7,

In the case when the decrease is greater than the subtracted, then the output of S3 of the adder 35 is the signal S3 0, which affects the control input AB of the multiplexer 37 so that its outputs pass the signals S2, S1, SO from the outputs of the adder 35. They are a positive number, which is itself a modulus of the difference.

For a comparative evaluation of the traditional and proposed principles for processing branch metrics, a direct calculation of the decoding process of a convolutional code was performed when operating in a binary symmetric channel with an error probability of 001. The results are presented in the form of a trellis diagram in Fig. 9 of the decoding process.

It was assumed that when transmitting a completely zero code sequence, the fourth and fifth code branches were received with errors, as shown in Fig. 9, where the number of the received code branch coincides

em with decoding step number. From FIG. Ea, which graphically depicts the decoding process based on the traditional processing of branch metrics, it can be seen that

the two erroneously received code branches at the 4th and 5th decoding steps caused an erroneous event at the 4th-9th decoding steps, which is that the decoded sequence is not

0 is the same as the transmitted (completely zero sequence).

Bold lines indicate code sequences stored in memory block 8. Noise immunity

5 decoding is the higher, the better these sequences coincide with each other. As can be seen from Fig. Ea, up to the 24th decoding step, three sequences are stored in the memory of the decoder, which are dispersed with each other at the 4th and 8th decoding steps. Therefore, at the 24th decoding step, it is still not possible to say that, starting from the 10th decoding step, the event will be correct, since at

5, the 10th decoding step with the correct sequence matches only one of those stored in the decoder memory.

As can be seen from Fig.96, the proposed principle of processing branch metrics results

0 to a significantly better result. With exactly the same error in the channel (4- and 5-branches are taken as 11, although a completely null sequence was transmitted), an erroneous event did not occur at all, and, starting from the 9th decoding step, all sequences that are stored in the memory of the decoder (they are also highlighted in bold lines) merged into one correct sequence in the branch x 1-9.

0 This means that at the 9th decoding step, it is safe to say that these branches are accepted correctly. In this particular example, the decoding delay, equal to 14-3-11 steps, is

5 sufficient to correct a channel error. At the same time, in traditional processing, the coding delay equal to 24 - 3 21 steps is not sufficient for reliable decoding.

0 An even more significant effect is provided by the proposed principle of processing branch metrics in the case of an abbreviated basic search procedure based on the Viterbi algorithm.

5 An example of calculation for an abbreviated search is shown in FIG. 10 under the same conditions in the transmission channel. The calculation shows that by reducing the number of calculations in the decoder processor by 2 times, the traditional principle of branch processing can lead to a so-called catastrophic error. As can be seen from FIG. UA, it consists in the fact that the error event does not end at the final coding delay: no decoded sequence is stored in the decoder memory that matches the completely zero transmitted code sequence.

If the proposed principle of processing branch metrics is used in such an abbreviated decoding procedure, then. as shown in FIG. 106. after an erroneous event, starting with the 8th decoding step, the decoder begins to correctly decode a completely zero sequence.

Claims (1)

Claims of the Invention A decoder code containing a synchronizer, the first input of which is a decoder input, n synchronizer output groups (where n is the number of code symbols forming one code branch) are connected to the corresponding inputs of the branch metrics calculator, the state metric calculator The outputs of which are connected to the corresponding inputs of the memory block, the outputs of which are connected to the corresponding inputs of the block correction, the first and second outputs of which are connected respectively to the decoder output and the second synchronizer input, the third input of which is connected to the first output of the clock unit, the second output of which is connected to the second inputs of the branch metrics calculator, the state metrics calculator, the memory block and the block correction, characterized in that, in order to increase speed, a register and 2P processing channels are entered into it, each of which contains a subtractor, a comparator and an erase unit, the first and second inputs of the subtractor and the erasing each processing channel in pairs are combined and connected respectively to the outputs of the metrics of the opposite branches of the branch metrics computing unit, the subtractor's outputs are connected to the first inputs of the comparator of their processing channel, the output of the comparator is connected to the third input of the erasing unit of the same processing channel, the outputs of the erasing all channels are connected to the corresponding information inputs of the register, the clock input of which is connected to the second output of the clocking unit, the second inputs of the comparators are connected to the corresponding inputs of the threshold. Table 1 table 2 To block I . .G but en lg .one bt5p t t M 3S 37 and and but IN 1 -BUT to At s J5 / 41 FIG. five "about one I f {; (W) l ( E I42 Jrr .. 6 / 2gm block m (m) FIG. 7 "Jo I 62 63 to block 7-7 ... 7-H K vpokuV 5  To block 7-5 :) From block B Is correct  PMtoMQ event  Sequence oo oo 04 About 1 2 7} be ouiuSovfttte. /. ffemft / W, W 00 00 00 00 Correct kodoZo sequence / 00 00 00 00 00 00 00 00/00 00 00 00 00 00 00 uj.-sh chi ii ai vu ii ai ii ai ii aa ca ii ai iii / w ii ai ii ii ao oo ai 3 5 B 7 B 9 W 11 12 13 15 76 17 1B 19 20 21 22 23 24, Delay Decoding / 00 00 00 Iff / U1 00 00 00 00 00 00 00 00 (7, 3 O 1 2 3 "5 b 7 B 9 10 11 12 13 14 breathing ff To block Correct kodoZo sequence / 00 00 00 00 00 00 00 00/00 00 00 00 00 00 00 ai ii ai ca cha ii ai ii / w ii ii ai ii oo ai W 11 12 13 15 76 17 1B 19 20 21 22 23 24 , 3 I Fig.Z and osem cfsuon § ew 5J S