SU1658159A1 - Device for user interfacing to a computer - Google Patents

Abstract

The invention relates to computing and can be used, for example, for organizing communication systems of subscribers (computing modules) with a host computer in distributed process control systems. The aim of the invention is to reduce the hardware cost of the device. The goal is achieved by the fact that the device containing in each communication unit with the subscriber a request trigger, two AND-NOT elements, a NOT element, three AND elements, an address switch node, a transceiver node, an address comparison node, a receive ready trigger, input and output registers , a switch, a priority trigger, a load element and a separation element are introduced into each communication unit with the subscriber. The organization of data exchange between computers and the obonents via a single information bus of the address / data and ensuring the reciprocal confirmation of the receiver’s readiness to receive the next message from the computer reduces the hardware costs and simplifies the transmission of the broadcast message to all connected subscribers. When the device is operated, the priority of subscribers for access to computer resources is not violated. Full operability in the event of a power failure of the K-th communication unit is maintained. 2 Il. J

Description

The invention relates to computing and can be used in computer systems of automated control systems.

The aim of the invention is to reduce the hardware cost of the device.

FIG. 1 shows a fragment of the device and a functional diagram of a communication unit with a subscriber; in fig. 2 is a block diagram of a device with an M communication unit with a subscriber;

The device contains (Fig. 1) in each communication unit with the subscriber node 1 transceivers, node 2 address switches, node 3 address comparison, input register

4, output register 5, request trigger 6, priority trigger 7, receive readiness trigger 8, first, third and second elements AND 9-11, AND-NO elements 12, 13, HE element 14, load element (resistor) 15, breakaway element (diode) 16 and switch 17.

The device (Fig. 2) contains M communication units 18 with a subscriber. FIG. 1 and 2 also shows a block 19 of matching resistors, information inputs 20 and outputs 21 of block 17, inputs of writing 22 and reading 23 of block 18, readiness outputs of transmitter 24 and receiver 25 of block 18, inputs of demand

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interrupts on input 26 and output, 27 computers, computer output synchronization line 28, computer input synchronization lines 29, information data bus 30 / computer addresses, relay elements 31.1 and 31.2 of switch 17, computer 32, subscriber 33, load elements (resistors) 34 , lines 35-39 of intra-block communications, Information inputs and outputs, control inputs and outputs of each communication unit are connected respectively to information outputs and inputs, control outputs and inputs of the corresponding subscriber (the same designations are found in the description with the K index for the K-th channel and exchange, where K 1, M).

Computing modules (computers, processors, memory blocks, etc.) can be used as subscribers 33.

The format of the message transmitted from subscribers 33 to the computer via information bus 30 includes the following fields: the sender's address; own data.

The format of the message transmitted from the computer to the subscribers 33 via the information bus 30 includes the following fields: the recipient's address; actually data.

Transceiver node 1 contains amplifying elements that, depending on the signal level at the control input Y, operate in two modes: 1st mode - 1, the bus lines 30 are switched on lines 39 and 35, and the data itself goes to the inputs of the input register 4, and the recipient's address is in node 3 of the comparison; The 2nd mode is 0 and the lines 36 and 37 are switched to the bus line 30.

Node 2. The address switches are designed to set the subscriber’s address 33 on lines 37. To and the addresses of the broadcast messages on lines 38,

Node 3 address comparison is designed to compare the recipient's field in the form of a message received by line 35 from the computer to the subscriber 33.K with the address of the connected subscriber 33.K (line 37) and with the address of the broadcast message (line 38). If the recipient's field matches in the message format with the subscriber address 33. To or with the address of the broadcast message at the output of the node 3. By comparison, a signal of a logical unit is formed, otherwise - a logical zero.

The elements of the node 1.K connected to the bus 30, the elements NOT 14.K and I 11.K are elements with an open collector.

The winding of the relay elements 31.1 and 31.2 of the switch 31.K is connected to the supply voltage of the subscriber source

33.K. At the normal supply voltage level of the source, the strict and third contacts of the relay elements 31.2, 31.1 are closed.

The device works as follows.

In the initial state, the triggers 6-8 of all blocks 18 are in the zero state: GPRD GPRM synchronization lines of output 28 and input 29 of computers are in the state of logical zero; the input 26 of the interrupt input request (TPRVV) of the computer receives a logical unit signal (there are no subscribers in the system,

5 requiring maintenance); the input 27 of the output requirement (TLBFV) of the computer receives a logical unit (the input registers of all subscribers are ready to receive the next message from the computer); node 1.K transceiver sensors is in the first mode of operation.

When transmitting information from the computer 32 to the selected subscriber, the computer 32 exposes on the bus 30 a message containing the address

5 recipient (subscriber) and the actual data, and produces a short-term single pulse on the output synchronization line 28. Let the message be intended for transmission to the Kth subscriber, then at the output of the host node Z.K a signal of a logical unit is formed, which ensures the recording of data in the input register 4.K and the setting of the trigger 8.K in the unit state. GPRM.K 1 causes a signal transition

5 TRPVYV in the zero state (the input register of the subscriber is not ready to receive the next message from the computer), In addition, this signal arrives at the input of the subscriber 33.K and informs it about the presence in the input register 4.K to the received message. Subscriber 33.K reads data from input register 4. K from information inputs 21. To and generates a signal Read K, which arrives at the read input of block 18. K communication, which causes a reset trigger 8. To receive readiness. The transition signal TRPVYV informs the computer about the possibility to transfer the next message to the subscriber.

0 Subscriber 33, K, if he has information for transmitting the computer 22, exposes the information inputs 20. To the data and generates a short-term RECORD signal of a single level, which

5 is connected to the input 22.K of the recording of the 18.K communication unit. At the signal RECORD. The K writes the data to the output register 5.K and sets the trigger 6.K to the request to one. The transition signal TPRD.K to zero state informs the subscriber

33.K that the data recorded in the register 5.K are not yet received by the computer. Elements 11, AND-NO 12 and priority trigger 7 are designed to queue the subscriber request service 33.K to interrupt the operation of the computer. The operation of this circuit is carried out in accordance with the following table.

Let the subscriber 33.K - the leader of the queue. Trigger 7.K. priority is in the state of CHOICE. K 1. The transition of the signal TRPVV in the state of zero level interrupts the operation of the computer, which generates on the synchronization line 29 a short-term signal of the unit Input. The zero signal from the inverse output of the trigger 7.K of priority blocks the passage of the signal. Input through the element 10.K. In block 18 (K + 1) of communication. At the output of the NAND 13K element, a short zero level signal is generated, which ensures the transfer of the 1.K transceiver unit to the second mode of operation, while a message is generated on the bus 30 that includes the address from the governor from the 2.K switches and the actual data from the output register 5.K. The computer receives this message, unambiguously identifies the source of information by address and processes it.

When a circular message is transmitted, the computer exposes on bus 30 a message containing the address of the broadcast message and the data itself, and generates a short-time unit level signal Output on the computer output timing line 28. The difference of this mode from the message transfer mode from the computer to the selected subscriber is that the message is received simultaneously in all input registers 4.1-4. M, the processing of the sent message in each block 18 is carried out in a similar way.

Suppose that in block 18.K, the subscriber’s power supply source 33.K crashed, which causes the second and first contacts to short out of the elements 31.1, 31.2. At the same time, the E 10.K and the trigger and 7.K of priority do not affect the passage of the Input signal along the input synchronization line 29 to the input of block 18. (K + 1). The output of the element 11.K + 1 begins to work on the load register 15.K-1, and the diode 16.K eliminates the influence of the load resistor 15.K on the shaping of the TPRVV signal. Thus, the integrity of the demand circuit of the computer input is not violated.

Claims (1)

Invention Formula A device for interfacing a computer with subscribers, containing M blocks of communication with the subscriber, information inputs and outputs, and data output synchronization inputs of which are information input-output and synchronization input of data output from the computer of the device, and information input and output, write and read inputs and readiness outputs for receiving and transmitting M communication units with the subscriber are the corresponding subscriber information input and output , write and read inputs and readiness outputs for receiving and transmitting a device, a block of matching resistors connected by input-output to information input-output from a computer of a device, and the first load el A device connected by the outputs of a positive polarity of the device and the output of the interrupt request input of the first communication unit with the subscriber respectively; the input data synchronization input and the output interruption demand input of the first communication unit with the subscriber are the input synchronization input and output respectively Requirements to interrupt the input of the device, the input of the request for interruption of the input and the output of data input synchronization K-th (K 1, M-1) of the communication unit with the subscriber are connected respectively to the output t Fucking interrupt input and input synchronization input data K + 1 of the communication unit with the subscriber, each communication unit with the subscriber contains a transceiver user whose information input-output is connected to the information input-output unit, input and output registers, node address switches, address comparison node, request trigger, receive readiness trigger, NOT element, three AND elements, two NAND elements, the first information input and output of the transceiver node being connected to the output register, respectively The information input and input register, the second information input and output of the transceiver node are connected respectively to the first output of the address switch node and the first information input of the address comparison node, the second information input of which is connected to the first output of the address switch node, the first input of the first And element is input synchronization of the data output of the communication unit with the subscriber, and the output is connected to the synchronous input of the receive ready trigger, the output of the input register, the information input and the sync The output registers are, respectively, the subscriber information output and the input and input of the record of the communication unit with the subscriber, the direct and information outputs of the request trigger. respectively, connected to the first inputs of the first NAND element and the second AND element, characterized in that, in order to reduce the hardware costs of the device, a priority trigger, a switch, a second load element and a separation element are entered into each communication unit with the subscriber; interrupting the output of each communication unit with the subscriber is connected to the subscriber output of the request to interrupt the output of the device, and in each communication unit with the subscriber the installation input of the priority trigger is connected to the output of A NAND element whose second input is connected to the first information input of the switch, to the input request to interrupt the input of the communication unit with the subscriber, and through the load element to the first output of the separation element, to the second output connected to the bus of the positive polarity of the source power supply of the device, the synchronous input input register is connected to the output of the first element I, the second input of the address comparison node connected to the output, the second information input of which is connected to the second output of the switch node ad control unit, the control input of the transceiver node is connected to the synchronous input of the request trigger and the output of the second NAND element, the first input of which is connected to the direct output priority trigger, the reset input of the request trigger connected to the forward output, and the inverted output to the first input of the third I element, the output of which is connected to the second information input of the switch, the control input of which is the voltage input of the subscriber of the communication unit with the subscriber, and the third information input of the switch is connected to the output of the second element I, the second input of which is connected to the first output of the switch and the output of the request to interrupt the input of the communication unit with the subscriber, the second inputs of the second element The NAND and the third element AND are connected to the fourth information input of the switch and the input data input synchronization input of the communication unit with the subscriber, the output of the receive readiness trigger is connected via the NOT element with the output of the output interrupt request output of the communication unit with the subscriber, the second output of the switch, the setup input and the inverse trigger output of the request, the output and the reset readiness trigger input are respectively the input data synchronization output, the recording input, the transmission readiness output, the receive readiness output and the read input and block communication with the subscriber data inputs and Request latch toiggera reception readiness are respectively connected with buses logic zero and logic unit of the device. Mai 1 FIG. 2