SU1644145A1 - Device for microprocessor system debugging - Google Patents

Abstract

The invention relates to computing and can be used to configure and control multiprocessor systems with a multi-trunk structure. The aim of the invention is to expand the functionality by implementing real-time monitoring of multiprocessor systems. The device contains main, buffer and input drives, data registers, addresses and returns, output register, subscriber communication unit, mode storage unit, control input synchronization unit. , block of exchange, block of cycles, output of test information, block of microprogram control, blocks of internal and system synchronization, block of indication, block of entry, block of automatic loading , counter, two multiplexers, switchboard, switchboard distributor, transition decoder and pause decoder, trigger, input control unit, selector, The device provides manual and automatic modes for loading the main drive and outputting information to it into the system, generating test data sequences necessary for diagnosing the system operation, as well as monitoring information on the trunk associated with one of the device ports. At the same time, the information is output through a high-speed buffer drive with a system clock frequency, and the data is monitored in the listening mode in (L1), which allows you not to interrupt working programs. As a result, the time for preparing, reconfiguring and diagnosing the system in comparing with known universal technical solutions, 30 il., 10 tab. OD OD 4 4 SP

Description

 The invention relates to computing and can be used to configure and control multiprocessor systems.

The purpose of the invention is to expand the functionality by organizing real-time debugging of multiprocessor systems.

Figures 1 and 2 depict a diagram of an arrangement TcJ in Fig. 3 - a diagram of a keyboard input unit} in Fig. 1 - a diagram of a control unit; FIG. 5 is a data register circuit; FIG. 6 is an address register circuit; FIG. - diagram, transition diagram and phase portrait of the automatic loading unit; in fig. 10 is a diagram of the storage unit pe10.

20

31644145

press, FIG. 11 is a diagram of the switch; FIG. 12 is a diagram of an internal synchronization unit; FIG. 13 is a block diagram of the display unit; FIGS. 14 and 15 are a diagram and transition diagram of a communication unit with a subscriber; FIG. 16 is a block diagram of an input synchronization block; FIG. 17 is a diagram of selector j in FIG. 18 is a diagram of the main accumulator in FIG. 19 is a circuit of a register of return j in FIG. 20 is a circuit diagram of a counter, FIG. 21 and 22 are a circuit and a transition diagram of the microprogram control unit 1, FIG. 23, block diagram of the system synchronization 1, figs, 24 and 25 is a diagram and transition diagram of the block of output of test information; FIG. 26 is a diagram of an exchange control unit; FIG. 27 is a diagram of a switchboard; on Fig-30 - time diagrams of the device,

The device part shown in FIG. 1 contains an input block 1, an input control block 2, a data register 3, an address register 4, an automatic boot block 5, a mode storage block 6, a switch 7, a trigger 8, an internal synchronization block 9, a block 10 display, block 11 of communication with the subscriber, block 12 of input synchronization, selector 13i, input accumulator 14, marker input 15, data input 16, input / output 17 of receipts, input-output 18 occupancy. In addition, the data bus 19 and the address bus 20 are allocated. The device part, shown in FIG. 2, shows sync output 21, main storage 22, buffer storage 23, first and second multiplexers 2k and 25, return register 26, counter 27, comparison block 28, transition decoder 29, element OR- NOT 46, hi and 48 triggers, encoder 49, generator 50, block 51 buffer amplifiers, buttons 52-59,

Block 2 contains the register 60, the decoders 61 and 62, the elements And 63 and 6, the element OR 65.

The data register 3 contains a trigger 66, elements AND 67 and 68, an element AND-NOT 69, a group of elements AND-NOT 70, elements EXCLUSIVE OR 71 and 72, a register 73, a multiplexer 7 and a register 75,

Register 4 addresses contains the elements And 76-79, a group of elements-AND-NOT 80, 15 elements OR 82 and 81, trigger 83, register 81, multiplexer 85, register 86,

Block 5 contains the register 87 and ROM 88.

Block 6 contains the register 89, the trigger 90, the decoder 91, the element And 92, the elements AND-NOT 93-96

Switch 7 contains a two-channel multiplexer 97 and a four-channel multiplexer 98.

Block 9 internal synchronization contains triggers 99-SW, counter, elements 2И-OR 105-107, generator 108,

The display unit 10 contains multiplexers 109-111, a decoder 112, an encoder 113, a generator 114, a counter 115, an AND element 116, an EXCLUSIVE OR 117 element, transistors 118, and sign-synthesizing indicators 119.

Block 11 contains multiplexers 120-122, register 123, elements AND 124-126, elements AND-NOT 127-133, element OR-NOT 134, elements NOT 135 and 136 and element AND-NOT 137 with an open collector,

Block 12 contains the trigger 138-142, the element AND NOT 143, the element AND

25

thirty

35

40

the input register 30, the microprocessor 31 31, 144, the OR element 145, the 2I-OR-gram control element, the system 32 HE-146 and the button .147.

synchronization, block 33 of the test information output cycles, block 34 of exchange control, decoder 35 pauses, switchboard distributor 36, group of inputs 37 receipts, group of inputs 38 occupancy, input 39 of the number of output message and input 40 of the initial installation, In addition, highlighted bus 41 early and bus 42 addresses. The outputs form the information outputs of the device.

Block 1 contains the element AND-NO 43, the element OR-NOT 44, the element AND-NO 45,

50

55

The selector 13 contains counters 148 and 149, the element OR 150, the elements AND-NOT 151 and 152 and the element NOT 153.

The main drive 22 contains RAM 154, the element AND-NOT 155, the element And 156.

Register 26 return contains the elements AND NOT 157 and 158, the element And 159 and register 160,

The counter 27 contains the elements OR NOT 161 and 162 and the counter 163.

Block 31 contains a register 164, multiplexers 165 and 166, SSN 167 and 168,

0

0

element OR-NOT 46, hi and 48 triggers, encoder 49, generator 50, block 51 buffer amplifiers, buttons 52-59,

Block 2 contains the register 60, the decoders 61 and 62, the elements And 63 and 6, the element OR 65.

The data register 3 contains a trigger 66, elements AND 67 and 68, an element AND-NOT 69, a group of elements AND-NOT 70, elements EXCLUSIVE OR 71 and 72, a register 73, a multiplexer 7 and a register 75,

Register 4 addresses contains the elements And 76-79, a group of elements-AND-NOT 80, 5 elements OR 82 and 81, trigger 83, register 81, multiplexer 85, register 86,

Block 5 contains the register 87 and ROM 88.

Block 6 contains the register 89, the trigger 90, the decoder 91, the element And 92, the elements AND-NOT 93-96

Switch 7 contains a two-channel multiplexer 97 and a four-channel multiplexer 98.

Block 9 internal synchronization contains triggers 99-SW, counter, elements 2И-OR 105-107, generator 108,

The display unit 10 contains multiplexers 109-111, a decoder 112, an encoder 113, a generator 114, a counter 115, an AND element 116, an EXCLUSIVE OR 117 element, transistors 118, and sign-synthesizing indicators 119.

Block 11 contains multiplexers 120-122, register 123, elements AND 124-126, elements AND-NOT 127-133, element OR-NOT 134, elements NOT 135 and 136 and element AND-NOT 137 with an open collector,

Block 12 contains the trigger 138-142, the element AND NOT 143, the element AND

five

0

five

0

5 144, element OR 145, element 2-OR-NO 146 and button .147.

0

five

The selector 13 contains counters 148 and 149, the element OR 150, the elements AND-NOT 151 and 152 and the element NOT 153.

The main drive 22 contains RAM 154, the element AND-NOT 155, the element And 156.

Register 26 return contains the elements AND NOT 157 and 158, the element And 159 and register 160,

The counter 27 contains the elements OR NOT 161 and 162 and the counter 163.

Block 31 contains a register 164, multiplexers 165 and 166, SSN 167 and 168,

elements AND 169 and 170, elements AND-NOT 171-173, element OR 17 and element NOT 175, element AND 176.

The system synchronization unit 32 contains a trigger 177, an element ZI-OR 178, elements AND-NOT 179-180, and elements AND 181 and 182.

Block 33 contains a register 183 and 184, counters 185 and 186, ROM 187, multiplexer 188, elements NOT 189 and 190.

Block 3 contains triggers 191-193, element 2И- AND-OR 19, elements AND-NO 195 and 196, element OR-NOT 197, element OR 198, and element NOT 199.

The switchboard 36 contains a register 200, a demultiplexer 201, a multiplexer 202, and an element 2I-2-OR-NE 203.

In Figs. 1-30, the following functional designations of the inputs are accepted: CR transfer transfer, CE - account resolution; С / Р - operation mode (0 - preset, 1 - count) j PE - preset, A - cell address or channel number; G) - information input, Z - input of the control of the third state; R is the input of the initial installation or the gate input.

The device works as follows.

Information intended to be loaded into other devices of the system is initially entered into the main storage device 22. The input is made either from unit 1 or from input 16 in automatic mode. The output from the accumulator 22 is performed via the buffer accumulator 23, the output register 30. Further, the information is sent through the switch-distributor 36 to one of the output ports, each of which includes a data output, an input of 37 receipts and an occupancy input 38.

As storage device 22, it is convenient to use either MOS schemes, which provide the ability to store information when the power is turned off by switching to a micromotive autonomous power source, or other volatile memory circuits. In the case of operation of the device in the system for which the clock frequency is chosen in relation to the high-speed element base (TTL-SH, ECL, etc.), the speed of drive 22 provides: with insufficient and therefore information before outputting it from the drive 22 at

the system is pre-written to the high speed drive 23

The structure of words in accumulators 22 and 23 is generally AB, where A is the external part intended for output to the system, and B is the internal part used to control the transition to the next word. They are applied through four viral transitions: B 0 - stopping the output (end of the message), B 1 - switching to reading the neighboring word by increasing the state of the counter 27 by one; B 2 is the same as above, additionally register 26 stores the current state of counter 27, which is received through register k and multiplexer 2k, B 3 returns to the address from register 26,

The software case reset 26 is only used when reading from the buffer accumulator 23 and allows the organization to organize cyclically repetitive test data sequences for the system. The number of cycles is defined by block 33, which, when the specified number of cycles is reached, replaces the return to the beginning of the cycle with a transition to the next adjacent word.

The structure of gender A in the message word depends on the type of the word. There are three types of words.

a) Address word A1 OMO ..,

... NЈN ... NЈ, where m 1 and N are single-bit attributes distinguishing in a group of (k + l) -ro devices acting on the output line, devices that will receive messages and possibly run and that will only run according to previously entered messages.

b) The tuning word A2 11CH, where H is the tuning (program) information, C is the subaddress in the subscriber-device to be loaded,

c) The working word, where. 1, D - data, M and M & - single-bit marker bits. There is no subaddress here, since for each device of the system it is assumed to be unique — operational, super-operational, or buffer memory. Using marker bits, commands such as latching an element number in a sequence of data that is received later when reading

for basic, and starting the processing,

When loading several devices of the system, the message is divided into corresponding blocks, each of which begins with the address word A1. The blocks are separated among themselves by the words A2 pause, in which C 1 ... 1. Communication with the subscriber device is carried out when there are no other message sources on the output line, which is characterized by the third state on the busy line 38K. In the case of a free line, the address address A1 of the message is set at the output of the 36K distributor switch. If the message consists of several blocks, i.e. If the transmitted information is intended to be loaded into various devices of the system, then a break in the message initiates a break in communication with the old subscriber device. After the line is freed, it receives a new adress, which establishes communication with the new device of the system.

The device has three subgroups of submodes y, P and 0. Group Y sets the control, input and output of its own messages, group P - the generation of test sequences, data and the group ®KL-control messages from other devices

parts of DVK and D. This is due to the fact that the data size at input 16, as well as at outputs 36, is less than the size of accumulator 22 by the value of field B, which controls transitions in accumulators 22 and 23. In addition , when entering the Dfc data into the device in question, the latter need to be supplemented with their own subaddress C. As a result, two words of the input message are required to enter each word in the accumulator 22. When unpacking the input message, as well as when entering

system. Consider each of the names of 35 blocks 1, Am, and Dt are placed in registers b and 3, respectively, and in block 6, the submode H is set. Hocrte input in the register 3 second partly in registers b and 3, and in b 6, the submode H is set. Hocrte input in register 3 second hour

groups of submodes.

Message control 00, In the register, the address of the 22 cells monitored in the accumulator is set. When the Start button 57 is pressed, the word from the command 40, the corresponding pressing of the accumulator 22 is read the word, the button 57 Start at the address, and after

whith d of the first given

input of the second part of D | the second and se subsequent data is the command corresponding to the pressing of the button 58 Starting counting. Requirements to distinguish the time of formation of the start command (only after entering the second fragment DJ;), as well as the type of start (at the address for the first given and counting for all subsequent ones) are provided by subaddress C,

This is placed in register 3. The display unit 1 displays the contents of the selected cell and its address. Subsequent pressing of the button 58 Start counting leads to the selection and display of the contents of the neighboring cells of the drive 22.

Enter message Y. , In registers 3 and 4, the given data and address of the record are typed accordingly. After pressing the Start button 57, the address at the specified address is written, and then reading into register 3, Block 10 shows the address of the selected cell and its new content. Pressing button 58 further first changes the address in counter 27 by one, and then produces a new address

A record from the register 3 to the drive 22. In this case, this record will be a copy of the content from the previous cell,

Let now in the considered device, which has its own H number, the message is entered

JQ automatically. This input starts with the appearance at the input 15 and 16 of the address word A1, in which NH 1. This leads to the inclusion of an AND block giving permission to receive a message, words in which will have, depending on subaddress C, contents according to Table 1, where Ls is the starting address from which the formation of a message should be started in drive 22, D is the given address of this message. Each given CU is loaded with two

15

25

thirty

parts of DVK and D. This is due to the fact that the data size at input 16, as well as at outputs 36, is less than the size of accumulator 22 by the value of field B, which controls transitions in accumulators 22 and 23. In addition, entering the data device Dfc into the device in question requires the addition of their own subaddress C as a result. As a result, two words of the input message are required for entering each word into the accumulator 22. When unpacking the input message, as well as when entering

from block 1, am and dt are placed in registers b and 3, respectively, and in block 6 a submode H is set. Hocrte entering into the register 3 the second chaish command corresponds to pressing the button 57 Start at the address, and after

The command is equivalent to pressing the Start button 57 at the address, and after

whith d of the first given

The command is equivalent to pressing the Start button 57 at the address, and after

input of the second part of D | the second and see the following data - the command corresponding to pressing the button 58 Start counting. Requirements to distinguish the time of formation of the start command (only after entering the second fragment DJ;), as well as the type of start (at the address for the first given and counting for all subsequent ones) is provided by subaddress C,

Message output. In registers and 3, the starting address A of the message and the address of the control stop AO are set respectively. When the Start button 57 is pressed, the message from the drive 22 is rewritten to drive 23. Before outputting from drive 23 to counter 2

is recorded, which is retained during the whole of register 26 again the starting address of the NA, is stored in register 26 of the load period of drive 23. In the process of outputting the message from drive 23 to the system, when the word with address A0 is reached, the sample of the following words is stopped. At the same time, block 32 stops issuing clock pulses to the system, which allows monitoring of the system devices in statics. At the same time, at the output of the switchboard distributor 36 there is a word from the cell with the address AF, and in the registers C and 3 - the address АЈ + 1 and the corresponding word from the accumulator 23 But after the output is stopped, the button 57 is pressed, then the remaining words are automatically (without stopping). In the case of step-by-step message output, after the last word of the message, a continuous sequence of clock pulses is restored at the output of block 32.

Output from the device, as well as input, can be carried out automatically (by requests) from input 16. These requests initiate Start commands by

Address or Start

calculating,

In the first

In this case, the request is formed by a message of two words A1 A2, in which the address word A1 refers directly to the device in question, and in the tuning word A2 is taken C 1 and as H is the starting address of the AD output from message accumulator 22. To unpack the request, in block 6, the submode ,, is set, register 4 marks the address of the AC, after which the Start command is formed at the address. Since the control stop address Ao is not set here, in order to prevent an unprogrammed stop, in case the state of register 3 accidentally occurs in the address range of the output message, in block 28 of the comparison, its output is blocked. In the second case, the message consists of an arbitrary number of words and is addressed to another device. If at the same time in the address word A1 of this message N, 1, where H is still its own new

measures of the device under consideration, the Start command is estimated and the message is displayed with the starting address AC A yt. + 1, where A is the current state of the counter 27. As a result, it is possible to output individual messages placed directly one after the other.

FRIENDLY, in standby mode, when the output of each subsequent message occurs at. receiving from the system a response to one of the previous messages. In case of need fast

5 MANUAL output messages, but without the use of block 1, in drive 22, a zone of the full-digit start addresses of these messages is organized. Each of them is assigned a number, the number of bits in which can be made significantly less than in the initial addresses of the corresponding messages. These numbers are set at input 39, for example, using code switches of type PP-10-ZMS. When the Start button in block 12 is pressed, input 39 is connected to the address input of accumulator 22 via multiplexer 25, with the number of the displayed message deactivated on it. This number is converted at the output of accumulator 22 into a full-digit address, which through multiplexer 24 (mine register C) and then in transit through register 26 is set to counter 27. Further output of the message occurs according to the scheme already described above,

Let us now consider the group of subcategories R. With a small length of test sequences, the latter can be specified directly in the message itself. However, with a large length, it is more effective to directly assign a short, so-called generating subsequence (PP), by which one of two ways depends

0

five

five

from the submode P, longer test sequences are generated,

Generation of dough with stretching and repeating PP P0. Register 3 sets the number of K1 consecutive repetitions of each of the elements in the PN and the number of K2 cycles. Counter 27 in the test generation process increases its state by 1 only after the K1-fold reading of the current element in the PP. When the return point is reached in the message, the last the last element is copied to the PC, after which either the PC exit is completed by increasing the content of the counter 27 by 1t if the specified return point is already held K2-th time, or the start of the PC is returned to the beginning of the PC istra 26, JQ is thus rewritten in the counter 27. For example, if the PP is of the form 2 abc and K1, K2 3, the output test sequence budet15

aa hb her aa b b aa b b her

Generation of the test with interruption and repetition of the PP Rts, In register 3, the duration of the L1 interrupt (pause) in the cycles between the transponder and the number of L2 repetitions of the transponder is set. For example, if the PP has the form abc and L1 2, L2 3, then the output test sequence will be 25

abc AI abc AI abc,

where the symbol AND marks the cycles in which data is missing (on the corresponding data. If the Start button at the address is pressed after stopping, the filling of the accumulator starts again after skipping H of the data sequence elements. At the moment of filling the accumulator of the state register display board k in the block 10 goes out. Sequentially pressing the button 55 Result and one of the buttons 52 in block 1 results in display in block 10 of the contents selected from the accumulator cell and its number. Since the parameters Н ,, and Н are stored in the register If the stream is 3, then after outputting the contents from accumulator 1 to it, these parameters will be erased and with further continuation of the monitoring should be restored.

Active system monitoring © j. The lantern sub-mode differs from the previous one in the absence of other devices on the main line, except the one under consideration, which has its own number equal to N. As a result, this device itself generates signs of busyness and receipts. The sub-mode can be used to autonomously control individual devices in a system. The distributed switch output — distribution — personal combinations of sub-modes, forming the third state (36),

The control of the passive system is $ o. In register 3, the number H is set (the subscriber who is addressing the modes of operation of the device are shown in Table 2. The mode is set by sequentially pressing the 56 button and the monitored sequence is monitored in one of coherence, and the HQ number of the sequence element of the selectable mode,

If the step-by-step synchronization mode is necessary only when monitoring devices of the system, it is advisable to automatically output the message and then go to work on single clock pulses. (For this, the unit code is set in the fourth bit of the mode code, i.e. is shifted by 8. For example, when you enter a message, code 9 is set instead of code 1.

which starts the monitoring, In the monitoring process, the device in question does not generate, at the inputs-outputs 17 and 18, a receipt and an occupancy signal, which are issued by the subscriber device. When the address word A1 appears at the input 16, for which NЈJ 1, block 11, 45 gives permission to the selector 13. The latter starts counting the number of sequence elements received by the device and when Hg.-ro appears

4Q

element allows writing it and all subsequent elements of the sequence to drive 1 until it is completely filled. When this accumulator is completely filled in, block 32 stops the output of the sync pulses to the system and the state of the system is fixed. After pressing the Start button 58, the counting system resumes operation and the drive 1 is filled with the following sequence of data. If, however, after stopping, the Start button 57 is pressed at the address, the filling of the accumulator starts again after skipping H of the data sequence elements. At the moment of filling the accumulator of the state register display panel k in block 10 goes out, successively pressing the button 55 Result and one of the buttons 52 in block 1 leads to display in block 10 of the content selected from the accumulator and its number. If the memory is stored in register 3, then after the contents from accumulator 1 are output to it, these parameters are erased and with further continuation of the control should be restored.

Active system monitoring © j. The lantern sub-mode differs from the previous one in the absence of other devices on the main line, except the one under consideration, which has its own number equal to N. As a result, this device itself generates signs of busyness and receipts. The sub-mode can be used to autonomously control individual devices in a system. Razpok in the block of the corresponding code of the selected mode

If the step-by-step synchronization mode is necessary only when monitoring system devices, it is advisable to output the message automatically, after which a transition to single-clock operation occurs. (For this, a unit code is set in the fourth bit, i.e., the mode code is shifted by 8. For example, when you enter a message, code 9 is set instead of code 1.

If it is necessary to have the ability to work in steps at any point of input and output of a message, and with stopping both on the leading and trailing edges of the clock pulses, the button 59 is pressed.

Consider the work of individual units of devices.

Block 1 input. All buttons are divided into numeric and control groups. The number group includes 16 52k buttons used to load registers.

131644145

3 and 4, as well as block 6, and the control group of buttons corresponds to various executive and configuration commands of the device. Coding for

Both groups of buttons are implemented by common encoder 49, which converts the levels of negative logic into four-digit code 1.1. The latter is accompanied by a strobom 1,2 INPUT LOW LEVEL-

n To eliminate button chatter, this strobe is associated with generator 50 pulses using triggers 47 and 48 and element 45. The pulse duration in generator 50 is chosen so long that during this time transients for any of the buttons would end. To identify groups of buttons, a signal is generated 1.3 (0 is a numerical group, 1 is a control group). The composition of the teams and their coding are given in Table. 3. Button distribution from different groups is performed by the block 51 buffer amplifiers.

erasing the previous setting in register 60.

Entering numeric information is characterized by a low input level 7.3. This input follows immediately after the corresponding Address or Given configuration command and is not accompanied by writing to register 60. In accordance with the previous setting, either the sync signals for registers 4 and 3 (outputs 2.1 and 2.2), or the permission to write to registers 4 and 89 (outputs 2.3 and 2.4),

Register 3 data. It is a two-input register with parallel output 3.2, one parallel input 41 and one parallel-serial input 7.1. In the process of input from input 7.1. parallel-to-serial code conversion is performed. At the conversion time, inputs 2,4 and 8.1 are set to high levels, which

Input control unit 2. Appointment- 25 leads to the formation of a high level of a block — selection from information, n at the output of element 69, creating

the first resolution is for all elements 70. On command given at input 2.6, trigger 66 switches to state 1, 30 connected in multiplexer 74 to its output in parallel-to-serial input 7.1. At the same time, the register 73 is set to the state O and thereby creates a second resolution on the inputs of the elements 70); . Appearance of the first Let us first consider the selection of the control information at the output of the switch 7, which, depending on the code, is either decoded into the execution commands or used for the internal tuning of the block. According to this setting, writing to the corresponding registers of numerical information is then carried out.

The tetrad at input 7.1 is accompanied with a certain delay in the synchronization at input 2.2, which, in the lower order of register 73, is inserted into the unit information, which is accompanied by a high level at input 7.3. The input gate at input 7.2 code from input 7.1 is rewritten into a register

60. For a group of instructions with codes O,., 3, the state of register 60 in the next step determines which of the registers will be entered. This state is decoded in the decoder.

61, whose outputs O and 1 correspond to the choice of registers 4 and 3, respectively, output 2 - register 4

in the process of controlling the result (sampling from accumulator 14) and exit 3 - register 89 in block 6 of the mode. The first two commands (Address and Given) are parallelized with the entry into the register 60 and decoded in the decoder 62 and then used to initialize the registers 4 and 3 (outputs 2.5 and -. 2.6, respectively), when entering commands with codes 4, 5 and 6, the decoder 61 is blocked, which leads to

the first resolution is for all elements 70. On command given at input 2.6, trigger 66 switches to state 1, connected in multiplexer 74 to its output in parallel-to-serial input 7.1. At the same time, the register 73 is set to the state O and thereby creates a second resolution at the inputs of the elements 70); . The appearance of

The tetrad at input 7.1 is accompanied with a certain delay by the synchronization at input 2.2, which is moved one by one at the least significant bit of register 73, which leads to the formation of a positive front at the output of element 70 and the installation of the first tetrad in register 75. tetrad occurs

sequential filling with units of the following register bits 73 and, accordingly, loading with new tetrads of register 75.

After loading register 75 and starting

the device at a certain moment at the input 8 a low level receives a sign of the end of the recording and readiness of the accumulator 22 to indicate the selected cell. This signal triggers 66 and re

the horn 73 is set to state O. As a result, a parallel input 41 is connected to the output of multiplexer 74. Next, the first resolution for the elements 70 is formed again by the high level of the clock 9.2 and the accumulator 22 is written to the register 75 on the falling edge of the same clock,

Unlike drives 22 and 23, connected to the bus A1 in the second half-cycle (with a low clock signal), connection of drive 1A occurs in the first half-cycle. Therefore, when the content of accumulator 14 is indicated by a low-level result on input 2., the sync pulse 9.2 is inverted. As a result, an entry in register 75 occurs. already on the leading edge of this sync pulse, t, e, in the first half-cycle.

Register k addresses. The structure and the process of converting a parallel-serial code to a parallel one is similar to register 3. However, parallel input occurs via a clock signal 9.1, which records on the front at the end of the first semitact. When the result is displayed from accumulator 1A by a low level signal 2.k, trigger 83 is set to 1m and signal 7.2, unlike register 3, writes to register 86 from a parallel-serial input by signal 7.2 only in the last tetrad.

Block 5 automatic download. The unit controls the automatic entry of messages into the device. The operation of the block is illustrated by the transition diagram in Fig. 8, which shows the use case of the bit for accumulator 22 and input 16, respectively, equal to 20 and 1b-bit. In this case, the sizes of the fields ГБ and D2t are chosen equal to 8 and 12 bits. The initial state of the loader is S0, which is maintained at a high level at input 11.2. With the appearance of a low level there begins a serial conversion of a parallel code at input 16 to a parallel-serial code at the output of switch 7. This conversion is done with the purpose maximum use of the circuits that are involved in manual input from the keyboard 1. To describe the output functions 5, it is convenient to convert the transition diagram to a phase portrait (FIG. 9), where one of the coordinates forms the F 16.1 subaddress, and the other with allowed to stand S. of transition diagrams, and where the b ... 5 - features

corresponding to the buttons 56 Mode, 53 Address, This, 57 Start at 1, 58 Start counting, X ,, Xe. and X are the microcommands for connecting the first, second and third tetrads from the input input fields DD, C is the blanking flag (set to state 1) of the trigger 8, P is the sign of issuing an unconditional receipt, P is the sign of issuing a delayed receipt according to the condition that the content is transferred from register 3 to drive 22; q d and are the submodes corresponding to the input and output of a message. The operation of block 5 will be considered first when entering a message. When the second word of the message appears (next to the address word A1) and containing the F 0 subaddress, the Mode command (point t in FIG. 9) is sequentially set to 1m code corresponding to the submode (te); Address (t) commands, micro-commands for connecting the first (t), second (t; §), and third (tfc) tetrad of the initial address of the Academy of Sciences, the Given command and the nx (ty) receipt tag. After receiving a receipt from the device in question, the source of the message establishes at input 16 the next word with subaddress F 2 that accompanies the DJ field. This field is successively entered into register 3 by tetrad (tb and tg), after which again by unconditional receipt n the source of the message establishes a new word with field D and subaddress C 3. With the input of this word (tjjj, tfl, tjQ register 3 is completely Next, the Start command is formed at the address (and then the Given command and conditional receipt flag). After the input to drive 22 from register 3 is completed (trigger 8 is in the O state), based on the sign Hg, block 11 generates receipt, message source sets at input 16 the next word with the D field, the first (tg) and the second (tg) tetrads are entered into the register 3 from the Oi’s floor and an unconditional receipt is issued according to the sign of P c. After the source has set the message, the words with the DJ field will be received as well as all subsequent The fields DЈ (K ;. 2) will occur along the new path - tf t and. The choice of this path is due to the fact that at its end it is required instead of the b4 command Start at the address to execute the bg TlycK counting command. When data is entered each time point t passes, trigger 8 is extinguished. This is due to the fact that this trigger is synchronized by pulses with a frequency reduced in comparison with the clock frequency at the source of the message K times. As a result, if quenching is not performed, then at the subsequent reaching of points Q4 or, receipts will be issued prematurely, when register 3 still contains uncounted old contents and which will be erased when the new word is entered from the message source.

If the device automatically prints messages at the request of the message source, then the operation of block 5 starts according to the subaddress F 1 from the point tgg in which the Mode code is set. Next, code 2 is generated (tc, after which it is sent to the tetrado (the t and t are entered in the register k are the initial Lie address. At point 1, a receipt is issued according to the sign, according to which the source of the message is set at input 16 the third state and block 5 is at the point t and after a clock cycle at input 11.2, the blocking signal of the outputs of ROM 88 appears high. In this state, multiplexer 7 connects block 1 to its output.

The coding of the states SK in block 5 is performed according to Table. , and the encoding of the output functions of ROM 88 - according to the table. 5, where the output 1 corresponds to the three-digit code of the next state S, output 2 - to the two-digit channel selection code in multiplexer 98, output 3 - to the type of tetrad entering the switch 7, J

Block 6. The block stores the mode code and decrypts it. The fourth bit in register 89 in state 1 sets the stop sign after the message is output to the system by switching to step-by-step synchronization. When the device is initially installed, this feature is masked with the help of trigger 90 and element 92, and they become effective only after the first start-up of the device, carried out by the signal 12.1 (otherwise the device will not start).

Block 9 internal synchronization. The block forms two synchro-sequences (outputs 9.1 and 9.2), the second of which is shifted from the first by a quarter of the period. Depending on the level at input 31.6, the frequency of these sync pulses can take two values f / 2K and f / 2, where f is the frequency of the master oscillator 108, K is the division ratio of the counter 104. The reduced frequency is used when the drive 22 is accessed than the accumulator 23.

Block 9 works as follows.

The signal 40, the trigger 101 is set to state 1 and the output of the element 105 appears pulses from the generator 108. If the input 31.6 has a sign of increased frequency (low level), the trigger 100, and with it the counter 105, is set to O. At the same time, the output of element 107 is connected to the output of counting trigger 99, which divides the frequency of the generator 108 by two times, and to the output of element 106, the output of trigger 102, which generates a quarter shift in the clock pulse from the output of the same trigger. In the case when the input level 31.6 is high, the output of element 107 is connected to the Nth (H loggK) counter 10, at which the frequency is divided relative to the output of the trigger 99 K times, the output of the element 106 is connected to the output of the trigger 103, which generates a pulse shifted by a quarter of the period relative to the H-th output of the counter 104 At the latter (H-1) -th output is connected to the synchronous input of the trigger 103.

When the button 59 is pressed, the trigger step 101 is set to the state .O. As a result, the input gate used as a single sync pulse appears at the output of the element 105 when pressing any of the buttons of the keyboard of the block 1. In this case, the trigger 101 and the counter 104 will be constantly in the state O.

Display unit 10. According to the states of the counter 105 controlled by the generator 114, the multiplexer 111 sequentially polls the outputs of the registers 3 and 4. The resulting four-bit code is further converted by the encoder 113 into a seven-segment indication code. Selection

For illumination of diffraction indices, a decoder 112 is implemented. If register 3 (4) is inputted from the keyboard of block 1 or from input 16, then initially resolution 3.1 (4.1) turns out to be high resolution, and input 3.2 (C.2 ) state 1, which leads to the blocking of the decoder 111 at the moment of daylong polling of register 3 - (4) and, accordingly, to the prohibition of illumination of the corresponding digital digits in. block 10. As the next tetrads are entered into the 3 (4) register, low levels appear on the corresponding inputs of the multiplexers 109 (110), and the corresponding digitizing numbers light up.

When operating in submode 6j, after filling in accumulator 14, input level 13.1 turns out to be low and, accordingly, the output level of multiplexer 109 when reading register 4 is high. Since inputs 4.2 and 4.3 have low levels, this causes a high level element 117 and the blanking of all digital digits in block 10. Pressing the button 55 The result leads to the appearance at input 2.10 of a low level and illumination of the M th address digital address, which will indicate the cell number in the accumulator 14 according to the pressed button 52.

Unit 11 of communication with the subscriber. The operation of the block is illustrated by the transition diagram in FIG. 15, where X / is the request to enter a message into the accumulator 22,. - a request to enter a message into the accumulator 14, QC, and signs of active and passive sub-modes of the system control, P - a sign of a pause (end of the message), S - the state of block 11.

State S is footed by register 123 and encoded according to Table. 6, where 04 and states at outputs 1 and 2 of register 123. A request X occurs if, with its own device number equal to H, and dialed by toggle switches at inputs A of multiplexer 120, the state H1 appears at the input HX of the same multiplexer. Additional conditions during the formation of the query X are the absence of a sign of employment at the input-output 18, as well as the presence of a low level marker 15 in one of the T bits. The last requirement eliminates the incorrect recognition of the third state at the input 16 as device numbers in the address word. Additional conditions are fed to the input of the element 124, which controls the building input of the multiplexer 120, at the output 4 of which the request a is highlighted.

When working on request X, the device’s own H number is set in register 3 and fed to the block at input 19.2. In addition to the additional conditions involved in generating a Chl request, two more conditions are used to allocate a Chl request — a sign of the submodes V, which comes in at input 6.6, and the presence of a low receipt level at input-output 17. The last condition is necessary when there is a delay in receipt the subscriber unit and the communication unit 11 as a result must remain in the S0 state, since otherwise the device in question will accept the address word as a request. The resultant condition is formed by element 125, which controls the gate input of multiplexer 121, which generates the query X.

A pause P is generated by a low level at the output of element 133 in the presence of a third state in the bits of marker 15, as well as in sub address F, acting at input 16, a receipt is generated in states 5 and S, and also at the moment of transition to these states . At the moment of transition to the S / state (and Sj, the permission to form a receipt is removed from the output of element 128, in the Sg state, this permission is obtained by element 129, and in state 5 it occurs either when a low-level indication is applied to input 5.3, (or at the simultaneous appearance of a high level of the character P & at input 5.4 and a low level of the sign of the end of the recording entering input 8. If the state sl is set to the submode M t ° at input 6.6, a high level is applied, masking the condition at input 8 and allowing the formation of a receipt immediately pic In the states Sd and S, the low level establishes through the element 136 at the input-output 18 a sign of busy line. The presence of this feature prevents other devices from communicating with both the device in question and with other devices connected common line with inputs 15-18. If the address word A1 at input 16 has the NJ: 1 sign (H is the own number of the device in question), then the output A of multiplexer 120 is a low-level request for the formation of the Start command is countable. In this case, block 11, if there are no X4 requests.

or XQ., remains in the So state. 10 turns into S or S

The gateway to the initial state S0 occurs at the initiative of the source of the message, which, after transmitting the last word, sets a pause P at the inputs 15 and 16 (third state).

Block 12. The block carries out the formation of the duration and coordination of the fronts of the Start-up commands at the address and the Start-up counting with the device's clock pulses. In this case, in the case of input and water, there is a reference to sync pulses of a lower frequency f / 2K, and when the block 32 is unblocked by the same commands, to the sync mode, an occurrence of 16 working words X at the input, for which the presence of low At least in one of the marker bits at input 15, at the output of element 152, the first resolution for counter 149 appears low and the counting resolution for counter 148. When arriving next, each new data that appears with the same frequency as sync pulses from output 21, soda Římov counter 148 will successively decrease by one. When the counter 148 is reached

pulses of increased frequency f / 2. Choice 25 Oh, transfer output

bridging clock pulses are performed by element 1.46. The identification of the type of launch — input (output) or unlocking of the system — is determined by the signs of filling up the accumulator (input 13.1), as well as the sign of step-by-step synchronization (input 6.5). In case of incomplete filling of drive 1, as well as in the case when the Start command

the address is preceded by the initial service, which appears at the exit 13.1 of the transfer,

Oh, the start team at the counting address

40

The setting on input 40 and trigger 90 in block 6 are still in the state

and start

perceived as I / O commands. Otherwise, they are considered unlock commands.

The button 147 performs the start-up of the device (output of the message) without the use of block 1. Starting when it is pressed is the same as starting from input 2.8. Additionally, at the output of element 144, a switching signal is generated for the inputs in multiplexers 25 and 26, the first of which connects to its own output terminal 39, and the second to the output of storage device 22.

Selector 13. The block selects from the end of the accumulator 14 operating at the input 16, which is a sign of the complete filling of the accumulator 14, blocking the output of a continuous series of clock pulses in block 32. Output 13.2 directly sets the address of the record.

Drive 14. It is a dual-address RAM with independent read and write processes (such as IC 45 CR1802IR1).

Block 31. The operation of the block is explained / by the transition diagram in FIG. 22, rd and M) 2. submodes of control, input and output of a message, 1 - prize of the end of the message, t - sign of a free highway, Z l and Z Ј - Start command at address and counting, g - sign of reaching the A0 address of the clock stop, S f. block.

the controllable sequence of the data to be entered into the accumulator 14. The initial installation of the selector is performed by the Start command at the address entering the low level.

there is input number 12.1, which in the counter 148 from input 19-1 records the number H of the initial element in the controlled sequence. Counter 149 before this signal 40 is set to state O. The operation enable is set to high level at input 11.1 when communication unit 11

turns into S or S

With the appearance at input 16 of the working words X, for which the presence of a low level at least in one of the marker bits at input 15 is necessary, the output of element 152 is low the first resolution for counter 149 and the resolution for counting 148. When you receive each new data that appears with the same frequency as the sync pulses from output 21, the contents of counter 148 will be sequentially reduced by one. When the counter 148 is reached through the NOT element 153, a transfer is prohibited at the transfer input of this counter, which stops further state changes in the counter 148 and sets the second resolution low level for the input of the element 150 to counter 149. Now for each new given counter 149 will increase its state by one. With

which is a sign that the accumulator 14 is completely filled, the output of the continuous series of clock pulses in block 32 is blocked. Output 13.2 directly sets the address of the record in accumulator 14.

Drive 14. It is a dual-address RAM with independent read and write processes (such as IC KR1802IR1).

Block 31. The operation of the block is explained by the transition diagram in FIG. 22, where M) 2. submodes of control, input and output of the message, 1 - sign of the end of the message, t - sign of the free highway, Z l and Z - Start command at address and counting, g - sign of reaching control stop address A0, S k. - block status.

The initial state of the block is S. In it, the contents of register 3 are copied in register 26. The command Z / makes a transition to the state S, in which

The contents of register 26 are rewritten to counter 27. In the next cycle, if the submode is set to 0 or C, it returns to the $ 8 state or goes to the S & for other submodes.

In state 8p, block 31 can go directly by the command of this state, the address in counter 27 is incremented by one, the contents at the selected address are rewritten into drive 23 and simultaneously written to register 3. As for

nor 8, in the next cycle in the submodes 15max and (4 returns to So, in the other submodes there is a delay in the SQ state, in which each cycle contains a sequential rewrite of the contents from the accumulator 22 to the accumulator 23. The sign of the end of the message leads to transition to the 84 state. In the states So, 84, 8, the frequency of the clock pulses 9.1 and 9.2 B20

The SK states are formed by register 16 and their codes are assumed to be equal to K. The following states are formed in ROM 167 according to the table. 7. ROM 168 (Table 8) is used to decipher register states as well as to obtain transition condition numbers, which are analyzed when determining the next state 3i. In this case, the conditions Z-f and Ze are fed to the inputs 12.1 and 12.2, h Chg to the input 6.1, - to the input 6.2, g - to the input. 28, 1 - to the input 29.1

In the process of monitoring the system, when the internal message has already been output, block 31. has returned to the initial connection Zo and drive 1 is full,

A call to the slow drive is coming. 22.

In the state 84, the counter 27 is again rewritten from register 26 to start lowered, since in them the pro 25 unit 32 is blocked.

Pressing the button 57 or 58 unlocks the block 32 and resumes issuing the clock to the system. However, restarting block 31

address of the message. The transition to the next-30 will not occur in this case, since the current state 8 is carried out in the presence of the sign t 1 of the free highway.

In the 5 $ state, the block 3.1 controls the output of the message from the accumulator 23 to the 35 system until the occurrence of the sign 1 end. In the submode c, when the address of the control stop (g 1) is reached, a switch occurs to the state Sg ,.

In the S & S state, starting from the next clock cycle after the transition to it, the output of sync pulses to the system stops. If it is necessary to continue further work in steps by pressing the button 58 Start counting (Z0) occurs 45

the occurrence time of signals Z 4 and Ze at input 13.1 will be affected by a low level signal holding register 16A in state S0. The same blocking of the start of block 31 occurs when the button 58 is pressed again in modes having state 1 in the fourth section of the code. The device operates in the standby mode by signals similar to Z g g and entering block 31 at input 11.3.

System synchronization unit 32. The block generates sync pulses for other devices of the system, as well as for clocked circuits of the device in question, receiving information from the system. The clock pulses are generated from the signals of block 9 using a controllable power amplifier 181. In the control process, a continuous series of sync pulses occurs at certain points in time, instead of which, burst or single sync pulses are output at the block output. The formation of packs occurs in the submodes bv and 0d of system control, when, after filling in accumulator 1 by the signal 13.1 of transfer, trigger 177 passes

transition to state S, in which counter 27 increases its contents by one, after which the next cycle automatically returns to state Sg,. As a result, at each transition in Sg, only one sync pulse will be generated in block 32, on the positive front of which a new word will be written to register 30. If, after an increase in the state 8E of the content of the counter 27 per unit, at the output of the accumulator 23 a sign of end 1 appears, then the state S0 returns. In the case of the EU

24

0

If the Start button at the address (2) is pressed in state 8b, a transition to state 87 occurs, in which the rest of the message is displayed automatically and then, on grounds 1, block 31 returns to Sp.

The SK states are formed by register 16 and their codes are assumed to be equal to K. The following states are formed in ROM 167 according to the table. 7. ROM 168 (Table 8) is used to decipher register states as well as to obtain transition condition numbers, which are analyzed when determining the next state 3i. In this case, the conditions Z-f and Ze are fed to the inputs 12.1 and 12.2, h Chg to the input 6.1, - to the input 6.2, g - to the input. 28, 1 - to the input 29.1

In the process of monitoring the system, when the internal message has already been displayed, block 31 has returned to the original connection - that is, Zo and drive 1 is full,

0 While this does not happen, because

five

0 5

Q

five

the occurrence time of signals Z 4 and Ze at input 13.1 will be affected by a low level signal holding register 16A in state S0. The same blocking of the start of block 31 occurs when the button 58 is pressed again in modes having state 1 in the fourth section of the code. The device operates in the standby mode by signals similar to Z g g and entering block 31 at input 11.3.

System synchronization unit 32. The block generates sync pulses for other devices of the system, as well as for clocked circuits of the device in question, receiving information from the system. The clock pulses are generated from the signals of block 9 using a controllable power amplifier 181. In the control process, a continuous series of sync pulses occurs at certain points in time, instead of which, burst or single sync pulses are output at the block output. The formation of packs occurs in the submodes bv and 0d of system control, when, after filling in accumulator 1 by the signal 13.1 of transfer, trigger 177 passes

sixteen

state 1 and closes amplifier 181. Subsequent presses of buttons 57 and 58 cause a low level at the inputs of element 179i to return the trigger 177 to state O and restore resolution at the input of amplifier 188. Since in the next cycle at the output of the unit 32 through the clock, the counter in the selector 13 will go to the state O, the blocking signal at input 13.1 will also disappear and the trigger 177 will remain as before O. As a result, the block 32 will form a burst of clock pulses, the end of which will be determined by the repeated moment The accumulator 1 and the corresponding occurrence at input 13.1 of the blocking signal. In the event that block 31 goes to the Re state when a message is being output from the accumulator, the prohibition is low at input 31.5 and the output of the clock pulses from the next clock cycle stops. Subsequently, each pressing of the button 58 will lead to the disappearance at the input 31.5 of the sign of the ST state not one cycle and, accordingly, to the formation by the block 32 of a single clock pulse. The same single sync pulses occur when the state mode code 1 is set in the fourth bit. Here, the first pressing of button 57 causes the trigger 177 to be set to state O. After block 31 returns to state 30, each pressing of button 58 (output 12.10 unlock unit 32 for the duration of one clock cycle.

Block 33. The block controls the counter 27 in the process of outputting information from accumulator 23. The operation of the block is illustrated by the transition diagram in Fig. 25, where X {and X are respectively the sign of the beginning and the end of the cyclically repeating part of the message ( inputs 29.2 and 29.3), the sign of exit from the cycle, S - the state of the block. The SK states are generated by register 18 and are encoded according to Table. 9, where X and the states at outputs 1 and 2 of the register.

The initial state is S, into which the block is initially set by a reset signal on input 0. In this state, if input 3.1 has a response from the subscriber to receive the current message word using ROM 187 at output 33.2, a high level

0 0 5 o

about 5 Q

five

The resolution of the count for counts is 27. After entering X on a cyclically repetitive part of the message, the ROM 187 generates at the outputs 2 and low signals the preset signals of the counters 185 and 1%. In this case, depending on the type of sub-mode, the values of K1 or L1 are set in the counter 185, and in the counter 186 - the values of K2 or L2 are set. These values are preprogrammed by the low level signal 31.3 to register 183.

After block 33 transitions to state S, ROM 187, depending on the type of sub-mode and current states of output transfer in counters 185 and 186, generates transition signals for the latter, according to which the counters change state by one or it remains old. When a sign of the end of the cycle appears and goes to the state if the last cycle reaches the output 8 of the ROM 18 /, the exit sign Xj is formed from the cycle, and at the output 6 a low level indicates an increase in the state in the counter 27 by one. If the state Sg. the last cycle has not yet been reached, then the next cycle returns to the S4 state. The following states are formed for the register by the multiplexer 188. The output states in the ROM 187 are encoded according to the table. 10, where the low levels at outputs 1 and 3 correspond to the counting resolution signals, and at outputs 2 and k to the preset signals of counters 185 and 186, low levels at outputs 6 and 5 to the counting and preset resolution signals in counter 27, low levels at output 7 - setting of the third state on the output 36 selected for the output, low level at the output 8 - sign.

Exchange control unit 3k. It controls the third state at output 36i, as well as writing to register 30. The third state is controlled by the state of flip-flop 191i, initially set by a reset signal on input 0 to state 0m. Transition of ilok 31 to states 85, S, and S7 (high level at input 31-7) in the absence of other sources at the selected output of the message (high level at

input 36.N + 1) causes trigger 191 to go to state 1, which connects register 30 through block 36 to output 36 ... If work occurs in submode P, then when a sign of interruption appears at input 33.3, trigger 191 during the time of action of this feature with a delay per clock, it returns to the state O, thereby disconnecting the register 30 from the output ZBk.

Trigger 192 is used to control writing to register 30, transition 10

pulse 21 enters state I1,1, which in the next cycle causes a delay in changing the state in the register 30 and in the counter 27. If a receipt arrives, trigger 192 on the reset input confirms or sets the state O.

E 1, 3ji 0. Situation corresponds to the case of the transfer of the last word of the message, or interruption by the input signal 33.3. As a result, the element 196 is closed and on the falling edge of the clock pulse 21 flip-flop 192

in which the dependencies are executed — J5 returns to state 1, blocks

ti from the current and next states of the trigger 191 and the presence of a receipt at the input 36.N + 2. The cases that arise in this case are grouped into four situations, EO, E0, where E and E / | - current and next state of flip-flop 191 Since both current and next ticks trigger 191 is in state O, in which register 30 is disconnected from the output of the ETA, the record in this register and the change of state in counter 27 must be absent. This is ensured by creating a ban on the input of element 196 on state E. As a result, on the falling edge of clock pulse 21, trigger 192 confirms its state 1 and in the next clock cycle element 197 will remain open.

EO, E 1. Here, in the next clock cycle, a register 30 must occur. Since this will be the first exit to the highway, a receipt from the subscriber device is not required to install new content in register 30. This is ensured by the creation of a state at the input of element 195 and the creation by state E of the input of element 196. As a result, at the output of element 195 the level is low, the trigger 192 will go to state O and in the next clock cycle element 197 will pass a sync pulse, which will register a new word in register 30, and the contents of counter 27 will increase by one.

E 1, E | 1. In this situation, both elements 195 and 196 are open. As a result, if in the second half of the clock cycle the low level of receipt 36.N + 2 does not come, then element 195 prohibits element 196 and trigger 192 on the falling edge of the sync

pulse 21 enters state I1,1, which in the next cycle causes a delay in changing the state in the register 30 and in the counter 27. If a receipt arrives, trigger 192 on the reset input confirms or sets the state O.

E 1, 3ji 0. Situation corresponds to the case of the transfer of the last word of the message, or interruption by the input signal 33.3. As a result, the element 196 is closed and on the falling edge of the clock pulse 21 flip-flop 192

0

0

five

five

five

In the next cycle, the states are changed to 27 and 30.

The switchboard 36. The output direction (output port) is stored in register 200, where it comes from the address word A1. If the message is addressed to one subscriber, the record in register 200 is made at the moment when the address word placed first in the message appears at the output of accumulator 22. In the event that the information in register 200 additionally changes whenever the word pause with C 1 ... 1 appears in the drive 23. These pauses can occur in the S, Sft and S-y states of the block 31. The demultiplexer 201 connects the output signal to the 3.2 input signal

the register 30 moves to one of the device outputs 36t depending on the output number specified by the register 200. The multiplexer 202 samples the busy signals and the receipts from the selected subscriber devices.

On Fig shows a timing diagram of the device when typing from the keyboard. At times t (... tf |, input is made in register 3, at instants C.t and fcn + e., Respectively, the Start command is executed at the address and the Start is counted.

Fig. 29 shows a time diagram of the device during automatic input from input 16. A case of entering a message is shown, consisting of address word A1, setup word AH and work words D (and D |. The message appears 5 at time t |; the reception of the tuning word ends at the moment tc, and the working word D. at the moment tg. At the moment the input ends

0

the hister 3 of the work word D and start from block 31 according to the Start command (at, address. At time t, writing to the drive 22 ends, after which the source of the message is disconnected from the device in question.

Fig. 30 shows a timing diagram of the device when a message is displayed. Shown is a three word message output. The launch occurs at time t, and at time tg, the last word is overloaded into drive 23 of 2. In the state, stopping occurs until t3, when the trunk at the output of the distribution switch 3 & K is released. At time tq. the second message word arrives on the trunk, after which, according to the source status of the message, the change of information in register 30 is delayed until t5, when a delayed receipt arrives at the device.

Claims (1)

Invention Formula A device for debugging multiprocessor systems, comprising a main drive, a counter, an input block of input data and commands, and a trigger, characterized in that, in order to increase the reliability of work by organizing real-time monitoring, an input control block, data registers and addresses are entered into it , mode storage unit, boot unit, first and second switches, internal and system synchronization units, display unit, communication unit with debugging object, input synchronization unit, selector, input accumulator, register Return it, first and second multiplexers, the comparison unit. a transition decoder, an output register, a firmware control block, a test information output cycle organizer, an exchange control block, a pause decoder and a buffer accumulator, the first output of the input control block connected to the first synchronous input of the address register, the second output to the first synchronous input of the data register and the display unit, the third output - with the write input of the display unit, the fourth output - with the reset input of the data register, the fifth output - with the write input of the storage unit of the mode, the sixth output - with the first synchronous input The input synchronization block, the seventh output with the second synchronous inputs of the data and address registers, the eighth output with the address input of the internal synchronization unit, the first input of the input control unit is connected to the first output of the first switch and the first information inputs of the address and data registers and the storage mode, the second command input of the input control unit is connected to the second output of the first switch, to the clock input of the internal synchronization block and to the second information inputs of the address register and the block is stored and the mode, the third command input of the input control unit is connected to the third output of the first switch, the first group of data inputs of which is connected to the output group of the input block, the second group of data inputs of the first switch is connected to the group of information inputs of the input drive and is to the backbone of the microprocessor system, the first subgroup of the device data input group is connected to the data input unit of the automatic loading unit, and the second subgroup the device data input groups are connected to the first group of data inputs of the communication unit with the subscriber, the control inputs of the automatic loading unit, the first switch, the comparison unit are connected to the first output of the communication unit with the subscriber, the synchronous input of the first switch is connected to the synchronous inputs of the exchange control unit , the communication unit with the subscriber, the automatic loading unit, the input accumulator of the selector and the first output of the system synchronization block, the fourth data input of the switch is connected to the first output of the automatic block oh loading, the second output of which is connected to the first input of the block. communicating with the subscriber, and the third output of the automatic loading block with the trigger data input, the synchro rotor of which is connected to the second synchronous input of the input synchronization block, with the write inputs of the buffer, main and input accumulators, the first synchronization inputs of the firmware control block and the block of output test information cycles, with the third synchronization input of the address register and the first synchronization inputs of the second switch return register and connected to the first output of the unit internal sync 3116M reset, the trigger reset input is connected to the first output of the firmware control unit, the trigger output is connected to the second inputs of the communication unit with the subscriber and the data register, the third synchronous input of the input synchronization unit is connected to the second output of the internal synchronization unit and the synchronous input of the system synchronization unit, the first input of the synchronization unit input is connected to the first output of the mode storage unit, the first input of logic conditions, the firmware control block and the first input of the system synchronization block, in The second input of the input synchronization block is connected to the first input of the display unit, the second input of the logic conditions of the firmware control unit, the second input of the system synchronization block and the first output of the selector, the first output of the input synchronization block is connected to the third input of the logic conditions of the firmware control block and the third input of the system control block synchronization, the second output of the system synchronization unit is connected to the third input of the mode storage unit, the fourth input of the logic conditions of the microprogram frame control and the fourth input of the system synchronization unit, the third output of the synchronization unit, the gadfly is connected to the control inputs of the first and second multiplexers, the first input-output of the communication unit with the subscriber is the input-output of the device for connecting to the bus of the microprocessor system bus, the second input-output of the communication unit with the subscriber is the input-output of the device for connecting the bus receipt of the microprocessor system bus, the third input of the communication unit with the subscriber is connected to the second output The storage unit of the mode, the fourth input of the communication unit with the subscriber is connected to the first control input of the selector and is a marker input of the device for connecting to the microprocessor system bus, the group of data register outputs is connected to the group of data inputs of the display unit and the group of data inputs of the main drive, moreover, the first, second, third and fourth subgroups of the group of outputs of the data register are connected respectively to the group of inputs of the selections 32 five 0 five 0 five 0 five 0 five the second group of inputs of the communication unit with the subscriber, with the input group of the output test cycles block and with the input group of the comparison unit, the second output of the communication unit with the subscriber is connected to the second control input of the selector, and the third output of the communication unit with the subscriber is with the fifth input of the logic conditions of the microprogram control unit, the second address input of the internal synchronization block is connected to the second output of the microprogram control block, the read inputs of the main and buffer synchronization accumulators, the third output block internal synchronization is connected to the third synchronous input of the data register, the second synchronized input of the return register, the clock input of the counter, the second synchronized input of the test information output cycle block, the second output of the selector is connected to the enable input of the input accumulator, the output register group of the address register is connected to the address input group of the display unit, first a group of data inputs of the first multiplexer and a group of address inputs of the input storage unit; the data output group of which is connected to the data input group of the register d data, with a group of data outputs of the main and buffer accumulators, a group of inputs of the output register and a transition decoder, the first and second subgroups of the data output groups of the input storage device are connected respectively to the second data input group of the first multiplexer and the first data input group of the second switch, the input group address register data is connected to the counter output group and to the second group of data inputs of the comparison unit and the second multiplexer; the synchronous input of the address register is connected to the third output microprogrammed control unit, with the fifth input of the system synchronization unit and with the synchronous input of the return register, the address register output is connected to the second data input of the display unit, the third data input of which is connected to the data register output, the fourth output of the input synchronization block is connected to the fourth input of the storage unit , the sixth and seventh inputs of the logic conditions of the firmware control block are connected respectively to the second and the third output of the mode storage unit, the fourth and fifth outputs of which are connected respectively to the first input of the test information output cycle block and the main storage mode inputs, the eighth input of the logic conditions of the microprogram control unit is connected to the output of the comparison block, the ninth input of the logic conditions of the microprogram control block is connected with the first output of the transition decoder and with the first input of the exchange control block, the tenth input of the logic conditions of the firmware control block is connected to the second input of the exchange control unit and the first output of the second switch, the fourth and fifth outputs of the microprogram control block are connected to the write and enable counts of the counter, respectively, the sixth output of the microprogram control block is connected to the second syncro inputs of the return register and the second switch, the seventh output of the block firmware control is connected to the second input of the main storage mode, the eighth, ninth and tenth high 15 20 25 the second switch, the third output of which is connected to the fifth input of the exchange control unit, the first output of which is connected to the sixth input of the test information output cycle block, the first and second outputs of which are connected respectively to the reset input of the counter and the fifth input of the exchange control unit, the group of outputs of the return register is connected to the group of information inputs of the counter, the second and third outputs of the exchange control block are connected to the synchronous input of the output register and the control input of the third state of the second comm respectively, the output of the pause decoder is connected to the sixth input of the exchange control unit and the enable input of the second switch, the first group of data inputs of which is connected to the input group of the pause decoder and output output register group, and the reset input of the input control unit is connected to the reset inputs of internal and system blocks synchronization, reset inputs of blocks of output of test information, control of exchange and storage mode, the strokes of the microprogram control block of the microprogram control and They are connected respectively to the third synchronous inputs of the second switch, exchange control unit and the second input of the test information output cycle block, the third input of which is connected to the second output of the transition decoder, the third output of which is connected to the fourth input of the test information output cycle block, group informational inputs of which are connected to the output group of the first multiplexer, the fifth input of the block of output of test information 35 40 input synchronization, selector and is the input of the initial setup of the device for connecting to the firmware line of the firmware system, the fourth and fourth outputs of the second switch are information outputs of the device for connecting to the microprocessor trunk, the second and third groups of data inputs of the second switch are a group of receipts inputs and a group of entrances of a device for connecting to the microprocessor system trunk, the third address input of the internal block connected to the fourth input of the control unit; synchronization is connected to the output of the exchange forwarding and to the second output switch. 0 five the second switch, the third output of which is connected to the fifth input of the exchange control unit, the first output of which is connected to the sixth input of the test information output cycle block, the first and second outputs of which are connected respectively to the reset input of the counter and the fifth input of the exchange control unit, the group of outputs of the return register is connected to the group of information inputs of the counter, the second and third outputs of the exchange control block are connected to the synchronous input of the output register and the control input of the third state of the second comm respectively, the output of the pause decoder is connected to the sixth input of the exchange control unit and the enable input of the second switch, the first group of data inputs of which is connected to the input group of the pause decoder and output output register group, and the reset input of the input control unit is connected to the reset inputs of internal and system blocks synchronization, reset inputs of blocks of output of test information, control of exchange and storage mode, five 0 input synchronization, selector and is the input of the initial setup of the device for connecting to the firmware line of the firmware system, the fourth and fourth outputs of the second switch are information outputs of the device for connecting to the microprocessor trunk, the second and third groups of data inputs of the second switch are a group of receipts inputs and a group of entrances of a device for connecting to the microprocessor system trunk, the third address input of the internal block switch. 37 Table 6 38 Table 16MY5 Table 9  0a s, o o s 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